[all-commits] [llvm/llvm-project] c2f10e: [DAGCombiner] Fold multiplication through vp_merge...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c2f10e00aea9aad66f3a7298e411a4721f53e93e
      https://github.com/llvm/llvm-project/commit/c2f10e00aea9aad66f3a7298e411a4721f53e93e
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-06-25 (Thu, 25 Jun 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-sdnode.ll

  Log Message:
  -----------
  [DAGCombiner] Fold multiplication through vp_merge into `partial_reduce_*mla` (#205890)

DAGCombiner is already doing this right now:
```
partial_reduce_*mla(acc, sel(p, mul(*ext(a), *ext(b)), splat(0)), splat(1))
   -> partial_reduce_*mla(acc, sel(p, a, splat(0)), b)
```
We should be able to have drop-in support for vp_merge (not for
vp_select though) as the select in the pattern above. This patch adds
such support.

The test is checking whether RISC-V's Zvdot4a8i instruction is
generated, as it depends on this pattern to fold away not just the
multiplication but also the sign / zero extensions.



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