[all-commits] [llvm/llvm-project] 36b204: [X86][APX] Implement push+push2+push pre-alignment...

[Feng Zou via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 36b204896a513569c1460640f5cc6fe9714a16d0
      https://github.com/llvm/llvm-project/commit/36b204896a513569c1460640f5cc6fe9714a16d0
  Author: Feng Zou <feng.zou at intel.com>
  Date:   2026-06-26 (Fri, 26 Jun 2026)

  Changed paths:
    M llvm/lib/Target/X86/X86FrameLowering.cpp
    M llvm/lib/Target/X86/X86MachineFunctionInfo.h
    A llvm/test/CodeGen/X86/apx/nf-stackadjust.ll
    M llvm/test/CodeGen/X86/apx/pp2-with-stack-clash-protection.ll
    M llvm/test/CodeGen/X86/apx/push2-pop2-cfi-seh-v3.ll
    M llvm/test/CodeGen/X86/apx/push2-pop2-cfi-seh.ll
    M llvm/test/CodeGen/X86/apx/push2-pop2.ll
    M llvm/test/CodeGen/X86/apx/win64-abi.ll
    M llvm/test/CodeGen/X86/win64-eh-unwindv3-push2pop2.ll

  Log Message:
  -----------
  [X86][APX] Implement push+push2+push pre-alignment strategy for PP2 (#205031)

Replace the dummy "push %rax" stack-alignment padding for APX push2/pop2
(PP2) with a push+push2+push strategy: when an even number of callee-saved
GPRs is involved, a single CSR push provides the 16-byte alignment instead
of a throwaway push %rax, and the remaining registers use push2/pop2. The
padForPush2Pop2 flag and its associated dummy push, SUB/LEA padding, and
SEH_StackAlloc emission in spill/restoreCalleeSavedRegisters are removed.

BuildStackAdjustment now uses NF (no-flags) variants of ADD/SUB, but
only as a smaller replacement for LEA, i.e. only when EFLAGS must be preserved
across the adjustment. When EFLAGS is dead the plain SUB/ADD is kept, which is
  shorter than the EVEX-encoded NF form. The NF opcodes are 64-bit
(SUB64ri32_NF/ADD64ri32_NF), so they are not used for the x32 ABI, and
they are recognized in mergeSPUpdates and the epilogue backward scan.

  Update LIT tests accordingly.

  Assisted-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>



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