[all-commits] [llvm/llvm-project] df49da: [flang][OpenMP] Decompose combined construct selec...
Krzysztof Parzyszek via All-commits
all-commits at lists.llvm.org
Thu Jun 25 14:08:25 PDT 2026
Branch: refs/heads/users/kparzysz/unresolved-critical
Home: https://github.com/llvm/llvm-project
Commit: df49da3201a05f7a2ef78ad00cdcfebe09ae1308
https://github.com/llvm/llvm-project/commit/df49da3201a05f7a2ef78ad00cdcfebe09ae1308
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M flang/lib/Semantics/openmp-utils.cpp
M flang/test/Lower/OpenMP/metadirective-construct.f90
Log Message:
-----------
[flang][OpenMP] Decompose combined construct selectors in variant matching (#205802)
The previous code resolved a `construct={...}` selector by mapping its
name to a trait through a string lookup
(`getOpenMPContextTraitSelectorKind` ->
`getOpenMPContextTraitPropertyForSelector`). That works for a standalone
leaf construct such as `parallel`, whose name matches a single construct
selector string, but not for a combined/composite directive such as
`target teams`: its name (`"target teams"`) matches no selector string,
so the lookup returns `invalid` and the selector's construct traits are
dropped.
This PR adds `AppendConstructTraitsForDirective` that walks the
directive sets and adds each leaf trait, so combined directives are no
longer reduced to a single (or dropped) trait. It also handles the
standalone `dispatch` construct trait.
Fixes https://github.com/llvm/llvm-project/issues/205664
Assisted-by: Cursor
Commit: 0e847869ab8dde02815d82b67c7f0bb834653b51
https://github.com/llvm/llvm-project/commit/0e847869ab8dde02815d82b67c7f0bb834653b51
Author: adams381 <adams at nvidia.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
A clang/test/CIR/CodeGen/new-array-init.cpp
M clang/test/CIR/CodeGen/new.cpp
M clang/test/CIR/CodeGen/paren-list-agg-init.cpp
M clang/test/CIR/CodeGenCXX/new-array-init.cpp
Log Message:
-----------
[CIR] Zero-init array-new with trivial ctor (#205611)
emitNewArrayInitializer hit errorNYI for a value-initialized array new of
a trivially-constructible element (new T[n]()), where the trailing
parentheses mean zero-initialization. Route the trivial-ctor branch
through the existing tryMemsetInitialization() helper, following classic
CodeGen: a zero-initializable element gets operator new[] plus a single
memset to 0, while a non-zero-initializable element (an array of
pointers-to-data-member, whose null value is -1) declines the memset and
falls through to the constructor loop value-initializing each element.
Also add the getParent()->isEmpty() early return. tryMemsetInitialization
builds the memset through the Address overload of createMemSet so the
destination alignment is preserved.
Found building the SPEC CPU 2026 LLVM benchmark (723.llvm_r / 823.llvm_s)
with ClangIR.
Commit: d3c00bf7b08c3746c6e62c56d6142c333b0a8d25
https://github.com/llvm/llvm-project/commit/d3c00bf7b08c3746c6e62c56d6142c333b0a8d25
Author: David Zbarsky <dzbarsky at gmail.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/driver.bzl
Log Message:
-----------
Bazel driver-tools build-setting simplification (#205846)
Read the validated `driver-tools` build setting directly in
`generate_driver_tools_def` instead of reconstructing tool names from
selected `CcInfo` dependency labels through `label.name`.
`generate_driver_selects` now returns the selected dependency labels, so
`select_driver_tools` is removed.
This fixes a silent issue when 2 multicall participants have the same
`label.name`.
Commit: fcc105f40c8ee7cd604c3dafb3750e8ee1db65b6
https://github.com/llvm/llvm-project/commit/fcc105f40c8ee7cd604c3dafb3750e8ee1db65b6
Author: Grigory Pastukhov <gpastukhov at meta.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M clang-tools-extra/clang-tidy/misc/ExplicitConstructorCheck.cpp
M clang-tools-extra/clang-tidy/utils/TypeTraits.cpp
M clang-tools-extra/clang-tidy/utils/TypeTraits.h
M clang-tools-extra/unittests/clang-tidy/CMakeLists.txt
A clang-tools-extra/unittests/clang-tidy/TypeTraitsTest.cpp
Log Message:
-----------
[clang-tidy] Move isStdInitializerList to utils::type_traits and add unit tests (#205449)
Moves isStdInitializerList from misc/ExplicitConstructorCheck into
utils::type_traits so it can be shared, and adds unit tests for it. NFC.
Commit: 78247bf69011b35f04e0905b3cea56eab7d7831c
https://github.com/llvm/llvm-project/commit/78247bf69011b35f04e0905b3cea56eab7d7831c
Author: Yonah Goldberg <ygoldberg at nvidia.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/test/Transforms/SROA/struct-to-vector-fp-store-only-tail.ll
M llvm/test/Transforms/SROA/struct-to-vector.ll
Log Message:
-----------
[SROA] Adjust struct layout requirements for struct to vector canonicalization (#201967)
Address a bug pointed out by @bjope (thank you!)
- To perform struct to vector canonicalization, it is not enough that
the struct layout size is the same as the vector layout size, because
structs and vectors may have padding in different locations! Previously
we would promote `{ i5, i5 }` as `<i5, i5>`, which is a miscompile!
- I also relaxed another requirement. Previously we made sure that the
struct layout size is equal to the vector allocation size. This
prevented promoting `{ i32, i32, i32 }` as `<i32, i32, i32>` because the
struct layout size is 3 x i32 but the vector allocation size is 4 x i32.
So instead we should compare to the vector store size, which is 3 x i32.
Commit: d4148a8476dfb63291ca3c63bc92a3bd8a19b773
https://github.com/llvm/llvm-project/commit/d4148a8476dfb63291ca3c63bc92a3bd8a19b773
Author: hulxv <hulxxv at gmail.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
A libc/docs/dev/builtin_compatibility.rst
M libc/docs/dev/index.rst
Log Message:
-----------
[libc][docs] add `builtin_compatibility` (#200539)
Document the built-in compatibility for different GCC versions since
GCC-5
Commit: 4f638ff7baf97dd16abff7fc961d76c22063dc1f
https://github.com/llvm/llvm-project/commit/4f638ff7baf97dd16abff7fc961d76c22063dc1f
Author: khaki3 <47756807+khaki3 at users.noreply.github.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCSpecializeForHost.cpp
M mlir/test/Dialect/OpenACC/acc-if-clause-lowering.mlir
Log Message:
-----------
[mlir][acc] Drop redundant `acc.terminator` erase that broke atomic capture under `if` (#205731)
Example:
```fortran
!$acc parallel if(cond)
!$acc atomic capture
a = a + 1
b = a
!$acc end atomic
!$acc end parallel
```
In this code, the `if` clause triggers host-fallback specialization. A
blanket `acc.terminator` erase pattern strips the implicit terminator of
the still-present `acc.atomic.capture`, so the later `getTerminator()`
trips `mightHaveTerminator()`.
Fix: remove that pattern — every ACC region op already erases its own
terminator when it unwraps/inlines, so it was redundant (and only raced
ahead to break this case). Adds a lit test.
Commit: 04450c8cd86e7bbfab42cbeb919d31d8668366a8
https://github.com/llvm/llvm-project/commit/04450c8cd86e7bbfab42cbeb919d31d8668366a8
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td
M mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir
M mlir/test/Target/SPIRV/ocl-ops.mlir
Log Message:
-----------
[mlir][SPIR-V] Add CL copysign, fdim, fmod and hypot ops (#203880)
Commit: d0373ba8b57bb2355cfed09ad4c15c315a36af8c
https://github.com/llvm/llvm-project/commit/d0373ba8b57bb2355cfed09ad4c15c315a36af8c
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLOps.td
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
M mlir/test/Dialect/SPIRV/IR/gl-ops.mlir
M mlir/test/Target/SPIRV/gl-ops.mlir
Log Message:
-----------
[mlir][SPIR-V] Add GL NMin, NMax and NClamp ops (#203878)
Commit: 4c203981fc40698bca926c9b41c98574648d537f
https://github.com/llvm/llvm-project/commit/4c203981fc40698bca926c9b41c98574648d537f
Author: hanbeom <kese111 at gmail.com>
Date: 2026-06-26 (Fri, 26 Jun 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/WebAssembly/or-reduction-zero-test.ll
A llvm/test/Transforms/SLPVectorizer/X86/reduction-zero-test-ctpop.ll
Log Message:
-----------
[SLP] Add pre-commit tests for zero-tested OR/UMax reductions (NFC) (#205738)
Add pre-commit tests for scalar OR/UMax reductions whose result is
only used by an eq/ne-zero comparison.
Commit: 6d6475328be051b35b22c5e72a0c4aa72c3815c4
https://github.com/llvm/llvm-project/commit/6d6475328be051b35b22c5e72a0c4aa72c3815c4
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/test/SemaCXX/constant-expression-p2280r4.cpp
Log Message:
-----------
[clang][bytecode] Don't ignore discarded `DeclRefExpr`s (#204165)
Check for the evaluating decl in `GetRefGlobal` so we don't fail too
early. We also need to mark the `APValue` as constexpr-unknown when
returning it, even though the backing `Descriptor` is not marked
constexpr-unknown.
This fixes the last differences in `constant-expression-p2280r4.cpp`.
Commit: cf223eb1ec5fd5430a110bbd9f3fc18b46796fa0
https://github.com/llvm/llvm-project/commit/cf223eb1ec5fd5430a110bbd9f3fc18b46796fa0
Author: Moazin K. <mkhatti at nvidia.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
A mlir/lib/Dialect/OpenACC/Transforms/ACCEmitRemarksPrivate.cpp
M mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
A mlir/test/Dialect/OpenACC/acc-emit-remarks-private.mlir
Log Message:
-----------
[OpenACC] Add pass `ACCEmitRemarksPrivate`. (#205824)
The pass emits remarks describing `acc.firstprivate` and `acc.private`
associated with OpenACC compute and loop constructs.
Assisted-by: Claude Code
Commit: 5e85dbcde1d4ca6088132de09a3a95ca99caad17
https://github.com/llvm/llvm-project/commit/5e85dbcde1d4ca6088132de09a3a95ca99caad17
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
A lldb/test/Shell/SymbolFile/DWARF/wasm-function-display-name.yaml
Log Message:
-----------
[lldb] Use the source name when the linkage name is not mangled (#205701)
When a DW_TAG_subprogram has a DW_AT_linkage_name that is not actually a
mangled name and differs from DW_AT_name, lldb used the linkage name as
the function's display name. For C++ the linkage name demangles back to
the source name, but a plain symbol such as __main_argc_argv does not,
so the function showed up under its raw linkage name in backtraces,
breakpoint locations and `image lookup`, and was not findable by its
source name.
This happens on WebAssembly: wasi-libc renames `int main(int, char**)`
to its __main_argc_argv argv-passing wrapper, keeping DW_AT_name "main"
but recording DW_AT_linkage_name "__main_argc_argv".
When the linkage name has no recognized mangling scheme, use DW_AT_name
as the display name and keep the linkage name as the symbol, so lookups
by either name still resolve.
Commit: 469e3e81c6264f61d4369246d498c587b5ac6c71
https://github.com/llvm/llvm-project/commit/469e3e81c6264f61d4369246d498c587b5ac6c71
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-26 (Fri, 26 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
A llvm/test/Transforms/LoopInterchange/transform-stop-partway.ll
Log Message:
-----------
[LoopInterchange] Add test for IR modification stops partway (#205562)
The transform phase in LoopInterchange, which actually modifies the
input IR, has several early exits. This means that if the process hits
one of them, the end result may be IR that has been left in a partially
modified state. As far as I have searched, there is only one case that
actually triggers an early exit. In that case, the final output happens
to be valid IR (though not interchanged), so I believe this is not a
correctness issue at the moment. However, the current implementation is
clearly undesirable, especially because the loop is regarded as
interchanged internally even though the transformation actually failed.
We should eliminate all such early exits.
This patch adds a test that I could find, and also adds a debug output
to make it clear which one is triggered.
Assisted-by: Claude Code
Commit: e87160eddf6d7986423209711878b26f82443009
https://github.com/llvm/llvm-project/commit/e87160eddf6d7986423209711878b26f82443009
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
Log Message:
-----------
[lldb] Fix DWARFASTParserClang formatting (#205857)
In #205701, I applied Michael's suggestion and enabled auto-merge.
Despite the formatter check failing, the change still got merged. Fix
the formatting and another inconsistency in the use of braces.
Commit: f3cb7bbc0110938c78542add1f79364fa526fb8d
https://github.com/llvm/llvm-project/commit/f3cb7bbc0110938c78542add1f79364fa526fb8d
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/benchmarks/CMakeLists.txt
A llvm/benchmarks/ImmutableSetIteratorBM.cpp
M llvm/include/llvm/ADT/ImmutableSet.h
M llvm/unittests/ADT/ImmutableSetTest.cpp
Log Message:
-----------
[ADT] Rewrite ImmutableSet/Map in-order iterator without per-node state (#205552)
ImutAVLTreeInOrderIterator was layered on a "generic" iterator whose
stack stored a 2-bit visit-state (None/Left/Right) packed into the low
bits of each node pointer, and which was spun through several
intermediate states per in-order step.
Replace it with a single iterator that keeps a stack of plain node
pointers (the root-to-current ancestor chain) and recovers the traversal
direction by inspecting whether it is ascending from a node's left or
right child. A node's parent cannot be cached in the node itself because
these trees are persistent and structurally shared (one node may be a
child of different parents across tree versions), so the ancestor stack
is the per-traversal parent chain.
The observable contract is unchanged: same in-order sequence, same
skipSubTree() semantics (so tree canonicalization via isEqual is
unaffected), and the iterator stays bidirectional. operator== now
compares the current node rather than the whole path, which is O(1) and
correct because within a single tree a node has a unique path.
Microbenchmarks (llvm/benchmarks/ImmutableSetIteratorBM.cpp, -O2 with
assertions) show ~2x faster plain traversal and skipSubTree, and the
node-identity operator== is ~1.5x faster on comparison-heavy loops (no
change on the common compare-against-end() path).
| Test (input size) | Before | After | Speedup |
|:--|--:|--:|--:|
| Cycle `N=100` | 64.3 ms | 52.3 ms | 1.23× |
| Cycle `N=200` | 464.5 ms | 375.5 ms | 1.24× |
| Cycle `N=300` | 1540 ms | 1260 ms | 1.22× |
| Merge `N=1000` | 51.3 ms | 44.7 ms | 1.15× |
| Merge `N=2000` | 237.0 ms | 198.0 ms | 1.20× |
| Merge `N=5000` | 1710 ms | 1480 ms | 1.16× |
| Switch fan-out `N=1000` | 73.8 ms | 62.7 ms | 1.18× |
| Switch fan-out `N=2000` | 328.0 ms | 294.2 ms | 1.11× |
| Switch fan-out `N=4000` | 1420 ms | 1260 ms | 1.13× |
Assisted by: Claude Opus 4.8
Co-authored-by: Gabor Horvath <gaborh at apple.com>
Commit: b7c56b5b0a54a6c966a74dfe311fcddcffade521
https://github.com/llvm/llvm-project/commit/b7c56b5b0a54a6c966a74dfe311fcddcffade521
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/lib/Target/NVPTX/CMakeLists.txt
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.h
M llvm/lib/Target/NVPTX/NVPTX.h
R llvm/lib/Target/NVPTX/NVPTXAddressFolder.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrFormats.td
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
R llvm/test/CodeGen/NVPTX/address-folder.ll
R llvm/test/CodeGen/NVPTX/address-folder.mir
Log Message:
-----------
Revert "[NVPTX] Fold symbol addresses into memory operands" (#205852)
Reverts llvm/llvm-project#202379
check-llvm now fails on one of the new testcases
```
Failed Tests (1):
LLVM :: CodeGen/NVPTX/address-folder.ll
```
Commit: 8987645d1d42147340367f6752cac563bf2c64be
https://github.com/llvm/llvm-project/commit/8987645d1d42147340367f6752cac563bf2c64be
Author: Tamir Duberstein <tamird at gmail.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
M llvm/lib/Target/BPF/BPFCORE.h
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/BPF/BTFDebug.h
A llvm/test/CodeGen/BPF/BTF/struct-member-order.ll
A llvm/test/CodeGen/BPF/CORE/struct-member-order.ll
Log Message:
-----------
[BPF] Sort BTF struct members by offset (#205396)
Sort BTF structure elements by their debug offsets. Prevent
source-ordered Rust debug metadata from producing descending member
offsets after rustc chooses a different physical layout, because the
kernel rejects such BTF.
Use the sorted order for member emission, declaration-tag component
indexes, and CO-RE access strings. Keep physical offset calculations on
the original debug indexes so changing BTF order does not change
generated code.
Eliminate the need for the bpf-linker metadata rewrite by enforcing the
ordering in the LLVM BPF backend:
https://github.com/aya-rs/bpf-linker/commit/1007ec7fed03562eb7d08f3e7521094a7e698b95
Commit: aa1cc2dc42733219a91167ca2279c96c1bce58e7
https://github.com/llvm/llvm-project/commit/aa1cc2dc42733219a91167ca2279c96c1bce58e7
Author: Alex Langford <alangford at apple.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/include/llvm/ADT/StringRef.h
M llvm/unittests/ADT/StringRefTest.cpp
Log Message:
-----------
[ADT] Add StringRef::nonEmptyOr (#204690)
This adds a new method to StringRef. The intended use case is for
situations when a non-empty StringRef is needed but some operation
returns an empty StringRef because of missing data or some other
exception.
This is primarily for ergonomics. I'm mainly motivated to avoid creating
a temporary StringRef in situations where a StringRef is obtained
through a long call chain. e.g.
`doAThing(my_obj.getFoo().getBar().getBaz().getStringRef().nonEmptyOr("unknown"))`
---------
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
Commit: 32572205a08d213c6a7cb387fe384fb3d98bca6c
https://github.com/llvm/llvm-project/commit/32572205a08d213c6a7cb387fe384fb3d98bca6c
Author: Alex Langford <alangford at apple.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M lldb/include/lldb/Breakpoint/Breakpoint.h
M lldb/include/lldb/Breakpoint/BreakpointList.h
M lldb/source/Breakpoint/BreakpointList.cpp
M lldb/source/Target/Target.cpp
Log Message:
-----------
[lldb] Change BreakpointList::FindBreakpointsByName to use StringRef (#205695)
It's not possible to turn a StringRef into a c-string safely without a
potential allocation. I will use this in a follow-up to remove
ConstString from BreakpointName.
Commit: eb05efcd9b035b397c907d9949fd225e40173c07
https://github.com/llvm/llvm-project/commit/eb05efcd9b035b397c907d9949fd225e40173c07
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Semantics/program-tree.cpp
A flang/test/Semantics/OpenACC/acc-routine-bad.f90
Log Message:
-----------
[flang][openacc] Ignore bare acc routine in module subprogram part instead of erroring out (#205450)
This small code below would trigger not easy to understand error like
`error: expected 'END'`. Ignore such directive and emit the standard
warning.
```
module acc_routine_bad
contains
!$acc routine
subroutine acc_routine20()
end subroutine
end module
```
Commit: e32a1c6d91a7a4e75a4a890ffdddfda068f8bd33
https://github.com/llvm/llvm-project/commit/e32a1c6d91a7a4e75a4a890ffdddfda068f8bd33
Author: Yusra Syeda <99052248+ysyeda at users.noreply.github.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChains/ZOS.cpp
M clang/test/Driver/zos-ld.c
Log Message:
-----------
[SystemZ][z/OS] Improve link command for shared libraries (#204205)
This PR adds -e/-O CELQSTRT and improves the link command for shared
libs.
Co-authored-by: Yusra Syeda <yusra.syeda at ibm.com>
Commit: 67cc47c7f9f4a0383bc386fdca748d0330a4aaf6
https://github.com/llvm/llvm-project/commit/67cc47c7f9f4a0383bc386fdca748d0330a4aaf6
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/include/llvm/Target/TargetLoweringObjectFile.h
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/Target/TargetLoweringObjectFile.cpp
M llvm/lib/Target/TargetMachine.cpp
R llvm/test/CodeGen/X86/large-implicit-section.ll
Log Message:
-----------
Revert "[x86] Handle implicit sections when determining if a global is large" (#205859)
Reverts llvm/llvm-project#204247
Causes crashes:
https://github.com/llvm/llvm-project/pull/204247#issuecomment-4799229027
Fixes #205801
Commit: bc3eb524b2d1dcc3e48161cd2eb80a2364fdc097
https://github.com/llvm/llvm-project/commit/bc3eb524b2d1dcc3e48161cd2eb80a2364fdc097
Author: adams381 <adams at nvidia.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
A clang/test/CIR/CodeGen/builtin-atomic-is-lock-free.c
Log Message:
-----------
[CIR] Lower __atomic_is_lock_free / __c11_atomic_is_lock_free (#205862)
`__atomic_is_lock_free` and `__c11_atomic_is_lock_free` were routed to
`errorNYI` in CIRGen, so `std::atomic<T>::is_lock_free()` failed to
compile under `-fclangir` whenever the query wasn't constant-folded --
which is what the libcxx atomics lock-free tests hit.
This mirrors classic CodeGen (`CGBuiltin.cpp`): emit a call to the
runtime entry `bool __atomic_is_lock_free(size_t size, void *ptr)`.
`__atomic_is_lock_free` forwards its pointer argument;
`__c11_atomic_is_lock_free` passes a null pointer, since an `_Atomic`
object is always suitably aligned. `__atomic_test_and_set` /
`__atomic_clear` stay NYI.
The lowered call omits the `noundef`/`zeroext` argument and return
attributes classic emits, and the declaration picks up `dso_local`.
That's the existing CIR libcall attribute gap, so the test uses split
`LLVMCIR`/`OGCG` prefixes where the two diverge and a shared skeleton
where they match.
Commit: ebc2f7946ad76daa1c4db18fc9196d94845e6946
https://github.com/llvm/llvm-project/commit/ebc2f7946ad76daa1c4db18fc9196d94845e6946
Author: adams381 <adams at nvidia.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/EHABILowering.cpp
A clang/test/CIR/CodeGen/cleanup-scope-throw-caught.cpp
Log Message:
-----------
[CIR] Fix lost catch clauses on EH landing pads (#205638)
A throw caught by an enclosing handler could call std::terminate instead of
entering the handler. The smallest trigger is a try that destroys a local and
throws a new-expression whose type has a throwing constructor: two cleanups
then sit on the path to the handler and produce two cir.eh.initiate operations
that funnel into one cir.eh.dispatch. The same bug also asserted on ordinary
nested try/catch and dropped the outer handler's catch clause from the inner
landing pad on a nested throw.
ItaniumEHLowering::lowerEhInitiate derived each landing pad's catch clauses
while destructively walking the eh_token graph, tying a correctness property
to lowering order: whichever initiate lowered first tore down the shared cir.br
edges, so the other reached no dispatch and kept an empty catch_type_list -- a
cleanup-only landing pad that resumes past the handler.
lowerFunc now does a read-only walk first. For each initiate it collects every
dispatch the exception can reach (innermost first, preserving nested catch
order) and records the catch_type_list, plus the cleanup clause when a cleanup
lies on the unwind path. Each dispatch is lowered once, after every initiate has
been processed.
Follow-up to #199121, which added cleanup-scope throw handling for the
single-dispatch case.
Commit: ab3d63cc080b767f97a23f4efc6cf109be084679
https://github.com/llvm/llvm-project/commit/ab3d63cc080b767f97a23f4efc6cf109be084679
Author: Shafik Yaghmour <shafik.yaghmour at intel.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M clang-tools-extra/pp-trace/PPCallbacksTracker.cpp
Log Message:
-----------
[Clang-tools-extra] Add missing values to CharacteristicKindStrings (#205455)
Static analysis flagged that we were indexing CharacteristicKindStrings
in PPCallbacksTracker::FileChanged based on the values of
SrcMgr::CharacteristicKind which would access outside array bounds for
some values of the enum. As far I can see all value of the enum are
possible when calling FileChanged and so the array should indeed cover
all values. So I added the missing values to the array.
Commit: 291a2d12fec082a234cb1d800723acdb0fd32f8d
https://github.com/llvm/llvm-project/commit/291a2d12fec082a234cb1d800723acdb0fd32f8d
Author: Teresa Johnson <tejohnson at google.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/test/ThinLTO/X86/memprof-icp.ll
Log Message:
-----------
[MemProf] Make ICP test check compared target more strictly (#201656)
We intend to check that we are comparing to the original uncloned
target, but weren't checking for EOL. Add the EOL check.
Commit: 65d16616f810d22e5bcfa2abe7b769172bc260bf
https://github.com/llvm/llvm-project/commit/65d16616f810d22e5bcfa2abe7b769172bc260bf
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
Log Message:
-----------
[lldb][gdb-remote] Send QSetSTDIOWindowSize for a 0x0 size (#205772)
The client uses a 0x0 STDIO window size as a deliberate signal to the
server that there is no client terminal, so the server should redirect
the inferior's stdio over anonymous pipes instead of a ConPTY (on
Windows).
This is a follow up to https://github.com/llvm/llvm-project/pull/203562.
rdar://178725958
Commit: 99f4b63a79ecbaed60be14fcea05279e8e16e9de
https://github.com/llvm/llvm-project/commit/99f4b63a79ecbaed60be14fcea05279e8e16e9de
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/rotate-add.ll
Log Message:
-----------
AMDGPU: Fix wrong triple in rotate-add test (#205863)
This was overwritten by the command line anyway.
Commit: 7ede8a4c665bb999f35ebc0293dd49812329e2bd
https://github.com/llvm/llvm-project/commit/7ede8a4c665bb999f35ebc0293dd49812329e2bd
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M clang/test/CIR/CodeGen/constant-inits.cpp
M clang/test/CIR/CodeGen/record-zero-init-padding.c
Log Message:
-----------
[NFC][CIR] Fix test that used 'DAG-SAME' (#205867)
'DAG-SAME' isn't a thing in file-check, so these lines weren't being
checked. This patch just puts them all on teh same line as they should
be.
Commit: 5c561a32a5afccb42b2a44f95535dbe6ea939f44
https://github.com/llvm/llvm-project/commit/5c561a32a5afccb42b2a44f95535dbe6ea939f44
Author: Christopher Bate <cbate at nvidia.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M mlir/lib/TableGen/CodeGenHelpers.cpp
A mlir/test/IR/test-successor-verifier.mlir
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/mlir-tblgen/constraint-unique.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Log Message:
-----------
[MLIR] Fix broken 'Successor<CPred<...>>' functionality in mlir-tblgen (#205375)
Previously, mlir-tblgen would generate incorrect C++ code when
passing a custom constraint to `Successor<...>`. The code would fail
to compile. We lacked end-to-end tests for this functionality and all
in-tree dialects only use `AnySuccessor` for their successors.
Custom C++ predicates for an Operation's successor(s) can be useful
in order to generate verification for certain conditions (e.g. that the
successor is the "next" block). This commit fixes the mlir-tblgen
functionality and adds end-to-end tests in the Test dialect for single
and variadic successors.
Assisted-by: Claude
Commit: 1254310544a8ef042b635bc15b4d70e891fae62b
https://github.com/llvm/llvm-project/commit/1254310544a8ef042b635bc15b4d70e891fae62b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/add_i128.ll
M llvm/test/CodeGen/AMDGPU/add_i64.ll
M llvm/test/CodeGen/AMDGPU/alignbit-pat.ll
M llvm/test/CodeGen/AMDGPU/allow-check.ll
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
M llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir
M llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
M llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir
M llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir
M llvm/test/CodeGen/AMDGPU/commute-compares.ll
M llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll
M llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cttz-elts.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll
M llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/extract-load-i1.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll
M llvm/test/CodeGen/AMDGPU/fceil64.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
M llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/freeze-other-uses-issue-198094.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/global-alias.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir
M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
Log Message:
-----------
AMDGPU: Avoid using default subtarget in generated codegen tests (1/9) (#205784)
Fix codegen tests using amdgcn triples without a target-cpu. The dummy
default subtarget has always been an irritating edge case to deal with.
For unknown/mesa3d/amdpal triples, this has been a gfx600-like result
and gfx700-like result for amdhsa. Convert tests to use the explicit
target. This was performed by vibe-coded script, and covers tests
using update_{llc|mir}_test_checks. There are some minor codegen
differences to be expected, mostly due to now having a scheduling
model.
In the future we should forbid trying to codegen the default target.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 334907c294934e7f83867d96035ee3af4f0d63b6
https://github.com/llvm/llvm-project/commit/334907c294934e7f83867d96035ee3af4f0d63b6
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
A llvm/test/Transforms/IndVarSimplify/exit-value-gep-inbounds.ll
Log Message:
-----------
[IndVars] Add tests with exit uses of inbounds GEPs. (NFC) (#205665)
Commit: 1813ca6e98ac0159aea9ef9aa40cc441d185ec8e
https://github.com/llvm/llvm-project/commit/1813ca6e98ac0159aea9ef9aa40cc441d185ec8e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/icmp.i16.ll
M llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
M llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir
M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
M llvm/test/CodeGen/AMDGPU/mcp-use-before-def.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir
M llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir
M llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
M llvm/test/CodeGen/AMDGPU/perfhint.ll
M llvm/test/CodeGen/AMDGPU/rcp_iflag.ll
M llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
M llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
M llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
M llvm/test/CodeGen/AMDGPU/rotate-add.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/setcc-select-hi32mask.ll
M llvm/test/CodeGen/AMDGPU/setcc-select.ll
M llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-nested-control-flows.ll
M llvm/test/CodeGen/AMDGPU/si-i1-copies.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-body.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-latch.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-multi-entry-cycle.mir
M llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
M llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
M llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
M llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
M llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir
M llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir
M llvm/test/CodeGen/AMDGPU/trunc-bitcast-vector.ll
M llvm/test/CodeGen/AMDGPU/trunc-cmp-constant.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
M llvm/test/CodeGen/AMDGPU/udivrem24.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
Log Message:
-----------
AMDGPU: Avoid default subtarget in generated codegen tests (2/9) (#205785)
Continue migrating away from testing the dummy target, and use
real targets approximating the old behavior. Performed by script.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: a916cb6b5793ee5e853dd308fed9c14940821023
https://github.com/llvm/llvm-project/commit/a916cb6b5793ee5e853dd308fed9c14940821023
Author: Ian Anderson <iana at apple.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M clang/include/clang/Basic/DarwinSDKInfo.h
M clang/lib/Basic/DarwinSDKInfo.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Darwin.h
M clang/test/Driver/driverkit-path.c
M clang/test/Driver/incompatible_sysroot.c
M clang/unittests/Basic/DarwinSDKInfoTest.cpp
Log Message:
-----------
[clang][driver][darwin] DarwinSDKInfo doesn't match sufficiently modified triples, doesn't warn for unsupported architectures (#204061)
DarwinSDKInfo::getPlatformPrefix(...) is passed the effective target
triple which has undergone modifications from the original -target
value, which can sometimes even include changes to the triple's
environment. That will cause it to fail to match the platform infos, not
get a platform prefix, and get incorrect default search paths. In the
case where a triple doesn't match, check all platform infos, and if they
all have the same platform prefix, then use that.
DarwinSDKInfo::supportsTriple(...) doesn't try to match the architecture
of the triple. That makes it not emit -Wincompatible-sysroot e.g. when
trying to use arm64 against a sufficiently old macOS SDK or when still
trying to build i386 for macOS. Instead of parsing values from
SDKSettings.json into a Triple, storing the probably-relevant
components, and then comparing those against a full Triple, just store
the parsed triple and get rid of the custom comparison code. While this
does make the matching problem above a little more fragile, in practice
that's well mitigated by treating thumb* and arm* as equivalent, and it
does allow for better diagnostics and overall simpler code.
Clean up some unnecessary copies in DarwinSDKInfo and related code.
Assisted-by: Claude Code
rdar://172876443
Commit: 336aa499241da677ba5dadf055ae3b4b5affba03
https://github.com/llvm/llvm-project/commit/336aa499241da677ba5dadf055ae3b4b5affba03
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
A offload/test/offloading/xteam_min_reduction_partial_wave.c
M openmp/device/src/Reduction.cpp
Log Message:
-----------
[offload][OpenMP] Fix partial warp reduction (#205861)
Don't use a full warp for the final cross-team reduction if the
reduction's thread limit is below the warp size.
Claude assisted with the test.
Commit: c6c76421d3c24a7009cffd7fcdb9022c81d9c898
https://github.com/llvm/llvm-project/commit/c6c76421d3c24a7009cffd7fcdb9022c81d9c898
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M libcxx/lib/abi/CHANGELOG.TXT
Log Message:
-----------
[libc++] Add missing ABI changelog entry for #173283 (#205887)
PR #173283 (Remove numpunct_byname::__init) removed symbols but forgot
to add the relevant entry in the ABI changelog.
Commit: b8c5f6ee633cd4176acdb5153c537e5dafa61063
https://github.com/llvm/llvm-project/commit/b8c5f6ee633cd4176acdb5153c537e5dafa61063
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant64_to_sgpr.mir
M llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-debug-non-first-terminators.mir
M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
M llvm/test/CodeGen/AMDGPU/wqm-debug-instr.mir
Log Message:
-----------
AMDGPU: Avoid default subtarget in generated codegen tests (3/9) (#205786)
Another batch of tests updated by script.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: aa939e521d71407d5d653eb8fd6b5ce283e3e32c
https://github.com/llvm/llvm-project/commit/aa939e521d71407d5d653eb8fd6b5ce283e3e32c
Author: Akhil Goel <akhil.goel at intel.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
A llvm/test/CodeGen/SPIRV/pointers/global-vars-untyped.ll
Log Message:
-----------
[SPIR-V] Avoid typed pointers for global variables (#201203)
This PR replaces typed pointers with opaque pointers for global variable
types. Since typed pointers are legal in SPIR-V, the type retrieved when
creating a global variable may be a typed pointer, causing it to leak
into the module. This will break the bitcode parsing of the serialized
module.
Commit: aca3f14c0d24d6d3ddc376ebbe1b5b0636e12ed6
https://github.com/llvm/llvm-project/commit/aca3f14c0d24d6d3ddc376ebbe1b5b0636e12ed6
Author: Schrodinger ZHU Yifan <yfzhu at google.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M libc/benchmarks/CMakeLists.txt
M libc/benchmarks/JSON.cpp
M libc/benchmarks/JSONTest.cpp
M libc/benchmarks/LibcBenchmark.cpp
M libc/benchmarks/LibcBenchmark.h
M libc/benchmarks/LibcBenchmarkTest.cpp
M libc/benchmarks/LibcFunctionPrototypes.h
M libc/benchmarks/LibcMemoryBenchmark.cpp
M libc/benchmarks/LibcMemoryBenchmark.h
M libc/benchmarks/LibcMemoryBenchmarkMain.cpp
M libc/benchmarks/LibcMemoryGoogleBenchmarkMain.cpp
M libc/benchmarks/MemorySizeDistributions.cpp
M libc/benchmarks/MemorySizeDistributions.h
Log Message:
-----------
[libc][benchmark] allow benchmark to be built without llvm support (#200951)
Update benchmark to allow it to be built in runtimes driven mode.
It is still useful to have an in-tree benchmark suite. On my side, I am
working on some allocators related benchmarks. Due to the broken state
of this in-tree benchmark suite, I have to frequently port changes
between two workspace. Also, having benchmark suite can make it easier
to track performance change in a consistent view.
Assisted-by: AI tools, checked manually
Commit: 3021455fcc4d173a92ffad2ac39a11a5dcf8271a
https://github.com/llvm/llvm-project/commit/3021455fcc4d173a92ffad2ac39a11a5dcf8271a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shifts.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpyinline.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memset.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memsetinline.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/v_bfe_i32.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void-inseltpoison.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void.ll
Log Message:
-----------
AMDGPU: Avoid default subtarget in codegen tests (4/9) (#205787)
Continue migrating targets away from codegenning the dummy target
by script.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 5375e9c91c26431923d74793460b20ba7c1b08fa
https://github.com/llvm/llvm-project/commit/5375e9c91c26431923d74793460b20ba7c1b08fa
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Remove unused MinProfitableTripCount field from ILV (NFC) (#205666)
The MinProfitableTripCount is never read. Remove it.
Commit: fbc32eb9fcf6e16173daabdd3bdbff169dda5917
https://github.com/llvm/llvm-project/commit/fbc32eb9fcf6e16173daabdd3bdbff169dda5917
Author: Zorojuro <sawantsukumar at gmail.com>
Date: 2026-06-26 (Fri, 26 Jun 2026)
Changed paths:
M libc/src/math/docs/add_math_function.md
Log Message:
-----------
[libc][docs] updating entrypoints in `add_math_functions.md` (#204700)
It updates the entrypoint documentation, which currently has only two
entrypoints listed (Outdated)
Commit: 8af6c2936d4eb824f853dfaba24722527277a520
https://github.com/llvm/llvm-project/commit/8af6c2936d4eb824f853dfaba24722527277a520
Author: Moazin K. <mkhatti at nvidia.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCTypeInterfaces.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtils.h
M mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtils.cpp
A mlir/test/Dialect/OpenACC/acc-recipe-materialization-firstprivate-two-allocs.mlir
Log Message:
-----------
[OpenACC] Propagate variable names to ops after materializing recipes. (#205821)
ACCRecipeMaterialization only attaches names to the result of the recipe
being materialized. However, some recipes produce multiple ops that need
to carry the variable name.
This change introduces `acc::getVarNamePlaceholder()`, a placeholder
value for `acc.var_name`. Implementations can attach this placeholder
while building the recipe to any ops that should carry the variable
name. ACCRecipeMaterialization will then replace the placeholder with
the actual variable name while materializing the recipe.
Assisted-by: Claude Code
Commit: 3b5c4ae855e6c2ee173c0cab37b8c6b38f344b8f
https://github.com/llvm/llvm-project/commit/3b5c4ae855e6c2ee173c0cab37b8c6b38f344b8f
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
M llvm/test/CodeGen/DirectX/scalarize-dynamic-vector-index.ll
Log Message:
-----------
[DirectX] Widen i1 indexable temps to i32 in DXILDataScalarization (#205444)
fixes #205443
Dynamically-indexed <N x i1> vectors were lowered to alloca [N x i1]
indexable temps. DXIL booleans are 32-bit in memory, and i1 stack arrays
are mishandled downstream (e.g. WARP returns 1 for every
dynamically-indexed element), producing wrong results for dynamic
bool vector/matrix accesses.
Widen i1 indexable-temp arrays to [N x i32], zero-extending on store and
truncating back to i1 on load, matching DXC. Fixes the dynamic bool
extract/insert miscompile.
We make this change in DXILDataScalarization because this is the pass
that adds the i1 allocas which was the cause of our miscompile.
Assisted by Claude Opus 4.7
Commit: 23e960431d294646b0664f759463529588471fc4
https://github.com/llvm/llvm-project/commit/23e960431d294646b0664f759463529588471fc4
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M libcxx/include/__memory/shared_ptr.h
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/make_shared.pass.cpp
Log Message:
-----------
[libc++] Fix move-only types in std::make_shared (#205819)
https://github.com/llvm/llvm-project/pull/200401 broke `make_shared` and
friends support for move-only types.
Commit: 0b328bc6a50becb35ebfb158dd3de69bd32c5563
https://github.com/llvm/llvm-project/commit/0b328bc6a50becb35ebfb158dd3de69bd32c5563
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M flang-rt/lib/runtime/__cuda_device.f90
M flang-rt/lib/runtime/cuda_runtime_api.f90
Log Message:
-----------
[Flang-RT] Make __cuda_builtins dependency explicit (#205895)
When compiling CUDA-Fortran, a use of the module __cuda_builtins is
added implicitly by the compiler. Add explicit use so CMake can consider
it in the built order. The other modules that are compiled with CUDA
enabled (`cudadevice.f90` and `cooperativegroups.f90`) transitively
depend on depend on __cuda_builtins as well.
Commit: f0fd1ee64993eca0acb9d847ebf351ed7eb10bac
https://github.com/llvm/llvm-project/commit/f0fd1ee64993eca0acb9d847ebf351ed7eb10bac
Author: Alex Langford <alangford at apple.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M lldb/include/lldb/Utility/FileSpec.h
Log Message:
-----------
[lldb][NFC] Correct documentation for FileSpec::GetFileNameExtension (#205871)
Commit: 0a00381c67afcbb411679407c96e6b3e6613ee2f
https://github.com/llvm/llvm-project/commit/0a00381c67afcbb411679407c96e6b3e6613ee2f
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
A llvm/test/Analysis/MemorySSA/invariant-load-intrinsic.ll
A llvm/test/Transforms/GVN/invariant-load-intrinsic.ll
A llvm/test/Transforms/InstCombine/invariant-load-like-sink.ll
M llvm/test/Transforms/Sink/invariant-load.ll
Log Message:
-----------
[llvm][NFC] Add invariant.load intrinsic precommit tests (#205894)
Add tests to show what does/doesn't currently happen to !invariant.load
on intrinsics that read memory.
AI disclosure: Codex wrote these. They got put into new files in many cases and I _think_ that's a reasonable call.
Co-authored-by: Codex <codex at openai.com>
Commit: f2459f9ec89db238fb84b13a75ae38867d0b6cb2
https://github.com/llvm/llvm-project/commit/f2459f9ec89db238fb84b13a75ae38867d0b6cb2
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-memory-op-decisions.ll
Log Message:
-----------
[VPlan] Handle loads feeding memops in makeMemOpWideningDecisions (NFC) (#196842)
The legacy cost model force-scalarizes loads feeding memory ops, unless
the target prefers vector addressing. Add the logic to
makeMemOpWideningDecisions. Currently this should match the legacy
decision as-is. Should be test-able in VPlan-printing test if legacy
decisions are done in a separate sub-pass as
https://github.com/llvm/llvm-project/pull/182593
PR: https://github.com/llvm/llvm-project/pull/196842
Commit: fc171ea41ab66eb05c27e939dd12e12de5da7423
https://github.com/llvm/llvm-project/commit/fc171ea41ab66eb05c27e939dd12e12de5da7423
Author: Justin Bogner <mail at justinbogner.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/docs/GettingInvolved.md
Log Message:
-----------
[GettingInvolved] Add wg-hlsl to online sync ups (#205891)
This has been on the community calendar for a very long time, but
apparently we never added it here.
Commit: 749abf04eadaa38549e0168f1f6def513c86bee1
https://github.com/llvm/llvm-project/commit/749abf04eadaa38549e0168f1f6def513c86bee1
Author: Gedare Bloom <gedare at rtems.org>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M clang/lib/Format/FormatToken.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] annotate inline assembly parens (#201703)
Annotate the opening and closing parens of inline assembly. This will
make other improvements related to inline assembly easier.
Commit: de3787e56829165917efef19c4ef030f230dc9e8
https://github.com/llvm/llvm-project/commit/de3787e56829165917efef19c4ef030f230dc9e8
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-es.ll
M llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp-on.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-psenable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-ps.ll
M llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
M llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll
M llvm/test/CodeGen/AMDGPU/atomic_load_add.ll
M llvm/test/CodeGen/AMDGPU/atomic_load_sub.ll
M llvm/test/CodeGen/AMDGPU/barrier-elimination.ll
M llvm/test/CodeGen/AMDGPU/basic-branch.ll
M llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll
M llvm/test/CodeGen/AMDGPU/branch-uniformity.ll
M llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
M llvm/test/CodeGen/AMDGPU/call-constant.ll
M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
M llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll
M llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
M llvm/test/CodeGen/AMDGPU/coalescer_remat.ll
M llvm/test/CodeGen/AMDGPU/commute_modifiers.ll
M llvm/test/CodeGen/AMDGPU/concat_vectors.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir
M llvm/test/CodeGen/AMDGPU/debug-value.ll
M llvm/test/CodeGen/AMDGPU/debug-value2.ll
M llvm/test/CodeGen/AMDGPU/debug_frame.ll
M llvm/test/CodeGen/AMDGPU/default_amdhsa_code_object_version.ll
M llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir
M llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-xnor.ll
M llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll
M llvm/test/CodeGen/AMDGPU/eh_frame.ll
M llvm/test/CodeGen/AMDGPU/elf.ll
M llvm/test/CodeGen/AMDGPU/enable-no-signed-zeros-fp-math.ll
M llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll
M llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
M llvm/test/CodeGen/AMDGPU/exceed-max-sgprs.ll
M llvm/test/CodeGen/AMDGPU/extload-align.ll
M llvm/test/CodeGen/AMDGPU/extload-private.ll
M llvm/test/CodeGen/AMDGPU/extload.ll
M llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll
M llvm/test/CodeGen/AMDGPU/fadd.ll
M llvm/test/CodeGen/AMDGPU/fceil.ll
M llvm/test/CodeGen/AMDGPU/ffloor.f64.ll
M llvm/test/CodeGen/AMDGPU/ffloor.ll
M llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/fma.f64.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.f64.ll
M llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
M llvm/test/CodeGen/AMDGPU/fmul.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/fneg.f64.ll
M llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
M llvm/test/CodeGen/AMDGPU/fold-fmul-to-neg-abs.ll
M llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
M llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir
M llvm/test/CodeGen/AMDGPU/fold-over-exec.mir
M llvm/test/CodeGen/AMDGPU/fold-readlane.mir
M llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll
Log Message:
-----------
AMDGPU: Avoid default subtarget in hand-written codegen tests (5/9) (#205788)
Introduce -mcpu arguments in tests that did not need check line updates.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 7f0fad687d76fecc087fe6aca70d7086655d2e41
https://github.com/llvm/llvm-project/commit/7f0fad687d76fecc087fe6aca70d7086655d2e41
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.ptr.buffer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.f64.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.f64.ll
M llvm/test/CodeGen/AMDGPU/fpext.ll
M llvm/test/CodeGen/AMDGPU/fract.f64.ll
M llvm/test/CodeGen/AMDGPU/fract.ll
M llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir
M llvm/test/CodeGen/AMDGPU/fsub.ll
M llvm/test/CodeGen/AMDGPU/ftrunc.ll
M llvm/test/CodeGen/AMDGPU/global-constant.ll
M llvm/test/CodeGen/AMDGPU/global-directive.ll
M llvm/test/CodeGen/AMDGPU/global-extload-i16.ll
M llvm/test/CodeGen/AMDGPU/gv-const-addrspace.ll
M llvm/test/CodeGen/AMDGPU/hoist-cond.ll
M llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-deduced-arg-attr.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll
M llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir
M llvm/test/CodeGen/AMDGPU/huge-private-buffer.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll
M llvm/test/CodeGen/AMDGPU/icmp64.ll
M llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
M llvm/test/CodeGen/AMDGPU/indirect-private-64.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir
M llvm/test/CodeGen/AMDGPU/invalid-inline-asm-constraint-crash.ll
M llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll
M llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
M llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
M llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
M llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll
M llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll
M llvm/test/CodeGen/AMDGPU/lds-alignment.ll
M llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll
M llvm/test/CodeGen/AMDGPU/lds-size.ll
M llvm/test/CodeGen/AMDGPU/liveness.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.clamp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.msad.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.decperflevel.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.incperflevel.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.hi.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.ll
M llvm/test/CodeGen/AMDGPU/load-global-f64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i1.ll
M llvm/test/CodeGen/AMDGPU/load-global-i64.ll
M llvm/test/CodeGen/AMDGPU/load-local-f32.ll
M llvm/test/CodeGen/AMDGPU/load-local-f64.ll
M llvm/test/CodeGen/AMDGPU/load-local-i1.ll
M llvm/test/CodeGen/AMDGPU/load-local-i32.ll
M llvm/test/CodeGen/AMDGPU/load-local-i64.ll
M llvm/test/CodeGen/AMDGPU/load-local-i8.ll
M llvm/test/CodeGen/AMDGPU/load-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/local-64.ll
M llvm/test/CodeGen/AMDGPU/local-atomics.ll
M llvm/test/CodeGen/AMDGPU/local-atomics64.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir
M llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll
Log Message:
-----------
AMDGPU: Avoid default subtarget in hand-written codegen tests (6/9) (#205789)
Introduce -mcpu arguments in tests which didn't require check line
updates.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: 0f1abfe0afe13b0fc101721aeef64d2169a32e7e
https://github.com/llvm/llvm-project/commit/0f1abfe0afe13b0fc101721aeef64d2169a32e7e
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/clause-validity02.f90
M flang/test/Semantics/OpenMP/declarative-directive01.f90
M flang/test/Semantics/OpenMP/device-constructs.f90
M flang/test/Semantics/OpenMP/sections01.f90
M flang/test/Semantics/OpenMP/single04.f90
M flang/test/Semantics/OpenMP/workshare02.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.h
Log Message:
-----------
[flang][OpenMP] Move clause validity checks into OpenMP-specific code (#205607)
The checks for syntactic properties of clauses (e.g. uniqueness, being
required, etc.) were originally handled by infrastructure common to
OpenMP and OpenACC. That infrastructure, however, is not fully equipped
to handle OpenMP needs: being unable to express version-based properties
or clause set properties being two prominent examples.
The first step towards fulfilling the OpenMP requirements it is to
transfer the handling of clause validity checks into OpenMP-specific
code, which can then be modified without interfering with OpenACC.
In addition to that, this PR also changes the way that clauses on end-
directives are handled: first, a clause appearing on an end-directive is
checked to be allowed to appear on an end-directive, then all clauses
from the begin- and the end-directives are tested together. This unifies
checks for uniqueness of clauses that can appear in both places.
Commit: c002097b9bc07f858edb16947c6500077d2b2b17
https://github.com/llvm/llvm-project/commit/c002097b9bc07f858edb16947c6500077d2b2b17
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
Log Message:
-----------
[VPlan] Remove unused VPlanPrinter::getOrCreateName(const VPBlockBase*) (#205896)
The block-name printers use getName()/getUID() directly; this overload
has no callers.
Commit: 988a1a212035a0ee1688a0d1b1d2fbc331151ce5
https://github.com/llvm/llvm-project/commit/988a1a212035a0ee1688a0d1b1d2fbc331151ce5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir
M llvm/test/CodeGen/AMDGPU/madmk.ll
M llvm/test/CodeGen/AMDGPU/max-sgprs.ll
M llvm/test/CodeGen/AMDGPU/max3.ll
M llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
M llvm/test/CodeGen/AMDGPU/mem-builtins.ll
M llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-m0.mir
M llvm/test/CodeGen/AMDGPU/min3.ll
M llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
M llvm/test/CodeGen/AMDGPU/movrels-bug.mir
M llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
M llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir
M llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
M llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll
M llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll
M llvm/test/CodeGen/AMDGPU/nullptr.ll
M llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
M llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll
M llvm/test/CodeGen/AMDGPU/operand-spacing.ll
M llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir
M llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
M llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll
M llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll
M llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir
M llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir
M llvm/test/CodeGen/AMDGPU/register-count-comments.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/reorder-stores.ll
M llvm/test/CodeGen/AMDGPU/rotl.i64.ll
M llvm/test/CodeGen/AMDGPU/rotr.i64.ll
M llvm/test/CodeGen/AMDGPU/s_movk_i32.ll
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll
M llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir
M llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/sdivrem24.ll
M llvm/test/CodeGen/AMDGPU/select-opt.ll
M llvm/test/CodeGen/AMDGPU/selectcc-opt.ll
M llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
M llvm/test/CodeGen/AMDGPU/setcc-opt.ll
M llvm/test/CodeGen/AMDGPU/setcc-sext.ll
M llvm/test/CodeGen/AMDGPU/setcc64.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
M llvm/test/CodeGen/AMDGPU/sgprcopies.ll
M llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll
M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
M llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.ll
M llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll
M llvm/test/CodeGen/AMDGPU/smed3.ll
M llvm/test/CodeGen/AMDGPU/spill-before-exec.mir
M llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll
M llvm/test/CodeGen/AMDGPU/stack-size-overflow.ll
M llvm/test/CodeGen/AMDGPU/store-barrier.ll
M llvm/test/CodeGen/AMDGPU/store-v3i64.ll
M llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
M llvm/test/CodeGen/AMDGPU/subreg_interference.mir
M llvm/test/CodeGen/AMDGPU/target-cpu.ll
M llvm/test/CodeGen/AMDGPU/trap.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-i1.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
M llvm/test/CodeGen/AMDGPU/uint_to_fp.ll
M llvm/test/CodeGen/AMDGPU/umed3.ll
M llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
M llvm/test/CodeGen/AMDGPU/undef-build-vector.ll
M llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll
M llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
M llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll
M llvm/test/CodeGen/AMDGPU/v_mac.ll
M llvm/test/CodeGen/AMDGPU/verify-sop.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
Log Message:
-----------
AMDGPU: Avoid default subtarget in hand-written codegen tests (7/9) (#205790)
Introduce an -mcpu argument to tests missing it to avoid codegening
the default dummy target. These are cases that didn't require adjusting
the check lines.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: f9aa739d5ad1798f68ceedd97af77e9f1209001f
https://github.com/llvm/llvm-project/commit/f9aa739d5ad1798f68ceedd97af77e9f1209001f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/vop-shrink.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir
M llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
M llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll
M llvm/test/CodeGen/AMDGPU/zext-lid.ll
Log Message:
-----------
AMDGPU: Avoid default subtarget in hand-written codegen tests (8/9) (#205791)
Introduce the missing -mcpu argument to some tests which are not
autogenerated.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
Commit: c9f4ba01521f2a1b5610235a1766fa03b25309eb
https://github.com/llvm/llvm-project/commit/c9f4ba01521f2a1b5610235a1766fa03b25309eb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/gep-address-space.ll
M llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/schedule-physregdeps.mir
M llvm/test/CodeGen/AMDGPU/setcc.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
M llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll
Log Message:
-----------
AMDGPU: Avoid default subtarget in hand-written codegen tests (9/9) (#205792)
Fix some manual test checks using amdgcn triples without -mcpu. These
require the most careful consideration. The highest impact changes are the
optimizations removing execz branch now that there's a sched model.
Commit: 9b84d3b85642edf373163f395ec65ba3fcac1fc1
https://github.com/llvm/llvm-project/commit/9b84d3b85642edf373163f395ec65ba3fcac1fc1
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M libcxx/include/__ranges/take_while_view.h
A libcxx/test/libcxx/ranges/range.adaptors/range.take_while/nodiscard.verify.cpp
Log Message:
-----------
[libc++][ranges] Applied `[[nodiscard]]` to `take_while_view` (#205172)
Towards #172124
# References:
- https://wg21.link/range.take_while
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Commit: ad850b8176cdb122ca1b8f0e1dce718e4f60f66d
https://github.com/llvm/llvm-project/commit/ad850b8176cdb122ca1b8f0e1dce718e4f60f66d
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M libcxx/include/__ranges/split_view.h
A libcxx/test/libcxx/ranges/range.adaptors/range.split/nodiscard.verify.cpp
Log Message:
-----------
[libc++][ranges] Applied `[[nodiscard]]` to `split_view` (#205161)
Towards #172124
# References:
- https://wg21.link/range.split
-
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
---------
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Commit: 29bf2c4068a4c7a2c4f15e9982d4ae7cef7e50ec
https://github.com/llvm/llvm-project/commit/29bf2c4068a4c7a2c4f15e9982d4ae7cef7e50ec
Author: mygitljf <101249452+mygitljf at users.noreply.github.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M mlir/test/IR/visitors.mlir
M mlir/test/lib/IR/TestVisitors.cpp
Log Message:
-----------
[mlir] Fix visitor block erasure (#205854)
I made the visitor test drop block-defined value uses before erasing the
block and added a small regression case.
Fixes #205717
Commit: 1f46c12683f0683c13d86016d1ecba6392c08060
https://github.com/llvm/llvm-project/commit/1f46c12683f0683c13d86016d1ecba6392c08060
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/gpu-exceptions.cpp
Log Message:
-----------
[Clang] Disable C++ exceptions by default for GPU targets (#205402)
Summary:
Exceptions are not supporter, and likely will never be supported, on
GPUs. The SIMT model makes context switching nearly impossible, and
building an unwinder would require stashing a register file that is
over 8 KiB these days. There's precedent to disable this for the target,
so we should just do this.
Offloading languages have their own weird handling, some chimera that
just accepts exceptions but turns them into traps on the device side, so
we leave that unaffected.
Commit: 1774a65964a0b1b8220bf440991cfc3af2896b06
https://github.com/llvm/llvm-project/commit/1774a65964a0b1b8220bf440991cfc3af2896b06
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/test/CodeGenCUDA/offload_via_llvm.cu
M offload/include/Shared/APITypes.h
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/common/src/RecordReplay.cpp
M offload/plugins-nextgen/cuda/dynamic_cuda/cuda.cpp
M offload/plugins-nextgen/cuda/dynamic_cuda/cuda.h
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/host/src/rtl.cpp
M offload/plugins-nextgen/level_zero/include/L0Kernel.h
M offload/plugins-nextgen/level_zero/src/L0Kernel.cpp
Log Message:
-----------
[Offload] Unify the kernel argument passing (#205224)
Summary:
Currently we have two conflicting methods of passing kernel arguments, a
flat pointer + size and an array of pointers. We recently decided to
move the offload API to the latter because it is more generic and lets
you construct the other formats.
This PR primarily just changes the format and the one existing core use.
The uses should be simplier now. Future changes will change the OpenMP
argument parsing.
Commit: a18c09a05d6d6a950b1b7cd9c59a43fcee5cb442
https://github.com/llvm/llvm-project/commit/a18c09a05d6d6a950b1b7cd9c59a43fcee5cb442
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M clang/lib/UnifiedSymbolResolution/USRGeneration.cpp
M clang/test/Analysis/Scalable/PointerFlow/entity-name-no-conflict.cpp
M clang/unittests/Index/IndexTests.cpp
Log Message:
-----------
[clang][index][USR] GenLoc prints file entry at most once, allow repeated offsets (#205430)
`GenLoc` previously printed the source location at most once per USR,
gated by a member flag toggled on the first call. During the recursive
visit, if both an outer and an inner decl needed to print the location,
only the outer one was printed. When the outer decl did not need the
offset, no offset was ever printed. For example, the USR of
`Holder<decltype([]{})>::method` depends on the location of the type of
the lambda but the outer decl prints the file entry only, which disables
offset printing.
Change the logic so the file-entry part of the location is printed at
most once (it must be identical), while offsets of sub-decl locations
may be printed multiple times.
rdar://180654884
---------
Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
Commit: d9906882fc613471ab51e7185094efae893066de
https://github.com/llvm/llvm-project/commit/d9906882fc613471ab51e7185094efae893066de
Author: adams381 <adams at nvidia.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.h
A clang/test/CIR/Transforms/abi-lowering/expand-struct-arg.cir
Log Message:
-----------
[CIR] Implement ArgKind::Expand in CallConvLowering (#201718)
ArgKind::Expand classifies a struct argument for flattening: each field
becomes a separate scalar argument at the ABI level. Classic CodeGen
calls this "struct expansion" — used on targets like MIPS and some ARM
calling conventions.
CIRABIRewriteContext previously emitted errorNYI at both classification
sites. The replacement covers three call paths. In buildNewArgTypes,
the original struct type is replaced by one wire type per field. In
insertArgCoercion, the single struct block argument is replaced by N
scalar block arguments and an alloca+get_member+store+load sequence at
the entry block reassembles them for body uses; a running block-argument
index (rather than classIdx + sretOffset) correctly tracks the expanded
slot count when multiple Expand args or sret+Expand combinations appear.
The Ignore-drop loop gains a classToBlockArg pre-computation so that
Ignore args following Expand args are erased at the correct index. In
rewriteCallSite, cir.extract_member decomposes the struct operand into
its constituent fields, which become separate call arguments.
Asserts guard the two structural invariants: Expand requires a struct
type (not a union) and at least one field.
Commit: 512677061a0cd521f800eefa53dbf086bf37c3e6
https://github.com/llvm/llvm-project/commit/512677061a0cd521f800eefa53dbf086bf37c3e6
Author: David Rivera <davidriverg at gmail.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/test/CIR/CodeGenCUDA/address-spaces.cu
Log Message:
-----------
[CIR][CUDA] Replace poison attr usages to undef for global shared/shadow/device-shadow instantiation (#204663)
Commit: 9b29fb8c82117f5dfae60591b568ef589b3c82d2
https://github.com/llvm/llvm-project/commit/9b29fb8c82117f5dfae60591b568ef589b3c82d2
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M flang/test/Semantics/cuf05.cuf
Log Message:
-----------
[flang] Fix testcase after 0b328bc6a50becb35ebfb158dd3de69bd32c5563 (#205914)
Commit: ddc1588aaf55c822faaca3a6ae090fd17b70f700
https://github.com/llvm/llvm-project/commit/ddc1588aaf55c822faaca3a6ae090fd17b70f700
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-25 (Thu, 25 Jun 2026)
Changed paths:
M clang-tools-extra/clang-tidy/misc/ExplicitConstructorCheck.cpp
M clang-tools-extra/clang-tidy/utils/TypeTraits.cpp
M clang-tools-extra/clang-tidy/utils/TypeTraits.h
M clang-tools-extra/pp-trace/PPCallbacksTracker.cpp
M clang-tools-extra/unittests/clang-tidy/CMakeLists.txt
A clang-tools-extra/unittests/clang-tidy/TypeTraitsTest.cpp
M clang/include/clang/Basic/DarwinSDKInfo.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/Basic/DarwinSDKInfo.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/Dialect/Transforms/EHABILowering.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.h
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Darwin.h
M clang/lib/Driver/ToolChains/ZOS.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/UnifiedSymbolResolution/USRGeneration.cpp
M clang/test/Analysis/Scalable/PointerFlow/entity-name-no-conflict.cpp
A clang/test/CIR/CodeGen/builtin-atomic-is-lock-free.c
A clang/test/CIR/CodeGen/cleanup-scope-throw-caught.cpp
M clang/test/CIR/CodeGen/constant-inits.cpp
A clang/test/CIR/CodeGen/new-array-init.cpp
M clang/test/CIR/CodeGen/new.cpp
M clang/test/CIR/CodeGen/paren-list-agg-init.cpp
M clang/test/CIR/CodeGen/record-zero-init-padding.c
M clang/test/CIR/CodeGenCUDA/address-spaces.cu
M clang/test/CIR/CodeGenCXX/new-array-init.cpp
A clang/test/CIR/Transforms/abi-lowering/expand-struct-arg.cir
M clang/test/CodeGenCUDA/offload_via_llvm.cu
M clang/test/Driver/driverkit-path.c
A clang/test/Driver/gpu-exceptions.cpp
M clang/test/Driver/incompatible_sysroot.c
M clang/test/Driver/zos-ld.c
M clang/test/SemaCXX/constant-expression-p2280r4.cpp
M clang/unittests/Basic/DarwinSDKInfoTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/Index/IndexTests.cpp
M flang-rt/lib/runtime/__cuda_device.f90
M flang-rt/lib/runtime/cuda_runtime_api.f90
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/openmp-utils.cpp
M flang/lib/Semantics/program-tree.cpp
M flang/test/Lower/OpenMP/metadirective-construct.f90
A flang/test/Semantics/OpenACC/acc-routine-bad.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/clause-validity02.f90
M flang/test/Semantics/OpenMP/declarative-directive01.f90
M flang/test/Semantics/OpenMP/device-constructs.f90
M flang/test/Semantics/OpenMP/sections01.f90
M flang/test/Semantics/OpenMP/single04.f90
M flang/test/Semantics/OpenMP/workshare02.f90
M flang/test/Semantics/cuf05.cuf
M libc/benchmarks/CMakeLists.txt
M libc/benchmarks/JSON.cpp
M libc/benchmarks/JSONTest.cpp
M libc/benchmarks/LibcBenchmark.cpp
M libc/benchmarks/LibcBenchmark.h
M libc/benchmarks/LibcBenchmarkTest.cpp
M libc/benchmarks/LibcFunctionPrototypes.h
M libc/benchmarks/LibcMemoryBenchmark.cpp
M libc/benchmarks/LibcMemoryBenchmark.h
M libc/benchmarks/LibcMemoryBenchmarkMain.cpp
M libc/benchmarks/LibcMemoryGoogleBenchmarkMain.cpp
M libc/benchmarks/MemorySizeDistributions.cpp
M libc/benchmarks/MemorySizeDistributions.h
A libc/docs/dev/builtin_compatibility.rst
M libc/docs/dev/index.rst
M libc/src/math/docs/add_math_function.md
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__ranges/split_view.h
M libcxx/include/__ranges/take_while_view.h
M libcxx/lib/abi/CHANGELOG.TXT
A libcxx/test/libcxx/ranges/range.adaptors/range.split/nodiscard.verify.cpp
A libcxx/test/libcxx/ranges/range.adaptors/range.take_while/nodiscard.verify.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.create/make_shared.pass.cpp
M lldb/include/lldb/Breakpoint/Breakpoint.h
M lldb/include/lldb/Breakpoint/BreakpointList.h
M lldb/include/lldb/Utility/FileSpec.h
M lldb/source/Breakpoint/BreakpointList.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Target/Target.cpp
A lldb/test/Shell/SymbolFile/DWARF/wasm-function-display-name.yaml
M llvm/benchmarks/CMakeLists.txt
A llvm/benchmarks/ImmutableSetIteratorBM.cpp
M llvm/docs/GettingInvolved.md
M llvm/include/llvm/ADT/ImmutableSet.h
M llvm/include/llvm/ADT/StringRef.h
M llvm/include/llvm/Frontend/OpenMP/OMP.h
M llvm/include/llvm/Target/TargetLoweringObjectFile.h
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
M llvm/lib/Target/BPF/BPFCORE.h
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/BPF/BTFDebug.h
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
M llvm/lib/Target/NVPTX/CMakeLists.txt
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.h
M llvm/lib/Target/NVPTX/NVPTX.h
R llvm/lib/Target/NVPTX/NVPTXAddressFolder.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrFormats.td
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/TargetLoweringObjectFile.cpp
M llvm/lib/Target/TargetMachine.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
A llvm/test/Analysis/MemorySSA/invariant-load-intrinsic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shifts.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-prefetch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-ptrmask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-struct-return-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpyinline.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memset.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memsetinline.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.ptr.buffer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/selected-inst-flags.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/v_bfe_i32.ll
M llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll
M llvm/test/CodeGen/AMDGPU/add_i128.ll
M llvm/test/CodeGen/AMDGPU/add_i64.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll
M llvm/test/CodeGen/AMDGPU/alignbit-pat.ll
M llvm/test/CodeGen/AMDGPU/allow-check.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-function-calls-option.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-es.ll
M llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp-on.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-psenable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll
M llvm/test/CodeGen/AMDGPU/amdpal-ps.ll
M llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll
M llvm/test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll
M llvm/test/CodeGen/AMDGPU/atomic_load_add.ll
M llvm/test/CodeGen/AMDGPU/atomic_load_sub.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/barrier-elimination.ll
M llvm/test/CodeGen/AMDGPU/basic-branch.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bfe-patterns.ll
M llvm/test/CodeGen/AMDGPU/bfi_nested.ll
M llvm/test/CodeGen/AMDGPU/bfm.ll
M llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
M llvm/test/CodeGen/AMDGPU/branch-uniformity.ll
M llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/call-constant.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
M llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
M llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll
M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
M llvm/test/CodeGen/AMDGPU/coalescer-identical-values-undef.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
M llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
M llvm/test/CodeGen/AMDGPU/coalescer_remat.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir
M llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
M llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir
M llvm/test/CodeGen/AMDGPU/combine-and-sext-bool.ll
M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
M llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
M llvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir
M llvm/test/CodeGen/AMDGPU/commute-compares.ll
M llvm/test/CodeGen/AMDGPU/commute_modifiers.ll
M llvm/test/CodeGen/AMDGPU/concat_vectors.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll
M llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll
M llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cttz-elts.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll
M llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll
M llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll
M llvm/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir
M llvm/test/CodeGen/AMDGPU/debug-value.ll
M llvm/test/CodeGen/AMDGPU/debug-value2.ll
M llvm/test/CodeGen/AMDGPU/debug_frame.ll
M llvm/test/CodeGen/AMDGPU/default_amdhsa_code_object_version.ll
M llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-xnor.ll
M llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll
M llvm/test/CodeGen/AMDGPU/eh_frame.ll
M llvm/test/CodeGen/AMDGPU/elf.ll
M llvm/test/CodeGen/AMDGPU/enable-no-signed-zeros-fp-math.ll
M llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll
M llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
M llvm/test/CodeGen/AMDGPU/exceed-max-sgprs.ll
M llvm/test/CodeGen/AMDGPU/extload-align.ll
M llvm/test/CodeGen/AMDGPU/extload-private.ll
M llvm/test/CodeGen/AMDGPU/extload.ll
M llvm/test/CodeGen/AMDGPU/extract-load-i1.ll
M llvm/test/CodeGen/AMDGPU/extract-lowbits.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector.ll
M llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
M llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
M llvm/test/CodeGen/AMDGPU/fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll
M llvm/test/CodeGen/AMDGPU/fadd.ll
M llvm/test/CodeGen/AMDGPU/fceil.ll
M llvm/test/CodeGen/AMDGPU/fceil64.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
M llvm/test/CodeGen/AMDGPU/ffloor.f64.ll
M llvm/test/CodeGen/AMDGPU/ffloor.ll
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/fma.f64.ll
M llvm/test/CodeGen/AMDGPU/fmax3.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.f64.ll
M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fmin3.ll
M llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
M llvm/test/CodeGen/AMDGPU/fmul.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg.f64.ll
M llvm/test/CodeGen/AMDGPU/fold-cndmask.mir
M llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
M llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
M llvm/test/CodeGen/AMDGPU/fold-fmul-to-neg-abs.ll
M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
M llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
M llvm/test/CodeGen/AMDGPU/fold-implicit-operand.mir
M llvm/test/CodeGen/AMDGPU/fold-over-exec.mir
M llvm/test/CodeGen/AMDGPU/fold-readlane.mir
M llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp-to-int-to-fp.ll
M llvm/test/CodeGen/AMDGPU/fp32_to_fp16.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.f64.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.f64.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpext.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/fract.f64.ll
M llvm/test/CodeGen/AMDGPU/fract.ll
M llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir
M llvm/test/CodeGen/AMDGPU/freeze-other-uses-issue-198094.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fsub.ll
M llvm/test/CodeGen/AMDGPU/ftrunc.ll
M llvm/test/CodeGen/AMDGPU/gep-address-space.ll
M llvm/test/CodeGen/AMDGPU/global-alias.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
M llvm/test/CodeGen/AMDGPU/global-constant.ll
M llvm/test/CodeGen/AMDGPU/global-directive.ll
M llvm/test/CodeGen/AMDGPU/global-extload-i16.ll
M llvm/test/CodeGen/AMDGPU/global_atomics.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/gv-const-addrspace.ll
M llvm/test/CodeGen/AMDGPU/hoist-cond.ll
M llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-deduced-arg-attr.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll
M llvm/test/CodeGen/AMDGPU/huge-number-operand-folds.mir
M llvm/test/CodeGen/AMDGPU/huge-private-buffer.ll
M llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir
M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll
M llvm/test/CodeGen/AMDGPU/icmp.i16.ll
M llvm/test/CodeGen/AMDGPU/icmp64.ll
M llvm/test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/indirect-private-64.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/invalid-inline-asm-constraint-crash.ll
M llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll
M llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
M llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
M llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
M llvm/test/CodeGen/AMDGPU/kernel-args.ll
M llvm/test/CodeGen/AMDGPU/kernel_code_t_recurse.ll
M llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/knownbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/lcssa-optnone.ll
M llvm/test/CodeGen/AMDGPU/lds-alignment.ll
M llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll
M llvm/test/CodeGen/AMDGPU/lds-size.ll
M llvm/test/CodeGen/AMDGPU/liveness.mir
M llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdiv.fast.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.clamp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.msad.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.decperflevel.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.incperflevel.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.hi.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sad.u8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.cos.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/llvm.rint.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-f64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i1.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i64.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/load-local-f32.ll
M llvm/test/CodeGen/AMDGPU/load-local-f64.ll
M llvm/test/CodeGen/AMDGPU/load-local-i1.ll
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
M llvm/test/CodeGen/AMDGPU/load-local-i32.ll
M llvm/test/CodeGen/AMDGPU/load-local-i64.ll
M llvm/test/CodeGen/AMDGPU/load-local-i8.ll
M llvm/test/CodeGen/AMDGPU/load-weird-sizes.ll
M llvm/test/CodeGen/AMDGPU/local-64.ll
M llvm/test/CodeGen/AMDGPU/local-atomics.ll
M llvm/test/CodeGen/AMDGPU/local-atomics64.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.xfail.mir
M llvm/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll
M llvm/test/CodeGen/AMDGPU/machinelicm-convergent.mir
M llvm/test/CodeGen/AMDGPU/machinelicm-copy-like-instrs.mir
M llvm/test/CodeGen/AMDGPU/mad24-get-global-id.ll
M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
M llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir
M llvm/test/CodeGen/AMDGPU/madmk.ll
M llvm/test/CodeGen/AMDGPU/max-sgprs.ll
M llvm/test/CodeGen/AMDGPU/max3.ll
M llvm/test/CodeGen/AMDGPU/mcp-use-before-def.mir
M llvm/test/CodeGen/AMDGPU/med3-no-simplify.ll
M llvm/test/CodeGen/AMDGPU/mem-builtins.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll
M llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-m0.mir
M llvm/test/CodeGen/AMDGPU/min3.ll
M llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
M llvm/test/CodeGen/AMDGPU/movrels-bug.mir
M llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
M llvm/test/CodeGen/AMDGPU/new-pm-machine-analysis.mir
M llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll
M llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir
M llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll
M llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll
M llvm/test/CodeGen/AMDGPU/nullptr.ll
M llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
M llvm/test/CodeGen/AMDGPU/opencl-image-metadata.ll
M llvm/test/CodeGen/AMDGPU/operand-spacing.ll
M llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/opt_exec_copy_fold.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
M llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir
M llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
M llvm/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll
M llvm/test/CodeGen/AMDGPU/peephole-opt-regseq-removal.mir
M llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
M llvm/test/CodeGen/AMDGPU/perfhint.ll
M llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/rcp_iflag.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll
M llvm/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir
M llvm/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll
M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
M llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
M llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir
M llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
M llvm/test/CodeGen/AMDGPU/register-count-comments.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir
M llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/reorder-stores.ll
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir
M llvm/test/CodeGen/AMDGPU/rotate-add.ll
M llvm/test/CodeGen/AMDGPU/rotl.i64.ll
M llvm/test/CodeGen/AMDGPU/rotl.ll
M llvm/test/CodeGen/AMDGPU/rotr.i64.ll
M llvm/test/CodeGen/AMDGPU/rotr.ll
M llvm/test/CodeGen/AMDGPU/s_movk_i32.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sched.barrier.inverted.mask.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
M llvm/test/CodeGen/AMDGPU/schedule-global-loads.ll
M llvm/test/CodeGen/AMDGPU/schedule-physregdeps.mir
M llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir
M llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
M llvm/test/CodeGen/AMDGPU/scratch-buffer.ll
M llvm/test/CodeGen/AMDGPU/sdivrem24.ll
M llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
M llvm/test/CodeGen/AMDGPU/select-opt.ll
M llvm/test/CodeGen/AMDGPU/selectcc-opt.ll
M llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
M llvm/test/CodeGen/AMDGPU/setcc-opt.ll
M llvm/test/CodeGen/AMDGPU/setcc-select-hi32mask.ll
M llvm/test/CodeGen/AMDGPU/setcc-select.ll
M llvm/test/CodeGen/AMDGPU/setcc-sext.ll
M llvm/test/CodeGen/AMDGPU/setcc.ll
M llvm/test/CodeGen/AMDGPU/setcc64.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
M llvm/test/CodeGen/AMDGPU/sgpr-to-vreg1-copy.mir
M llvm/test/CodeGen/AMDGPU/sgprcopies.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-nested-control-flows.ll
M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
M llvm/test/CodeGen/AMDGPU/si-i1-copies.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-body.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-latch.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-multi-entry-cycle.mir
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
M llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
M llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.ll
M llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
M llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll
M llvm/test/CodeGen/AMDGPU/smed3.ll
M llvm/test/CodeGen/AMDGPU/spill-before-exec.mir
M llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
M llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll
M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
M llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
M llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/AMDGPU/stack-size-overflow.ll
M llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir
M llvm/test/CodeGen/AMDGPU/store-barrier.ll
M llvm/test/CodeGen/AMDGPU/store-v3i64.ll
M llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
M llvm/test/CodeGen/AMDGPU/subreg_interference.mir
M llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir
M llvm/test/CodeGen/AMDGPU/target-cpu.ll
M llvm/test/CodeGen/AMDGPU/trap.ll
M llvm/test/CodeGen/AMDGPU/trunc-bitcast-vector.ll
M llvm/test/CodeGen/AMDGPU/trunc-cmp-constant.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-i1.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence-keep-copy-on-use.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
M llvm/test/CodeGen/AMDGPU/udivrem24.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.ll
M llvm/test/CodeGen/AMDGPU/umed3.ll
M llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
M llvm/test/CodeGen/AMDGPU/undef-build-vector.ll
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll
M llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
M llvm/test/CodeGen/AMDGPU/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll
M llvm/test/CodeGen/AMDGPU/v_mac.ll
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
M llvm/test/CodeGen/AMDGPU/verify-sop.mir
M llvm/test/CodeGen/AMDGPU/vgpr_constant64_to_sgpr.mir
M llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-debug-non-first-terminators.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-trailing.mir
M llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
M llvm/test/CodeGen/AMDGPU/wqm-debug-instr.mir
M llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll
M llvm/test/CodeGen/AMDGPU/zext-lid.ll
A llvm/test/CodeGen/BPF/BTF/struct-member-order.ll
A llvm/test/CodeGen/BPF/CORE/struct-member-order.ll
M llvm/test/CodeGen/DirectX/scalarize-dynamic-vector-index.ll
R llvm/test/CodeGen/NVPTX/address-folder.ll
R llvm/test/CodeGen/NVPTX/address-folder.mir
A llvm/test/CodeGen/SPIRV/pointers/global-vars-untyped.ll
R llvm/test/CodeGen/X86/large-implicit-section.ll
M llvm/test/ThinLTO/X86/memprof-icp.ll
A llvm/test/Transforms/GVN/invariant-load-intrinsic.ll
A llvm/test/Transforms/IndVarSimplify/exit-value-gep-inbounds.ll
A llvm/test/Transforms/InstCombine/invariant-load-like-sink.ll
A llvm/test/Transforms/LoopInterchange/transform-stop-partway.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void-inseltpoison.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void.ll
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-memory-op-decisions.ll
A llvm/test/Transforms/SLPVectorizer/WebAssembly/or-reduction-zero-test.ll
A llvm/test/Transforms/SLPVectorizer/X86/reduction-zero-test-ctpop.ll
M llvm/test/Transforms/SROA/struct-to-vector-fp-store-only-tail.ll
M llvm/test/Transforms/SROA/struct-to-vector.ll
M llvm/test/Transforms/Sink/invariant-load.ll
M llvm/unittests/ADT/ImmutableSetTest.cpp
M llvm/unittests/ADT/StringRefTest.cpp
M mlir/include/mlir/Dialect/OpenACC/OpenACCTypeInterfaces.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtils.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLOps.td
A mlir/lib/Dialect/OpenACC/Transforms/ACCEmitRemarksPrivate.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCSpecializeForHost.cpp
M mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtils.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
M mlir/lib/TableGen/CodeGenHelpers.cpp
A mlir/test/Dialect/OpenACC/acc-emit-remarks-private.mlir
M mlir/test/Dialect/OpenACC/acc-if-clause-lowering.mlir
A mlir/test/Dialect/OpenACC/acc-recipe-materialization-firstprivate-two-allocs.mlir
M mlir/test/Dialect/SPIRV/IR/gl-ops.mlir
M mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir
A mlir/test/IR/test-successor-verifier.mlir
M mlir/test/IR/visitors.mlir
M mlir/test/Target/SPIRV/gl-ops.mlir
M mlir/test/Target/SPIRV/ocl-ops.mlir
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/IR/TestVisitors.cpp
M mlir/test/mlir-tblgen/constraint-unique.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M offload/include/Shared/APITypes.h
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/common/src/RecordReplay.cpp
M offload/plugins-nextgen/cuda/dynamic_cuda/cuda.cpp
M offload/plugins-nextgen/cuda/dynamic_cuda/cuda.h
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/host/src/rtl.cpp
M offload/plugins-nextgen/level_zero/include/L0Kernel.h
M offload/plugins-nextgen/level_zero/src/L0Kernel.cpp
A offload/test/offloading/xteam_min_reduction_partial_wave.c
M openmp/device/src/Reduction.cpp
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/driver.bzl
Log Message:
-----------
Merge branch 'main' into users/kparzysz/unresolved-critical
Compare: https://github.com/llvm/llvm-project/compare/4b7b7ec920bd...ddc1588aaf55
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