[all-commits] [llvm/llvm-project] 647c29: [AArch64] Correct A510 scheduling information for ...

[John Brawn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 647c29886973c7111a32702e3c7a5ccc33a9feeb
      https://github.com/llvm/llvm-project/commit/647c29886973c7111a32702e3c7a5ccc33a9feeb
  Author: John Brawn <john.brawn at arm.com>
  Date:   2026-06-25 (Thu, 25 Jun 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SchedA510.td
    M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-neon-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-writeback.s

  Log Message:
  -----------
  [AArch64] Correct A510 scheduling information for LDn instructions (#205518)

The latency and throughput for these instructions don't match what's in
the A510 Software Optimization Guide, so adjust them so that they do
match. Also rearrange the definitions to match how they're structured in
the optimization guide and rename things in a similar manner to how the
C1 CPUs do things, as it's much clearer.



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