[all-commits] [llvm/llvm-project] 86c17e: [AArch64][SVE] Expose flags result of predicate-as...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 86c17ecd4cc558769be4ab87bf5c89061ea99f5d
      https://github.com/llvm/llvm-project/commit/86c17ecd4cc558769be4ab87bf5c89061ea99f5d
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2026-06-25 (Thu, 25 Jun 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td

  Log Message:
  -----------
  [AArch64][SVE] Expose flags result of predicate-as-counter whiles (NFC) (#202976)

For predicate-as-counter there is not "ptest" instruction. So unlike for
the SVE1 while instructions, we can't fold
`extract_vector_elt(pext(whilelo, 0), 0)` to PTEST_FIRST_ACTIVE, then
rely on the ptest elimination to remove redundant tests.

This patch instead adds new ISD nodes for predicate-as-counter while
instructions that return both the predicate and the status flags. This
will allow us to DAG combine `extract_vector_elt(pext(whilelo, 0), 0)`
to `CSET (whilelo, first)`. A further DAG combine could also fold the
`CSET` into a BR_CC (if it has one use).



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