[all-commits] [llvm/llvm-project] 42550d: [AMDGPU] Fixed crash due to virtual register defs ...
Dhruva Chakrabarti via All-commits
all-commits at lists.llvm.org
Wed Jun 24 16:47:27 PDT 2026
Branch: refs/heads/users/dhruvachak/issue-196671
Home: https://github.com/llvm/llvm-project
Commit: 42550d9152fe333f6076e6eaa20ed5bba0f919b3
https://github.com/llvm/llvm-project/commit/42550d9152fe333f6076e6eaa20ed5bba0f919b3
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-24 (Wed, 24 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-implicit-def-mir.mir
A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-implicit-def.ll
Log Message:
-----------
[AMDGPU] Fixed crash due to virtual register defs not dominating uses.
Fixes https://github.com/llvm/llvm-project/issues/196671.
Fixes duplicate ROCM-24494.
In Rewrite AGPR-Copy-MFMA pass, a spill reload may not have a dominating
spill store. If such a slot is unspilled into a vreg, the elimination
phase crashes because virtual register defs do not dominate all uses.
This patch fixes this problem by inserting IMPLICIT_DEFs on paths that
do not have a spill store.
This patch is based on suggestion by @ruiling on
https://github.com/llvm/llvm-project/pull/167347.
Compared to https://github.com/llvm/llvm-project/pull/167347 which bails
out if dominating defs are not found, this patch continues with spill
elimination by inserting implicit defs.
2 tests are added that check insertion of implicit defs.
Assisted-by: Cursor/Claude Opus
Commit: c704aee43fff03550479d2c39970b040d12076f2
https://github.com/llvm/llvm-project/commit/c704aee43fff03550479d2c39970b040d12076f2
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-24 (Wed, 24 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
Log Message:
-----------
Revert LSS-based implicit def insertion for missing dominating spill store.
Commit: f086f843ce64b5eaa0b64ab8101c328076be3480
https://github.com/llvm/llvm-project/commit/f086f843ce64b5eaa0b64ab8101c328076be3480
Author: theRonShark <rlieberm at amd.com>
Date: 2026-06-24 (Wed, 24 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
Log Message:
-----------
Verify dominance when rewriting spills to registers
Co-authored by: Austin Kerbow <Austin.Kerbow at amd.com>
Cherry-picked https://github.com/ROCm/llvm-project/commit/e5d02ddb
Commit: cfdad35a2325620ad7fee8479ce628412acc0d06
https://github.com/llvm/llvm-project/commit/cfdad35a2325620ad7fee8479ce628412acc0d06
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-24 (Wed, 24 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-implicit-def-mir.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-implicit-def.ll
Log Message:
-----------
Changed test debug message to reflect dominance check.
Commit: 69e950c3047781ecfcb4070a8254d9e5f201472f
https://github.com/llvm/llvm-project/commit/69e950c3047781ecfcb4070a8254d9e5f201472f
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-24 (Wed, 24 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-implicit-def-mir.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-implicit-def.ll
Log Message:
-----------
Ran instnamer to use named values.
Commit: 56de480e2025c160a95c7e781b790383d73300dd
https://github.com/llvm/llvm-project/commit/56de480e2025c160a95c7e781b790383d73300dd
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-24 (Wed, 24 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-implicit-def-mir.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-implicit-def.ll
Log Message:
-----------
Removed unneeded attributes.
Commit: d278856634ce858a5ac9f802b5ef7b22e19de958
https://github.com/llvm/llvm-project/commit/d278856634ce858a5ac9f802b5ef7b22e19de958
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-24 (Wed, 24 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-implicit-def-mir.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-implicit-def.ll
Log Message:
-----------
regex
Commit: d48ef10edc29938732430d348cf7a81f4f9c7ad0
https://github.com/llvm/llvm-project/commit/d48ef10edc29938732430d348cf7a81f4f9c7ad0
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-24 (Wed, 24 Jun 2026)
Changed paths:
R llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-implicit-def-mir.mir
R llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-implicit-def.ll
A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-joint-dom-mir.mir
A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-joint-dom.ll
Log Message:
-----------
Name cleanups.
Commit: 2333ef137627c65f76ca235aab5718f181f1b344
https://github.com/llvm/llvm-project/commit/2333ef137627c65f76ca235aab5718f181f1b344
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-24 (Wed, 24 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
Log Message:
-----------
Addressed review comments:
- Make isLoadJointlyDominatedByStores a member instead of lambda
- Remove Stores and Loads, instead use SpillReferences directly.
Commit: f820ece5dcce747d31458f6ec3538a4ae42df939
https://github.com/llvm/llvm-project/commit/f820ece5dcce747d31458f6ec3538a4ae42df939
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-24 (Wed, 24 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-joint-dom-mir.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-joint-dom.ll
Log Message:
-----------
Removed extra space from flat-wg-size.
Commit: 6911a98a9a65ff9a0bdb5b410e2530f5ba63323b
https://github.com/llvm/llvm-project/commit/6911a98a9a65ff9a0bdb5b410e2530f5ba63323b
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-24 (Wed, 24 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-joint-dom-mir.mir
Log Message:
-----------
Dropped IR section instructions, removed IR references.
Commit: 817bf6daefbcb2db410feabd080b11c178348dd6
https://github.com/llvm/llvm-project/commit/817bf6daefbcb2db410feabd080b11c178348dd6
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-24 (Wed, 24 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
Log Message:
-----------
Added braces to conform to AMDGPU coding style.
Compare: https://github.com/llvm/llvm-project/compare/8dfa78bee33a...817bf6daefbc
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