[all-commits] [llvm/llvm-project] 5ab7ad: [RISCV][XCV] Add missing IsRV32 predicate to the X...

[vitbur via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5ab7ad96b05277467b2bab27f510affd337fa3be
      https://github.com/llvm/llvm-project/commit/5ab7ad96b05277467b2bab27f510affd337fa3be
  Author: vitbur <vittorioburani at gmail.com>
  Date:   2026-06-23 (Tue, 23 Jun 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

  Log Message:
  -----------
  [RISCV][XCV] Add missing IsRV32 predicate to the XCVmac block (#205095)

The XCVmac instruction block was missing the `IsRV32` predicate that
every other XCV block already carries. `HasVendorXCVmac` on its own does
not require RV32, so `-mtriple=riscv64 -mattr=+xcvmac` could select
these RV32-only vendor instructions on RV64. Add `IsRV32` to the XCVmac
block to match the other XCV extensions and prevent selecting invalid
instructions on RV64.

Split out of #204879 at review request (one fix per PR).

Part of a CORE-V (XCV) series; see RFC:
https://discourse.llvm.org/t/rfc-core-v-xcv-support-for-cv32e40p-clang-builtins-xcvsimd-intrinsics-and-generic-auto-selection/91111



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