[all-commits] [llvm/llvm-project] c0a9c4: [LLVM] Fix a bug in auto upgrading lifetime start/...
Krzysztof Parzyszek via All-commits
all-commits at lists.llvm.org
Mon Jun 22 06:59:48 PDT 2026
Branch: refs/heads/users/kparzysz/m02-locator-frontend
Home: https://github.com/llvm/llvm-project
Commit: c0a9c4463b01afe6006012d38a4926dd317ec7f3
https://github.com/llvm/llvm-project/commit/c0a9c4463b01afe6006012d38a4926dd317ec7f3
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/IR/AutoUpgrade.cpp
A llvm/test/Assembler/autoupgrade-lifetime-intrinsics-invalid-decl.ll
Log Message:
-----------
[LLVM] Fix a bug in auto upgrading lifetime start/end intrinsics (#204601)
When creating the new intrinsic declaration, use the correct pointer
argument (arg #1) from the existing call. Currently, we use arg #0
(size) and end up creating an invalid intrinsic declaration. However,
later on we do not use this declaration directly and instead call
`CreateLifetimeStart` or `CreateLifetimeEnd` IRBuilder functions that
end up creating valid intrinsic declarations. The net result is that we
are left with a stray unused invalid declaration.
Fix this issue by creating the intrinsic with the right pointer argument
type.
Commit: de53dd06a2c3a3f4c58f057773bbfc0863f1fb75
https://github.com/llvm/llvm-project/commit/de53dd06a2c3a3f4c58f057773bbfc0863f1fb75
Author: Balaji V. Iyer. <43187390+bviyer at users.noreply.github.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M mlir/test/Analysis/DataFlow/test-staged-analyses.mlir
M mlir/test/lib/Analysis/TestDataFlowFramework.cpp
Log Message:
-----------
Added a check for unsigned integer before accessing (#204276)
Possible fix for #203862
Unsigned value is assumed but signed is possible. So added a check if it
is unsigned before accessing as unsigned, otherwise access as integer
and typecast to unsigned.
Commit: 1e2d1bbc12f6a5f5931c77d39894ee1b8679f5f8
https://github.com/llvm/llvm-project/commit/1e2d1bbc12f6a5f5931c77d39894ee1b8679f5f8
Author: Prasoon <prasoonkumar054 at gmail.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/utils/lit/lit/main.py
M llvm/utils/lit/lit/run.py
Log Message:
-----------
[lit] Migrate lit to ProcessPoolExecutor (#202681)
This PR is a foundational refactor for the lit single-process
re-architecture.
It migrates test execution from `multiprocessing.Pool` to
`concurrent.futures.ProcessPoolExecutor`. While the process model
remains unchanged (this is purely correctness and API modernization with
no behavior change on a passing suite), this migration establishes the
`concurrent.futures` API foundation required to introduce a
`ThreadPoolExecutor` backend in future PRs.
By collecting results with `as_completed` via an explicit `{future:
test}` map, this refactor also fixes two latent bugs:
1. **Stale timeout bug**: The per-iteration timeout budget was
previously computed once and reused. It is now correctly anchored to an
absolute deadline.
2. **Submission-order coupling**: Results are now safely routed by
future identity rather than submission index.
Signed-off-by: Prasoon Kumar <prasoonkumar054 at gmail.com>
Commit: 154115307ba171489125550ece373302f0ab01e1
https://github.com/llvm/llvm-project/commit/154115307ba171489125550ece373302f0ab01e1
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/test/Driver/hip-toolchain-rdc-static-lib.hip
M clang/test/Driver/hip-toolchain-rdc.hip
Log Message:
-----------
[HIP] Remove default `-flto-partitions=8` in the HIP toolchain (#203948)
Summary:
This was added and made it into a release, but it never should've been a
default argument. Partitioning the LTO is a fundamentally different
compilation model and has real impacts on the generated code. Right now
it is added silently, which breaks non-Hostcall printf and degreades
performance due to split uselists.
This is a contract that should not be made default. "Compile times" is
not a justification to silently change compilation semantics, that is
the user's build system's job. Parititioning to a magic number is not an
appropriate solution when passing -flto-partitions=8 or `-Xarch_device
-flto-partitions=8` is perfectly viable and not hidden from the user.
This resolves the 12% performance regression observed when switching to
the LTO toolchain in HIP for dcsrgemm.
Commit: bd5da5b539d471f909d75268a8ae8ceeb22a3300
https://github.com/llvm/llvm-project/commit/bd5da5b539d471f909d75268a8ae8ceeb22a3300
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M lldb/test/API/functionalities/breakpoint/cpp_exception/TestCPPExceptionBreakpoint.py
M lldb/test/API/functionalities/exec/TestExec.py
M lldb/test/API/functionalities/fork/resumes-child/TestForkResumesChild.py
M lldb/test/API/functionalities/inferior-changed/TestInferiorChanged.py
M lldb/test/API/functionalities/inferior-crashing/TestInferiorCrashing.py
M lldb/test/API/functionalities/inferior-crashing/TestInferiorCrashingStep.py
M lldb/test/API/functionalities/inferior-crashing/recursive-inferior/TestRecursiveInferior.py
M lldb/test/API/functionalities/inferior-crashing/recursive-inferior/TestRecursiveInferiorStep.py
M lldb/test/API/functionalities/longjmp/TestLongjmp.py
M lldb/test/API/functionalities/process_group/TestChangeProcessGroup.py
M lldb/test/API/lang/cpp/exceptions/TestCPPExceptionBreakpoints.py
M lldb/test/API/lang/cpp/floating-types-specialization/TestCppFloatingTypesSpecialization.py
M lldb/test/API/tools/lldb-dap/exception/cpp/TestDAP_exception_cpp.py
Log Message:
-----------
[lldb][test] Skip wasm-unsupported API tests (#204625)
WebAssembly inferiors are built with -fno-exceptions and run on a wasip1
runtime with no exec/fork/setpgid, no setjmp/longjmp (needs the
exception-handling proposal), no memory-protection faults/signals, and
no _Float16/__bf16 support. Mark the corresponding API tests as skipped
on wasm so they report unsupported instead of failing to build or run.
Commit: 74a146dd9c28c083db057d7f87afbcc617319392
https://github.com/llvm/llvm-project/commit/74a146dd9c28c083db057d7f87afbcc617319392
Author: Mark Zhuang <mark.zhuang at spacemit.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M openmp/runtime/src/ompd-specific.cpp
Log Message:
-----------
[OpenMP] Improve dladdr error handling in ompd_init() (#201043)
Guard dlerror() result against NULL before passing to fprintf to avoid
confusing "(null)" output. Also guard dli_fname against NULL on the
success path before calling strrchr.
Assisted-by: Claude Sonnet 4.6
Commit: d81069d7c3da46ea7bd000c3d6ab618e3db79bd4
https://github.com/llvm/llvm-project/commit/d81069d7c3da46ea7bd000c3d6ab618e3db79bd4
Author: Mark Zhuang <mark.zhuang at spacemit.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M openmp/runtime/CMakeLists.txt
M openmp/runtime/cmake/config-ix.cmake
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_config.h.cmake
M openmp/runtime/src/z_Linux_util.cpp
Log Message:
-----------
[OpenMP] Control KMP_CANCEL_THREADS via CMake and detect pthread_cancel (#193681)
KMP_CANCEL_THREADS was a preprocessor switch in kmp.h, with Android and
WASI explicitly #undef-ing it. Move the control to CMake:
- Detect pthread_cancel via check_symbol_exists()
- Drive KMP_CANCEL_THREADS from that result, emitted as a 0/1 #define in
kmp_config.h.cmake (overridable with -DLIBOMP_USE_CANCEL_THREADS=OFF).
- Drop the Android/WASM special-casing
Commit: 42058d48ef4b1de3c0b11ac59a1edca35f82db74
https://github.com/llvm/llvm-project/commit/42058d48ef4b1de3c0b11ac59a1edca35f82db74
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
Log Message:
-----------
AMDGPU/GlobalISel: Regbanklegalize rules for G_INTRINSIC_FPTRUNC_ROUND (#185491)
Commit: 0f707d4dd7f098d254551f69306845bfaebb9ce4
https://github.com/llvm/llvm-project/commit/0f707d4dd7f098d254551f69306845bfaebb9ce4
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
Log Message:
-----------
[RISCV] Remove unused CHECK prefixes in `rvp-simd-32.ll` (#204383)
They were probably introduced by merge conflicts + UTC script changes.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: fb6e3c8c36ba8412d6860ffe1013c1c66860a487
https://github.com/llvm/llvm-project/commit/fb6e3c8c36ba8412d6860ffe1013c1c66860a487
Author: Alexis Perry-Holby <aperry at lanl.gov>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
A flang/docs/MeetingNotes/2026/2026-06-17.md
Log Message:
-----------
[flang] Add Flang Community Call Notes from June 17th meeting (#204622)
Commit: 0a73d41791b858b9107f64d39b7541e8b3a2f230
https://github.com/llvm/llvm-project/commit/0a73d41791b858b9107f64d39b7541e8b3a2f230
Author: YongKang Zhu <yongzhu at fb.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M bolt/lib/Passes/LongJmp.cpp
Log Message:
-----------
[BOLT][AArch64] Only reserve constant-island space when an island exists (#204261)
`tentativeLayout()` aligns every function's tail to its constant island
alignment even when the function has no constant island. This over-padded
nearly every function, drifting tentative layout from emitted layout non
trivially, while the emitter only pads when emitting real constant island.
Guard with `estimateConstantIslandSize() > 0` so tentative better matches
emitted.
Commit: 8c6409765283993193ae63e3685858886a69f952
https://github.com/llvm/llvm-project/commit/8c6409765283993193ae63e3685858886a69f952
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M lldb/source/Host/windows/PythonRuntimeLoaderWindows.cpp
Log Message:
-----------
[lldb][Windows] fix missing include (#204628)
lldb fails to build when `LLDB_PYTHON_DLL_RELATIVE_PATH` is set because
of a missing include.
Commit: 2b76fe3877b626020dbc1aecbaab61a77d835f21
https://github.com/llvm/llvm-project/commit/2b76fe3877b626020dbc1aecbaab61a77d835f21
Author: Zorojuro <sawantsukumar at gmail.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M libc/src/math/docs/add_math_function.md
Log Message:
-----------
[libc][docs] Fix file path for fputil (#204534)
Fixes a nit in the file path ( replaces `FPUtils` correctly with `FPUtil` )
Commit: 4a86da464e16b8f18d105e620268db3ef808da97
https://github.com/llvm/llvm-project/commit/4a86da464e16b8f18d105e620268db3ef808da97
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/fuzz/CMakeLists.txt
R compiler-rt/lib/scudo/standalone/fuzz/get_error_info_fuzzer.cpp
M compiler-rt/lib/scudo/standalone/include/scudo/interface.h
M compiler-rt/lib/scudo/standalone/wrappers_c.cpp
Log Message:
-----------
[scudo] Remove static error info functions. (#204483)
Android was the only platform using the static error info functions. The
latest Android no longer uses them, so delete these unused functions.
These functions were implicitly exporting implementation details and
made it difficult to implement the multi-region code. This is the final
step to submit the multi-region code and modify how the region code
works.
Remove the error info fuzzer since that was only necessary since so many
values were passed in to the function.
Commit: e5ce3ed2f4ab0723e91c8d8aa04e254b8a217dc6
https://github.com/llvm/llvm-project/commit/e5ce3ed2f4ab0723e91c8d8aa04e254b8a217dc6
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
Log Message:
-----------
[SLP][NFC]Add a test with rt checks in optsize function, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/204646
Commit: 0edadae062e0e9a2d2f87c2f9f61cfdac7bedb28
https://github.com/llvm/llvm-project/commit/0edadae062e0e9a2d2f87c2f9f61cfdac7bedb28
Author: vitbur <vittorioburani at gmail.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/test/CodeGen/RISCV/xcvbitmanip.ll
Log Message:
-----------
[RISCV][XCV] Fix incorrect llvm.ctlz lowering to cv.fl1 (#197288)
Fixes #197006.
The XCVbitmanip pattern `def : PatGpr<ctlz, CV_FL1, i32>;` is
semantically incorrect: `cv.fl1` returns a bit position while
`llvm.ctlz` returns a leading-zero count. They differ by up to 31 on
every non-zero input, miscompiling every use of `__builtin_clz`,
including compiler-rt's `__udivdi3`.
This PR:
- Replaces the pattern with one matching `llvm.ctlz` with
`is_zero_poison=true`, lowered to `xori (cv.fl1 rs1), 31`.
- Adds explicit `setOperationAction` calls in `RISCVISelLowering.cpp`
to route `ISD::CTLZ` to generic expansion and keep
`ISD::CTLZ_ZERO_*` matched by the `.td` pattern.
The companion `def : PatGpr<cttz, CV_FF1, i32>;` is correct as-is
(both return 32 on zero, coincide on non-zero), and is left
untouched.
See the linked issue for the full analysis including a CV32E40P sim
trace showing miscompilation of `__udivdi3` in compiler-rt.
Commit: ece20ef68083e29fe450a8f188ce90fbd2bb6356
https://github.com/llvm/llvm-project/commit/ece20ef68083e29fe450a8f188ce90fbd2bb6356
Author: Jeremy Kun <jkun at google.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
A mlir/test/Conversion/MemRefToEmitC/memref-with-custom-types.mlir
M mlir/test/lib/Dialect/Test/CMakeLists.txt
M mlir/test/lib/Dialect/Test/TestDialectInterfaces.cpp
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[mlir][emitc] Apply type converter to memref element types in -convert-memref-to-emitc (#203742)
This change fixes a few places where the memref-to-emitc
conversion didn't properly convert memref element types.
This PR updates both memref.alloc and memref.copy to convert the memref
element type when using the element type for `sizeof` calls, as well as
generating the output pointer type (just for `alloc`).
This was missed because there are no `convert-to-emitc` tests that use a
type converter with custom types, so I added such a registration to the
test dialect. It is worth noting that, while this patch only affects
`-convert-memref-to-emitc`, the change has no impact without the
additional type converter registrations in `-convert-to-emitc` because
there are no builtin types that have nontrivial emit conversions today.
As a drive-by improvement, I deduped a "total size in bytes" calculation
that was happening in the lowerings for both `memref.alloc` and
`memref.copy`.
Commit: 410484f0b82017cc5ee7d70c2499446e8bc1f110
https://github.com/llvm/llvm-project/commit/410484f0b82017cc5ee7d70c2499446e8bc1f110
Author: Yao Qi <yao_qi at apple.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M lldb/source/Plugins/ObjectContainer/Universal-Mach-O/ObjectContainerUniversalMachO.cpp
M lldb/unittests/CMakeLists.txt
A lldb/unittests/ObjectContainer/CMakeLists.txt
A lldb/unittests/ObjectContainer/ObjectContainerUniversalMachOTest.cpp
Log Message:
-----------
[lldb][Mach-O] Fix two fuzzer-found hangs/crashes parsing universal Mach-O fat headers (#204471)
This fixes two denial-of-service issues in the universal (fat) Mach-O
container parser, both found by `lldb-target-fuzzer` and both reachable
from
`SBDebugger::CreateTarget` → `ObjectFile::GetModuleSpecifications` →
`ObjectContainerUniversalMachO::{GetModuleSpecifications,ParseHeader}`.
### 1. Bound the fat header arch loop by available data
`ParseHeader` read the untrusted 32-bit `nfat_arch` field and used it
directly
as the loop bound when indexing the `fat_arch` records, without
validating it
against the data actually present. A crafted header claiming
`nfat_arch = 0xFFFFFFFF` with only a few bytes of payload made the loop
spin
~4.29 billion times — `ValidOffsetForDataOfSize()` fails on every
iteration
past the real data, but the loop keeps going up to `nfat_arch`, so the
call
never returns in practice (~20 minutes under ASan). The reduced
reproducer is
40 bytes.
Fix: break out of the loop as soon as the next `fat_arch` record no
longer fits
in the remaining data. This is behavior-preserving — a failed
`ValidOffsetForDataOfSize` never advanced the offset, so the set of
parsed
`fat_archs` is unchanged; it just stops the useless spinning.
### 2. Reject self-referential slices in the fat container
`GetModuleSpecifications` re-parses every fat slice by recursing into
`ObjectFile::GetModuleSpecifications` at the slice's offset, with no
recursion-depth limit and no check that a slice advances past the
current
offset. A slice whose offset is 0 produces a recursive call with
identical
arguments (same file, same offset, same size) and recurses until the
stack
overflows. Fixing the `nfat_arch` loop bound above unmasked this for the
same
input: the initial 512-byte read zero-pads a short file, `ParseHeader`
then
parses a trailing all-zero arch record whose offset is 0, and the slice
recurses on itself.
Fix: require `slice_file_offset > file_offset` before recursing, so
every
recursive call strictly advances into the file. Offsets at or before the
current offset (including 0) and offsets inside the fat header are
skipped.
### Tests
Two API tests in `TestTargetCommand.py`, each with a `yaml2obj` fixture:
- `fat_nfat_arch_huge.yaml` — `nfat_arch = 0xFFFFFFFF` with a single
real
slice; `target create` must complete promptly.
- `fat_slice_offset_zero.yaml` — a self-referential slice at offset 0;
`target create` must skip it and fail gracefully ("is not a valid
executable") rather than crashing.
Commit: feace0917af56e35550e459e3abf41acdea1b6a9
https://github.com/llvm/llvm-project/commit/feace0917af56e35550e459e3abf41acdea1b6a9
Author: David Green <david.green at arm.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
R llvm/test/CodeGen/AArch64/aggressive-interleaving.ll
A llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll
Log Message:
-----------
[AArch64] Move aggressive-interleaving.ll test to LoopVectorizer tests. NFC (#204652)
It looks like this test was put into CodeGen where it would better live
with
other vectorizer tests in Transforms/LoopVectorize/AArch64.
Commit: 150ddcf32ba27b1555bcafbb58356537a1c4aa73
https://github.com/llvm/llvm-project/commit/150ddcf32ba27b1555bcafbb58356537a1c4aa73
Author: Guo Chen <guochen2 at amd.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll
A llvm/test/CodeGen/AMDGPU/spillv16Kernel.mir
Log Message:
-----------
[AMDGPU][True16] NFC. update two lit test for spill v16 (#203922)
Follow up from
https://github.com/llvm/llvm-project/pull/203589#discussion_r3406309174.
Update two tests
Commit: 075795005ef85e933f5ff63ef7004a4dab655946
https://github.com/llvm/llvm-project/commit/075795005ef85e933f5ff63ef7004a4dab655946
Author: janr-bay <jrehders at baylibre.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/include/llvm/ADT/APFloat.h
M llvm/lib/Support/APFloat.cpp
M llvm/unittests/ADT/APFloatTest.cpp
Log Message:
-----------
[APFloat] Extend fltSemantics and drop special case E8M0 bit conversionJan/apfloat e8m0 (#204200)
This is one step towards being able to make APFloat extensible with
custom formats in the future.
fltSemantics gained a new flag to indicate lack of denormal support.
Combined with hasZero = 0 it means exponent 0 does not have a special
meaning. This makes it possible to remove the special case
implementation for initFromFloat8E8M0FNUAPInt and handle it in the
generic version.
The generic initFromIEEEAPInt function now also supports existing
fltSemantics flags for hasZero, and hasSignedRepr which where only
needed in the specialized initFromFloat8E8M0FNUAPInt.
Also adds new tests for bitcasting to and from APInt. There are several
tests involving bitcastToAPInt together with convert functions but none
explicitly verify the functionality of bitcastToAPInt.
The implementations of convertIEEEFloatToAPInt and initFromIEEEAPInt
also diverged a bit in the past and have been synchronized, again. This
is a separate commit as it is not strictly required and could be dropped
if the risk is considered higher than it's benefit and so it can be
tested independently.
Commit: 77f7abc772e85fbe2a1f2b21d3614334cf0041fd
https://github.com/llvm/llvm-project/commit/77f7abc772e85fbe2a1f2b21d3614334cf0041fd
Author: Folkert de Vries <folkert at folkertdev.nl>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/Analysis/CostModel/AArch64/clmul-fixed.ll
M llvm/test/Analysis/CostModel/AArch64/clmul-scalable.ll
M llvm/test/Analysis/CostModel/AArch64/clmul.ll
M llvm/test/Analysis/CostModel/X86/clmul.ll
M llvm/test/CodeGen/AArch64/clmul-fixed.ll
M llvm/test/CodeGen/AArch64/clmul-scalable.ll
M llvm/test/CodeGen/AArch64/clmul.ll
M llvm/test/CodeGen/AMDGPU/clmul.ll
M llvm/test/CodeGen/PowerPC/clmul-vector.ll
M llvm/test/CodeGen/RISCV/clmul.ll
M llvm/test/CodeGen/RISCV/clmulh.ll
M llvm/test/CodeGen/RISCV/clmulr.ll
M llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmul.ll
M llvm/test/CodeGen/Thumb2/mve-clmul.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/clmul.ll
Log Message:
-----------
[ISel] Improve `clmul` fallback implementation for `i32` and `i64` (#203727)
Improve the `clmul` fallback implementation for `i32..=i64`.
The new approach is "multiplication with holes", based on [bearssl
source](https://github.com/unkaktus/bearssl/blob/6a1dab03beac9a324fdaed36ffdeb5081ac64b9a/src/hash/ghash_ctmul64.c#L27-L56),
https://www.bearssl.org/constanttime.html#ghash-for-gcm, and the
[polyval](https://github.com/RustCrypto/universal-hashes/blob/815ddc90ea652b09804565e193e34784c94a3849/polyval/src/field_element/soft.rs#L74-L108)
crate. https://www.bearssl.org/constanttime.html#ghash-for-gcm explains
the idea.
Future work is
- extend the fallback to smaller integer types. These can use a smaller
hole (the wider hole works but uses more instructions than the naive
fallback)
- investigate how to extend this approach to wider integers. We can use
wider holes, but a recursive definition defined in terms of smaller
integer types might be better.
https://timtaubert.de/blog/2017/06/verified-binary-multiplication-for-ghash/
has some good info.
I've tested this locally with a fuzzer against the current LLVM
implementation (via the rust standard library) and `pclmulqdq`.
CC https://github.com/llvm/llvm-project/issues/203694
CC: @RKSimon, @topperc, @eisenwave, @xarkenz, @artagnon.
Commit: 3aad8a1e53acfaf5af909dd7c4e14096a5baae1c
https://github.com/llvm/llvm-project/commit/3aad8a1e53acfaf5af909dd7c4e14096a5baae1c
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
A llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
Log Message:
-----------
[AMDGPU] Classify VMEM as VMEM for CoExecSched (#203396)
Previously classifyFlavor wasn't classifying buffer_loads as VMEM
Commit: bb2fcd01b8008779c2c1f178599bc22a94daa3d4
https://github.com/llvm/llvm-project/commit/bb2fcd01b8008779c2c1f178599bc22a94daa3d4
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
A llvm/test/CodeGen/AMDGPU/mir-dynamic-vgpr-block-size-roundtrip.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
Log Message:
-----------
[AMDGPU][MFI] Implement missing deserialization of dynamicVGPRBlockSize (#201939)
dynamicVGPRBlockSize can be set by the amdgpu-dynamic-vgpr-block-size
attribute. MFI takes precedence when we deserialize.
Commit: 2bbec86cc5835e10085d4598d4ff189bf89fc194
https://github.com/llvm/llvm-project/commit/2bbec86cc5835e10085d4598d4ff189bf89fc194
Author: Scott Linder <scott.linder at amd.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst
Log Message:
-----------
[AMDGPU][docs] Correct DWARF extension attribute encodings (#204419)
These were not updated when the final numbers were committed in
Dwarf.def, so update them now.
Change-Id: Ide931b835dc2c5def60dd7fad29525f598e8c8b6
Commit: a7a3849b63d17494866cd697e958e53aa1b3aed2
https://github.com/llvm/llvm-project/commit/a7a3849b63d17494866cd697e958e53aa1b3aed2
Author: Yuyang Zhang <yuyzhang at amd.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
Log Message:
-----------
[InstCombine] Drop assumption-cache update in freezeOtherUses (#204599)
Redundant now that freezeOtherUses re-queues the rewritten users
(#202306), which re-processes them in the same iteration. Added in
#192935 to avoid a fixpoint-verifier failure.
Commit: 05ca09a60323f18a7cdf6dd67b54f057a54049fd
https://github.com/llvm/llvm-project/commit/05ca09a60323f18a7cdf6dd67b54f057a54049fd
Author: Kunal Pathak <kunalspathak.github at gmail.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
A llvm/test/Transforms/SimplifyCFG/AArch64/two-entry-phi-fold-unpredictable.ll
Log Message:
-----------
[AArch64][TTI] Surface per-CPU branch misprediction penalty to SimplifyCFG (#201484)
AArch64 scheduling models already define `MispredictPenalty` per CPU
(e.g.,
Neoverse V2 = 11, Cortex-A55 = 8, Cyclone = 16), but this value was
never surfaced through TargetTransformInfo. The base class default of 0
effectively disabled profile-guided speculation of unpredictable
branches
in SimplifyCFG's foldTwoEntryPHINode.
Override `getBranchMispredictPenalty` in AArch64TTIImpl to read from the
scheduling model, enabling SimplifyCFG to speculate instructions into
conditional selects when the speculation cost is justified by the
misprediction penalty, matching the behavior X86 already has (hardcoded
at 14 cycles).
Godbolt: https://godbolt.org/z/68czz556j
(note: I am not sure why godbolt is not showing the compiler I saved,
but essentially the example shows the comparison of aarch64 clang vs.
gcc with `-O3` flags)
---------
Co-authored-by: Kunal Pathak <kupathak at fb.com>
Commit: 9824d350b87a7c1f813268dc66a3f311a57d0448
https://github.com/llvm/llvm-project/commit/9824d350b87a7c1f813268dc66a3f311a57d0448
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/ObjCLanguageRuntime.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/ObjCLanguageRuntime.h
A lldb/test/Shell/Expr/wasm-no-objc-codegen.test
Log Message:
-----------
[lldb] Don't enable Objective-C in expressions on unsupported formats (#204639)
Evaluating any expression against a WebAssembly target aborted LLDB:
```
(lldb) expr (int)sizeof(Point)
LLVM ERROR: Objective-C support is unimplemented for object file format
```
WebAssembly can't JIT expressions (RuntimeDyld doesn't support the Wasm
object format, so ProcessWasm sets CanJIT to false), but it can handle
simple expressions that can be IR interpreted.
When setting up the expression's language options, LLDB speculatively
enables Objective-C, which trips up the fatal error as Objective-C code
generation only supports Mach-O, ELF, and COFF.
Add ObjCLanguageRuntime::IsSupportedForArchitecture and disable
Objective-C in the expression's language options when the target's
object file format can't support it, parsing as C/C++ instead. The IR
interpreter can then evaluate what it supports, and the rest fails
cleanly instead of crashing.
Commit: 0607caafdf51a4cddc123fc3a3d78bb244854a85
https://github.com/llvm/llvm-project/commit/0607caafdf51a4cddc123fc3a3d78bb244854a85
Author: Osman Yasar <osmanyas05 at gmail.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/include/llvm/Target/GlobalISel/Combine.td
A llvm/test/CodeGen/AArch64/GlobalISel/combine-or-and-xor.ll
A llvm/test/CodeGen/AArch64/GlobalISel/combine-or-and-xor.mir
M llvm/test/CodeGen/AMDGPU/bitop3-shared-operand.ll
Log Message:
-----------
[GlobalISel] Add `or_and_xor_to_or` pattern from SelectionDAG (#204614)
PR #201108 was merged and then reverted due to a failing test. This PR
fixes the tests that failed.
Commit: a358c6cac126c4088ae0bb7308acb59ad6cdd8b8
https://github.com/llvm/llvm-project/commit/a358c6cac126c4088ae0bb7308acb59ad6cdd8b8
Author: gulfemsavrun <gulfem at google.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
Log Message:
-----------
[CMake][Fuchsia] Add llvm-profgen to Fuchsia toolchain (#204638)
Commit: d0283591800c1ae5018f665e452743fcb778c9dc
https://github.com/llvm/llvm-project/commit/d0283591800c1ae5018f665e452743fcb778c9dc
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.h
A llvm/test/tools/dsymutil/X86/fat-multiarch-parallel-link.test
Log Message:
-----------
[DWARFLinker] Fix data race on the global parallel strategy (#204642)
DWARFLinkerImpl::link() assigned the process-global
llvm::parallel::strategy on entry. dsymutil runs link() concurrently,
one call per architecture of a universal binary, so those assignments
race. An inconsistent strategy can route per-compile-unit cloning onto a
thread that is not an llvm::parallel ThreadPoolExecutor worker, where
the per-thread allocators call getThreadIndex().
This manifested itself as an assert, but otherwise returns in a
out-of-bounds.
```
Assertion failed: ((threadIndex != UINT_MAX) && "getThreadIndex() must be called from a thread created by " "ThreadPoolExecutor"), function getThreadIndex, file Parallel.h, line 51.
```
The assert is non-deterministic and needs more than one architecture to
reproduce.
Set the strategy under llvm::call_once so only the first link writes it.
Base it on the requested thread count, which is the same for every
architecture, rather than the per-architecture compile-unit count the
code used before which would race.
rdar://179339642
Commit: adae5c0902cd05bc682a18971d7261da006471a1
https://github.com/llvm/llvm-project/commit/adae5c0902cd05bc682a18971d7261da006471a1
Author: LU-JOHN <John.Lu at amd.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
Log Message:
-----------
[AMDGPU] Fix 64->32 bit division corner case (#204469)
Do not implement 64-bit signed division with 32-bit division if operands
are only constrained to a 32-bit signed range.
-2147483648/-1 != -2147483648/1, but their lower 32-bits are identical.
32-bit division cannot generate the correct result for both sets of
operands. Only use 32-bit division if operands are constrained to a
31-bit signed range.
Bug appears in both AMDGPUCodeGenPrepare.cpp and AMDGPUISelLowering.cpp.
Tested in https://github.com/llvm/llvm-test-suite/pull/428.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: 01b8de8010d7590877c1fe5d9984706c808202c0
https://github.com/llvm/llvm-project/commit/01b8de8010d7590877c1fe5d9984706c808202c0
Author: Sairudra More <sairudra60 at gmail.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/openmp-taskloop-reduction.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[mlir][OpenMP] Translate reductions on taskloop (#199670)
This patch adds LLVM IR translation for `reduction` and `in_reduction`
clauses on `omp.taskloop.context`.
For `taskloop reduction`, the lowering emits the implicit taskgroup
reduction setup, builds the task-reduction descriptor array, and maps
each generated task to runtime-provided private reduction storage
through `__kmpc_task_reduction_get_th_data`.
For `taskloop in_reduction`, the lowering uses the same runtime lookup
path with a null descriptor, allowing the runtime to find the enclosing
task-reduction context.
Unsupported byref, cleanup-region, and two-argument initializer forms
remain diagnosed.
### Stack / review order
This PR is part of the OpenMP task-reduction translation stack:
1. #199565 — `omp.taskgroup task_reduction` translation
2. #199670 — `omp.taskloop` `reduction` / `in_reduction` translation
3. #202611 — explicit `omp.task in_reduction` translation
Related sibling follow-up:
* #199967 — `omp.target in_reduction` host-fallback lowering
The intended main review order is:
#199565 → #199670 → #202611
This PR is stacked on #199565. Please review only the taskloop changes
in this PR for now. Once #199565 lands, I will rebase this branch onto
`main` so the diff contains only this patch.
Part of #199560.
Commit: 631aa1c8fdb4b720accf1ea1576ffbb05fbdce38
https://github.com/llvm/llvm-project/commit/631aa1c8fdb4b720accf1ea1576ffbb05fbdce38
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/openmp/runtime/src/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes d81069d (#204629)
This fixes d81069d7c3da46ea7bd000c3d6ab618e3db79bd4.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: e99e343dfdb2b1b490789a7bcba6d646a4824f15
https://github.com/llvm/llvm-project/commit/e99e343dfdb2b1b490789a7bcba6d646a4824f15
Author: mygitljf <101249452+mygitljf at users.noreply.github.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Fix annotation of alternative operator and (#199112)
I now annotate`and` as TT_BinaryOperator before the pointer/reference
heuristic. I left `bitand` alone since, like `&`, it can still be a
reference.
Fixes #199027.
Commit: 6c118c38a87620850ff21e3c4aa1817c9ecde5a6
https://github.com/llvm/llvm-project/commit/6c118c38a87620850ff21e3c4aa1817c9ecde5a6
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/trans-coexecution-hazard.mir
Log Message:
-----------
[AMDGPU] Remove TransCoexecutionHazard feature from gfx13 (#204645)
No TRANS coexecution hazard on gfx13 based on the latest SPG.
Commit: 2848608d11ef6214c611045c7f56132bf4aae803
https://github.com/llvm/llvm-project/commit/2848608d11ef6214c611045c7f56132bf4aae803
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/wmma-coexecution-valu-hazards.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
Log Message:
-----------
[AMDGPU] Introduce WMMACoexecutionHazards target feature (#204654)
gfx1250, gfx1251 and gfx12-5-generic have this feature, but gfx1310
does not have it.
Commit: 8c3fc449d742055dc3a596b0cce0988bd199b1d9
https://github.com/llvm/llvm-project/commit/8c3fc449d742055dc3a596b0cce0988bd199b1d9
Author: mygitljf <101249452+mygitljf at users.noreply.github.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Fix crash on malformed operator input (#199098)
fixes the remaining clang-format crash case after #199100 landed.
The problematic input is:
```cpp
{ operator } a
```
When annotating operator, clang-format should stop scanning at } instead
of consuming it and disturbing brace scope tracking. And adds a no-crash
regression test for it.
Commit: 19f6c18e389bfea2885179fb4f50e019ef7ea002
https://github.com/llvm/llvm-project/commit/19f6c18e389bfea2885179fb4f50e019ef7ea002
Author: Wael Yehia <wmyehia2001 at yahoo.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
Log Message:
-----------
[NFC] Add comments and Fix No-Asserts build by using [[maybe_unused]] (#202488) (#204672)
Co-authored-by: Wael Yehia <wyehia at ca.ibm.com>
Commit: df9b1f89a4f4f0c7b5afc03d273a825caef268fb
https://github.com/llvm/llvm-project/commit/df9b1f89a4f4f0c7b5afc03d273a825caef268fb
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M clang/docs/UsersManual.rst
M clang/include/clang/Options/Options.td
M clang/test/Driver/femit-dwarf-unwind.c
M clang/test/Driver/femit-dwarf-unwind.s
M clang/tools/driver/cc1as_main.cpp
M llvm/include/llvm/MC/MCTargetOptions.h
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
A llvm/test/MC/AArch64/compact-unwind-force-dwarf.s
M llvm/test/MC/MachO/ARM/compact-unwind-armv7k.s
A llvm/test/MC/X86/compact-unwind-force-dwarf.s
Log Message:
-----------
[clang][Mach-O] Add an option to force UNWIND_*_MODE_DWARF compact unwind info (#204005)
The new option value extends: `-femit-dwarf-unwind=dwarf-only`. This is
primarily intended as a testing mechanism to ensure coverage on the
DWARF-only parts of the unwinder, where previously the compact unwinder
would have taken care of most functions.
Commit: 0f4d8cefbf0e00e560d57cffe84064d1887246b4
https://github.com/llvm/llvm-project/commit/0f4d8cefbf0e00e560d57cffe84064d1887246b4
Author: Łukasz Plewa <lukasz.plewa at intel.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M offload/plugins-nextgen/level_zero/include/L0CmdListManager.h
M offload/plugins-nextgen/level_zero/include/L0Context.h
M offload/plugins-nextgen/level_zero/include/L0Device.h
M offload/plugins-nextgen/level_zero/include/L0Queue.h
M offload/plugins-nextgen/level_zero/src/L0Context.cpp
M offload/plugins-nextgen/level_zero/src/L0Device.cpp
M offload/plugins-nextgen/level_zero/src/L0Queue.cpp
M offload/unittests/OffloadAPI/memory/olMemFill.cpp
M offload/unittests/OffloadAPI/queue/olLaunchHostFunction.cpp
Log Message:
-----------
[offload][l0] Implement olLaunchHost function for level zero plugin (#204173)
Adds support to enqueue host tasks in Inorder queues for the L0 plugin.
Commit: 46b5bc7d786cf4cb889ae3489964f1809ab4689b
https://github.com/llvm/llvm-project/commit/46b5bc7d786cf4cb889ae3489964f1809ab4689b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Log Message:
-----------
[RISCV][P-ext] Fold (PSRL/PSRA (concat (trunc (PSRL X, C1)), (trunc (PSRL Y, C1))), C2). (#204659)
into (concat (trunc (PSRL/PSRA X, C1+C2)), (trunc (PSRL/PSRA Y,
C1+C2))). If C1 is equal to the number of bits discarded by the truncate.
We recently added this for for a single truncate. This expands it to
concatenated truncates.
Assisted-by: Claude
Commit: 6093c0e055d8ba3fbe0173627114cf4cad9f3900
https://github.com/llvm/llvm-project/commit/6093c0e055d8ba3fbe0173627114cf4cad9f3900
Author: Endre Fülöp <endre.fulop at sigmatechnology.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/test/Analysis/analyzer-enabled-checkers.c
M clang/test/Analysis/bstring.c
M clang/test/Analysis/bstring.cpp
M clang/test/Analysis/bstring_UninitRead.c
M clang/test/Analysis/cstring-uninitread-notes.c
M clang/test/Analysis/infeasible-crash.c
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
M clang/test/Analysis/wstring.c
Log Message:
-----------
[analyzer] Bring unix.cstring.UninitializedRead checker out of alpha (#196292)
There have been recent improvements (#186802) and fixes (#191061)
related to this checker. The reports are no longer noisy, as evaluated
on 14 OS projects.
---------
Co-authored-by: Donát Nagy <donat.nagy at ericsson.com>
Commit: def1355cf14cec28f71b8ca947b7723641c1580d
https://github.com/llvm/llvm-project/commit/def1355cf14cec28f71b8ca947b7723641c1580d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/AssumptionCache.h
M llvm/lib/Analysis/AssumptionCache.cpp
M llvm/lib/Transforms/Scalar/DropUnnecessaryAssumes.cpp
Log Message:
-----------
[AssumptionCache] Add replaceAssumption() to replace in-place. (#204432)
Add replaceAssumption and use it to replace assumptions when removing
bundles from assume in DropUnnecessaryAssumesPass, as suggested in PR
#203765.
Unfortunately I could not find any other candidates,that would not
require finding the WeakVH entry for assumes manually.
Compile-time impact is neutral/in the noise:
https://llvm-compile-time-tracker.com/compare.php?from=a2f4a1cabb083337ccb17c77cafb36d94c1ef52b&to=61a64fc62cbb38001894b75053f4add124869fe0&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/204432
Commit: 5471cdb0185c262e8e5fd5219f11095ccf7ddacb
https://github.com/llvm/llvm-project/commit/5471cdb0185c262e8e5fd5219f11095ccf7ddacb
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/riscv/hwprobe.inc
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/TargetParser/Host.cpp
Log Message:
-----------
[RISCV] Implement Zicfiss Extension Bitmask (#201699)
This implements the proposal here:
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/187
This was prepared with the assistance of AI.
Commit: a20244b9463263b7e098c4c938aa7277cba5f48a
https://github.com/llvm/llvm-project/commit/a20244b9463263b7e098c4c938aa7277cba5f48a
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-constant-ops.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-with-wide-ops-chained.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/narrow-interleave-groups-scalable-vf.ll
M llvm/test/Transforms/LoopVectorize/pr128062-interleaved-accesses-narrow-group.ll
Log Message:
-----------
[VPlan] Narrow interleave groups with distinct live-in operands. (#203778)
Extend narrowInterleaveGroups so bundles with live-ins can be narrowed
by using BuildVector for the operands.
This only applies to fixed VFs: for scalable VFs the number of original
iterations processed by the narrowed plan depends on vscale, so a fixed
per-field vector cannot be built.
Another missing piece for
https://github.com/llvm/llvm-project/issues/128062
On a large IR corpus based on C/C++ workloads (32k modules), this
triggers in ~38 modules.
PR: https://github.com/llvm/llvm-project/pull/203778
Commit: 8eb3b11a7cc6f87658eb82437b6e9e56fd694f89
https://github.com/llvm/llvm-project/commit/8eb3b11a7cc6f87658eb82437b6e9e56fd694f89
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td
M mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir
M mlir/test/Target/SPIRV/ocl-ops.mlir
Log Message:
-----------
[mlir][SPIR-V] Add CL expm1 and log1p ops (#203881)
Commit: 8d2165ee2db4b355ecc79c773684f2e7618cbf98
https://github.com/llvm/llvm-project/commit/8d2165ee2db4b355ecc79c773684f2e7618cbf98
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLOps.td
M mlir/test/Dialect/SPIRV/IR/gl-ops.mlir
M mlir/test/Target/SPIRV/gl-ops.mlir
Log Message:
-----------
[mlir][SPIR-V] Add GL Radians and Degrees ops (#203879)
Commit: d0981541cb55ad1ad53150b46a672f9e8149477f
https://github.com/llvm/llvm-project/commit/d0981541cb55ad1ad53150b46a672f9e8149477f
Author: Scott Linder <scott.linder at amd.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst
Log Message:
-----------
[AMDGPU][docs] Remove abandoned augementation-related changes (#204420)
These haven't been carried forward in the DWARF committee proposal, and
we don't expect them to standardized (at least in the form presented
here). Drop them to avoid confusion.
Change-Id: I60dd6ffb5df1bb63d132733466ecf3d697f79276
Commit: 729d7ab4810e7e9765880c93d268a84e79b73068
https://github.com/llvm/llvm-project/commit/729d7ab4810e7e9765880c93d268a84e79b73068
Author: Dan Brown <61992655+danbrown-amd at users.noreply.github.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaHLSL.cpp
Log Message:
-----------
Warns that the WaveSize attribute is unsupported for the SPIR-V target. (#196004)
Addresses #187188.
Commit: 7eef82d4ff37870e8ff2288f3f0f38b2a4bfb57e
https://github.com/llvm/llvm-project/commit/7eef82d4ff37870e8ff2288f3f0f38b2a4bfb57e
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Frontend/CompilerInvocation.h
M clang/include/clang/Frontend/FrontendOptions.h
M clang/include/clang/Options/Options.td
A clang/include/clang/ScalableStaticAnalysisFramework/Frontend/SSAFOptions.h
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
M clang/lib/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendAction.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendActionTest.cpp
Log Message:
-----------
[clang][ssaf][NFC] Move SSAF flags from FrontendOptions to a dedicated SSAFOptions (#204621)
This class will help keeping SSAF options apart from generic
FrontendOptions. It is inspired by AnalyzerOptions.
This way all of these SSAF (and future) options will be at a centralized place.
In preparation of rdar://179151023
Co-authored-by: Claude Opus 4.7 <noreply at anthropic.com>
Commit: a9e444adf3ca38add1d6f255a9f1802da1249dfa
https://github.com/llvm/llvm-project/commit/a9e444adf3ca38add1d6f255a9f1802da1249dfa
Author: Andrei Elovikov <andrei.elovikov at sifive.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Transforms/LoopVectorize/VPlan/scalarize-irregular-type-memops.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-before-after-all.ll
A llvm/test/Transforms/LoopVectorize/VPlan/widen_mem_idioms.ll
Log Message:
-----------
[VPlan] Split `makeMemOpWideningDecisions` into subpasses (#182593)
The idea is to have handling of strided memory operations (either from
https://github.com/llvm/llvm-project/pull/147297 or for VPlan-based
multiversioning for unit-strided accesses) done after some mandatory
processing has been performed (e.g., some types **must** be scalarized)
but before legacy CM's decision to widen (gather/scatter) or scalarize
has been committed.
And in longer term, we can uplift all other memory widening decision to
be done here directly at VPlan level. I expect this structure would also
be beneficial for that.
Changes behavior in the presence of
`-force-target-supports-gather-scatter-ops` option, but it's probably
right to scalarize irregular types regardless of that option.
---------
Co-authored-by: Luke Lau <luke at igalia.com>
Co-authored-by: Florian Hahn <flo at fhahn.com>
Commit: e65135507e5dce715aebb1e583bc792bc2d62bec
https://github.com/llvm/llvm-project/commit/e65135507e5dce715aebb1e583bc792bc2d62bec
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M clang/include/clang/Frontend/CompilerInstance.h
M clang/include/clang/Frontend/CompilerInvocation.h
M clang/include/clang/Frontend/FrontendOptions.h
M clang/include/clang/Options/Options.td
R clang/include/clang/ScalableStaticAnalysisFramework/Frontend/SSAFOptions.h
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
M clang/lib/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendAction.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendActionTest.cpp
Log Message:
-----------
Revert "[clang][ssaf][NFC] Move SSAF flags from FrontendOptions to a dedicated SSAFOptions" (#204686)
Reverts llvm/llvm-project#204621
Broke a Windows bot:
https://github.com/llvm/llvm-project/pull/204621#issuecomment-4746295964
https://lab.llvm.org/buildbot/#/builders/46/builds/36811
```
FAILED: ... project\clang\lib\Frontend\CompilerInvocation.cpp
tools\clang\include\clang/Options/Options.inc(9974): error C2065: 'SSAFOpts': undeclared identifier
tools\clang\include\clang/Options/Options.inc(9975): note: see reference to function template instantiation 'auto GenerateSSAFArgs::<lambda_fd4588547196dccacaf54a707a47a2b4>::operator ()<T>(const T &) const' being compiled
with
[
T=std::vector<std::string,std::allocator<std::string>>
]
```
Commit: 59d60d096048d37ff62b259eca71ac6cf1463845
https://github.com/llvm/llvm-project/commit/59d60d096048d37ff62b259eca71ac6cf1463845
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M lldb/test/API/commands/frame/diagnose/inheritance/main.cpp
M lldb/test/API/functionalities/plugins/python_os_plugin/TestPythonOSPlugin.py
M lldb/test/API/functionalities/plugins/python_os_plugin/main.c
M lldb/test/API/lang/cpp/extern_c/main.cpp
M lldb/test/API/lang/cpp/unique-types/main.cpp
M lldb/test/API/python_api/sbvalue_const_addrof/main.cpp
M lldb/test/API/python_api/sbvalue_unsigned_enum_bitfield_value/main.cpp
M lldb/test/API/python_api/target/main.c
M lldb/test/API/tools/lldb-dap/launch/main.c
M lldb/test/API/tools/lldb-dap/restart/main.c
Log Message:
-----------
[lldb][test] Avoid a 3-argument main in test inferiors (#204656)
On WebAssembly clang only wires a 0- or 2-argument main to the program
entry point: EmitMainVoidAlias emits the __main_void alias for a
no-argument main, and the 2-argument form is mangled to
__main_argc_argv.
A 3-argument main(argc, argv, envp) matches neither, so main is never
connected to the entry point and is left as an undefined-weak stub whose
body is `unreachable`. The affected inferiors trap with "Exception:
unreachable" before reaching main (even when run outside the debugger)
so any test using them fails on wasm.
Drop the unused third parameter, and where the environment is actually
iterated read it from `environ` instead. The inferiors now run on
WebAssembly and behave identically on other platforms.
Commit: 040a641988f6ed6f4fab250706ca2b620c1de2d8
https://github.com/llvm/llvm-project/commit/040a641988f6ed6f4fab250706ca2b620c1de2d8
Author: Gregory Roth <goyoroth at gmail.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M clang/test/CodeGenHLSL/builtins/ddx-coarse-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-coarse.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-fine-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-fine.hlsl
M clang/test/CodeGenHLSL/builtins/ddx.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-coarse-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-coarse.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-fine-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-fine.hlsl
M clang/test/CodeGenHLSL/builtins/ddy.hlsl
Log Message:
-----------
[HLSL] Correct SPIRV CHECKs in derivative tests (#176609)
The LABEL CHECKS intended to correspond to the CHECK-SPIRV directives
were misformed such that they had no effect. Given the similarity of the
output for SPIRV and DXIL, I've replaced them with common checks using
variables to match the parts that differ.
Commit: d0734df2c434c15815b2a9086102f3329dbd0a2a
https://github.com/llvm/llvm-project/commit/d0734df2c434c15815b2a9086102f3329dbd0a2a
Author: Ian Anderson <iana at apple.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M clang-tools-extra/clangd/test/background-index.test
M clang-tools-extra/clangd/test/include-cleaner-batch-fix.test
M clang-tools-extra/clangd/test/path-mappings.test
M clang-tools-extra/test/clang-tidy/checkers/misc/header-include-cycle.cpp
M clang-tools-extra/test/clang-tidy/checkers/portability/restrict-system-includes-transitive.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming-symlink.cpp
M clang-tools-extra/test/clang-tidy/infrastructure/clang-tidy-mac-libcxx.cpp
M clang-tools-extra/test/clang-tidy/infrastructure/remarks.cpp
M clang/test/APINotes/module-cache.m
M clang/test/ClangScanDeps/build-session-validation-relocated-modules.c
M clang/test/ClangScanDeps/header-search-pruning.cpp
M clang/test/ClangScanDeps/modules-context-hash.c
M clang/test/ClangScanDeps/modules-relocated-mm-macro.c
M clang/test/Driver/hip-runtime-libs-linux.hip
M clang/test/Driver/hip-version.hip
M clang/test/Driver/rocm-detect-lib-llvm.hip
M clang/test/Driver/rocm-detect.hip
M clang/test/InstallAPI/binary-attributes.test
M clang/test/InstallAPI/diagnostics-zippered.test
M clang/test/InstallAPI/directory-scanning-dylib.test
M clang/test/InstallAPI/directory-scanning-frameworks.test
M clang/test/InstallAPI/directory-scanning-subdirectories.test
M clang/test/InstallAPI/exclusive-passes-zippered.test
M clang/test/InstallAPI/extra-exclude-headers.test
M clang/test/InstallAPI/forwarded-search-paths.test
M clang/test/InstallAPI/umbrella-headers-unix.test
M clang/test/InstallAPI/umbrella-headers.test
M clang/test/Modules/add-remove-private.m
M clang/test/Modules/build-session-validation-relocated-modules.c
M clang/test/Modules/dependent-module-different-location.m
M clang/test/Modules/implicit-invalidate-common.c
M clang/test/Modules/include-relative.c
M clang/test/Modules/relative-import-path.c
M clang/test/Tooling/clang-check-mac-libcxx-abspath.cpp
M clang/test/Tooling/clang-check-mac-libcxx-fixed-compilation-db.cpp
M clang/test/Tooling/clang-check-mac-libcxx-relpath.cpp
M llvm/test/tools/llvm-cov/coverage-prefix-map.test
M llvm/test/tools/llvm-cov/directory_coverage.test
M llvm/test/tools/llvm-cov/multithreaded-report.test
M llvm/test/tools/llvm-cov/sources-specified.test
M llvm/utils/docker/build_docker_image.sh
M llvm/utils/lit/tests/filter-failed-delete.py
M llvm/utils/lit/tests/filter-failed-rerun.py
M llvm/utils/lit/tests/filter-failed.py
M llvm/utils/vscode/llvm/README.md
Log Message:
-----------
`cp -r` replaces symlinks, update to `cp -R` (#201463)
`cp -r` translates to `cp -RL` on at least FreeBSD and macOS. `-L`
replaces symlinks with flat directories which effectively breaks Apple
style bundles like frameworks. Switch to `-R` so that the symlinks don't
get broken.
Commit: 7f63067356cc142588248bbbce9577f58583cac0
https://github.com/llvm/llvm-project/commit/7f63067356cc142588248bbbce9577f58583cac0
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M lldb/include/lldb/Host/Editline.h
M lldb/source/Host/common/Editline.cpp
M lldb/unittests/Editline/EditlineTest.cpp
Log Message:
-----------
[lldb] Apply pending terminal resize before repainting the prompt (#203045)
Editline defers ApplyTerminalSizeChange() (el_resize plus refreshing the
cached terminal dimensions) to its read loop on the main thread, but
Refresh() and PrintAsync() repaint the prompt synchronously from the
resize notification on the signal thread, ahead of that apply. The
repaint therefore used the dimensions cached before the resize. Apply
any pending resize first via a shared helper. The output stream lock
already serializes these paths, and it is a no-op when nothing is
pending.
Editline keeps querying its own size (el_resize/EL_GETTC) rather than
using the dimensions the driver reports: el_resize must update libedit's
internal line-wrapping model regardless (libedit exposes no way to set
it), and editline's cursor arithmetic must use the same width libedit
wraps at. EL_GETTC reads back exactly that value, so the two cannot
diverge, while sourcing the width from the driver's separate ioctl
could.
Commit: 304c5a6587d4c23a920cc63e10c9337e285f41f9
https://github.com/llvm/llvm-project/commit/304c5a6587d4c23a920cc63e10c9337e285f41f9
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M offload/plugins-nextgen/common/src/RPC.cpp
Log Message:
-----------
[Offload] Flush pending RPC ports when tearing down a device (#204681)
The RPC client can push asynchronous work and then quit. These can be
lost if the kernel returns and is torn down before the RPC server gets
to run to check it. To handle this, we just manually flush the interface
once when we tear the device down. The interface is lock-free so this
should be safe even if the other thread is working through it as well.
Commit: d1c5cf2eac6b09c46adeb5593c11ecc0469b7bb6
https://github.com/llvm/llvm-project/commit/d1c5cf2eac6b09c46adeb5593c11ecc0469b7bb6
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M compiler-rt/test/fuzzer/fork.test
M compiler-rt/test/fuzzer/fork_corpus_groups.test
Log Message:
-----------
[Fuzzer] Bump rss_limit again (#204701)
These tests are still somewhat flaky, even after
3e11b3be3b86d4e72e73e610fb15fe431169f16e, so bump the limit again.
See
https://github.com/llvm/llvm-project/pull/203450#issuecomment-4737237866
for info on failures.
Commit: 15fa0c72562fbeb569c81352b55f3914f9e512d2
https://github.com/llvm/llvm-project/commit/15fa0c72562fbeb569c81352b55f3914f9e512d2
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M lldb/unittests/Host/HostTest.cpp
Log Message:
-----------
[lldb][test] Wait on the exit-status future in HostTest (#204704)
libc++ marks `std::future::get()` as` `[[nodiscard]]`. The cleanup
lambda only needs to block until the child is reaped, not read the
status. Use `wait()` to avoid the `-Wunused-result` warning.
Commit: 1fc592a0ebae43c222a01d90760373fcdb8e6da7
https://github.com/llvm/llvm-project/commit/1fc592a0ebae43c222a01d90760373fcdb8e6da7
Author: Tom Stellard <tstellar at redhat.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M .github/workflows/spirv-tests.yml
Log Message:
-----------
workflows/spirv-tests: Pin container image reference (#199479)
I pinned the image to the version that was used in the last successful
workflow run.
https://github.com/llvm/llvm-project/security/code-scanning/1807
https://docs.zizmor.sh/audits/#unpinned-images
Commit: a64928f267f3aeeb3571bfc7de92c432126d74e9
https://github.com/llvm/llvm-project/commit/a64928f267f3aeeb3571bfc7de92c432126d74e9
Author: Tony Varghese <tonypalampalliyil at gmail.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/PragmaKinds.h
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/Parse/ParsePragma.cpp
M clang/test/CXX/module/cpp.pre/module_decl.cpp
A clang/test/CodeGen/PowerPC/pragma-comment-copyright-modules.cpp
A clang/test/CodeGen/PowerPC/pragma-comment.c
M clang/test/CodeGen/lto-newpm-pipeline.c
A clang/test/Preprocessor/pragma-comment.c
A llvm/include/llvm/Transforms/Utils/LowerCommentStringPass.h
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/lib/Transforms/Utils/CMakeLists.txt
A llvm/lib/Transforms/Utils/LowerCommentStringPass.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
A llvm/test/Analysis/ModuleSummaryAnalysis/implicit-ref-edges.ll
M llvm/test/CodeGen/AArch64/print-pipeline-passes.ll
M llvm/test/CodeGen/Hexagon/print-pipeline-passes.ll
M llvm/test/Other/new-pm-O0-defaults.ll
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
A llvm/test/Transforms/LowerCommentString/lower-comment-string.ll
A llvm/test/Transforms/SCCP/implicit-ref-propagation.ll
Log Message:
-----------
[PowerPC][AIX] Support #pragma comment copyright for AIX (#178184)
This change supports **pragma comment copyright**.
Signature: `#pragma comment (copyright, "token_sequence")`
- The token_sequence is included in the generated executable and loaded
into memory when the program is run.
- copyright `comment` directive can appear only once in a translation
unit.
Implementation :
- Frontend (Clang): Parses `#pragma comment (copyright, "string")` for
AIX targets and emits :
- Emit weak_odr hidden hash-named global variables (e.g.,
`__loadtime_comment_str_<hash>`)
- Place strings in `__loadtime_comment` section and mark with
`!loadtime_comment` metadata
- Add to `llvm.compiler.used` to prevent early elimination
- Middle-end:
- `LowerCommentStringPass` Attaches `!implicit.ref` metadata from all
defined functions to the copyright string globals (that have
`!loadtime_comment` metadata).
- `ModuleSummaryAnalysis` (ThinLTO support) : `findImplicitRefEdges()`
collects globals referenced via `!implicit.ref` metadata and adds them
as explicit reference edges in the module summary. This ensures ThinLTO
import analysis treats copyright strings as live when their referencing
functions are live.
- `FunctionImport` (ThinLTO support):`protectImplicitRefGlobals()` finds
imported functions with `!implicit.ref` metadata pointing to
`available_externally` globals and adds those globals to
`llvm.compiler.used` to prevent DCE.
- `SCCPSolver` (optimization support):`propagateImplicitRefFromCall()`
preserves `!implicit.ref` metadata when calls are optimized away. When a
call is removed, propagates the callee's !implicit.ref metadata to the
caller and ensures copyright strings remain reachable even after
aggressive inlining/constant propagation.
- Backend: recognizes `!implicit.ref` metadata on functions and emits
`.ref` directives creating relocations from functions to copyright
strings. Linker keeps copyright strings as long as any referencing
function is kept.
Note:
- Emitting weak_odr, hidden, hash-named strings helps identical strings
from different TUs to be merged during import.
- Copyright strings are placed in a dedicated `__loadtime_comment`
section. In full LTO builds, multiple strings may be grouped into a
single csect, preventing individual linker GC. However, this groups
copyright strings "out of the way" from other data, which is beneficial
for memory layout. ThinLTO is not affected by this grouping.
- This change builds on top of [XCOFF associated
metadata](https://github.com/llvm/llvm-project/pull/159096)
---------
Co-authored-by: Tony Varghese <tony.varghese at ibm.com>
Co-authored-by: Hubert Tong <hubert.reinterpretcast at gmail.com>
Commit: 58f086d0cd58252b2b18fa95f96a566a06e96a36
https://github.com/llvm/llvm-project/commit/58f086d0cd58252b2b18fa95f96a566a06e96a36
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
A llvm/test/Transforms/RelLookupTableConverter/AArch64/no_relative_lookup_table.ll
M llvm/test/Transforms/RelLookupTableConverter/unnamed_addr.ll
Log Message:
-----------
Disable RelLookupTableConverter on AArch64 (#204669)
We're seeing miscompiles due to relative offsets overflowing 2GB.
AArch64 allows text + data to span up to 4GB in the small code model:
https://github.com/ARM-software/abi-aa/blob/main/sysvabi64/sysvabi64.rst#code-models.
We could also use 64-bit offsets, but I'll leave that for the futute.
Assisted-by: Gemini
Commit: 5a02a6d85aac93f5c47610300968a22b30892b8f
https://github.com/llvm/llvm-project/commit/5a02a6d85aac93f5c47610300968a22b30892b8f
Author: jofrn <jo7frn1 at gmail.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/test/CodeGen/X86/atomic-load-store.ll
Log Message:
-----------
[X86] Add aligned atomic vector load tests wider than 128 bits (NFC) (#204495)
These >128-bit loads are expanded to __atomic_load libcalls regardless
of alignment, since x86 caps atomic ops at 128 bits.
Store version: https://github.com/llvm/llvm-project/pull/202537
Commit: cc16c2cabacf3cfb904e94f2030b25eefb31c71f
https://github.com/llvm/llvm-project/commit/cc16c2cabacf3cfb904e94f2030b25eefb31c71f
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M clang/bindings/xml/comment-xml-schema.rng
A clang/test/Index/Inputs/CommentXML/invalid-concept-01.xml
A clang/test/Index/Inputs/CommentXML/valid-concept-01.xml
A clang/test/Index/Inputs/CommentXML/valid-concept-02.xml
M clang/test/Index/comment-xml-schema.c
Log Message:
-----------
[clang] Add concepts to XML comment schema, add tests (#202774)
Commit: 9fc458a1d95b9c3edf288e4ec2cd9dcd1fe0d895
https://github.com/llvm/llvm-project/commit/9fc458a1d95b9c3edf288e4ec2cd9dcd1fe0d895
Author: yonghong-song <yhs at fb.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/Target/BPF/BPFAsmPrinter.cpp
A llvm/test/CodeGen/BPF/jump_table_func_ptr_array.ll
Log Message:
-----------
[BPF] Fix erroneous removal of non-jump-table globals (#204594)
Jump tables are supported only for cpu v4. After lowering them into
.jumptables entries, BPFAsmPrinter::doFinalization() removes the private
constant arrays that backed the jump tables. But the below 'for' loop is
actually a no-op.
for (unsigned i = 1, e = CA->getNumOperands(); i != e; ++i) {
if (!dyn_cast<BlockAddress>(CA->getOperand(i)))
continue;
}
Targets.push_back(&Global);
With current implementation, 'Global' will be added to 'Targets' and
later in doFinalization(), 'Global' will be removed. But it is possible
in 'Global' there exists non BlockAddress which are used in later code.
This will cause the problem like:
error: Undefined temporary symbol .L__const.select_fn.fns
To fix the problem, For the above 'for' loop, only if all operands are
with BlockAddress, 'Global' can be pushed to 'Targets'.
The issue is discovered when running bpf selftest with -O1. The related
file is
tools/testing/selftests/bpf/progs/kprobe_multi_session.c
Before optimization, we have
@__const.session_check.kfuncs = private unnamed_addr constant [8 x ptr]
[ptr @bpf_fentry_test1, ptr @bpf_fentry_test2, ptr @bpf_fentry_test3,
ptr @bpf_fentry_test4, ptr @bpf_fentry_test5, ptr @bpf_fentry_test6,
ptr @bpf_fentry_test7, ptr @bpf_fentry_test8], align 8
With -O1, `@__const.session_check.kfuncs` is used in codegen like
...
$r2 = LD_imm64 @__const.session_check.kfuncs
...
which triggered the compilation failure.
With -O2, `@__const.session_check.kfuncs` is inlined in llvm
GlobalOptPass and each individual funciton `@bpf_fentry_test1` etc. is
directly used in IR, e.g.,
...
%9 = icmp eq i64 %8, ptrtoint (ptr @bpf_fentry_test1 to i64), !dbg !95
...
Commit: 4a1d8bbca2e4453ba680b6cf130e833338ac9490
https://github.com/llvm/llvm-project/commit/4a1d8bbca2e4453ba680b6cf130e833338ac9490
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
Log Message:
-----------
[AMDGPU][NFC]: Pre-commit load.async.to.lds.ll test (#204695)
Commit: 4da60b8a877d2ca4c8d57ed996da2bd3be5807e3
https://github.com/llvm/llvm-project/commit/4da60b8a877d2ca4c8d57ed996da2bd3be5807e3
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Utils/LowerCommentStringPass.cpp
Log Message:
-----------
[NFC] LowerCommentStringPass: remove unused #include (#204719)
This pass was added in a64928f267f3aeeb3571bfc7de92c432126d74e9 but does
not actually use PassBuilder
Commit: 17308a961710f91e073923405712bacc981c936a
https://github.com/llvm/llvm-project/commit/17308a961710f91e073923405712bacc981c936a
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M orc-rt/lib/executor/Session.cpp
M orc-rt/unittests/SessionTest.cpp
Log Message:
-----------
[orc-rt] Fix assertion, add fail-to-connect unit test. (#204720)
If a ControllerAccess object's connect method calls notifyDisconnected
then by the time we return to Connect we may have completed the detach,
in which case TargetState will be None, and CurrentState will be >=
Detached. This case was not covered by the assert after the return from
connect, leading to assertions when connect failed.
This commit relaxes the assertion to include the case above, and adds a
unit test to cover it.
Commit: 54ce8fc400f5e576e86437914829b1cba321e8ad
https://github.com/llvm/llvm-project/commit/54ce8fc400f5e576e86437914829b1cba321e8ad
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
Log Message:
-----------
[AMDGPU][NFC] Pre-commit test for fabs/fneg fold into fptrunc source modifiers (#204666)
Commit: 79349e509ab569636647829945e20a6f244d6c36
https://github.com/llvm/llvm-project/commit/79349e509ab569636647829945e20a6f244d6c36
Author: Kevin Sala Penades <salapenades1 at llnl.gov>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M offload/libomptarget/device.cpp
M offload/libomptarget/omptarget.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/include/RecordReplay.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/common/src/RecordReplay.cpp
M openmp/docs/design/Runtimes.rst
Log Message:
-----------
[offload] Improve report printing for kernel recording (#204505)
This commit extends the record reporting mechanism:
- `LIBOMPTARGET_RECORD_REPORT_FILENAME` enables the reporting mechanism
and allows specifying the name of the output file.
- The report of recorded kernels are ordered in recording order. This is
really useful for tests that need to record and replay more than one
kernel.
Commit: 24d6172f0c00d62287c211c9f0b84e4b6f6063d9
https://github.com/llvm/llvm-project/commit/24d6172f0c00d62287c211c9f0b84e4b6f6063d9
Author: Fangrui Song <i at maskray.me>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCStreamer.cpp
Log Message:
-----------
[MC] Remove unused FileNo parameter from MCStreamer::checkCVLocSection. NFC (#204729)
Commit: ed287c064db043a94b5470ebf36524153aeaf33f
https://github.com/llvm/llvm-project/commit/ed287c064db043a94b5470ebf36524153aeaf33f
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
A clang/test/CodeGenHLSL/resources/ConstantBufferT.hlsl
Log Message:
-----------
[HLSL][NFC] Add codegen test for ConstantBuffer<T> element access and initialization (#204507)
Adding tests coverage for `ConstantBuffer<T>` element access and
initialization.
Related to llvm/wg-hlsl#302 and llvm/llvm-project#195153
Commit: 21622397c16f65d00361cd883c769189b06df13c
https://github.com/llvm/llvm-project/commit/21622397c16f65d00361cd883c769189b06df13c
Author: Sairudra More <sairudra60 at gmail.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/openmp-task-in-reduction.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[mlir][OpenMP] Translate explicit task in_reduction (#202611)
Lower `in_reduction` on explicit `omp.task` operations to LLVM IR.
Inside the outlined task body, obtain the executing thread's `gtid` and call `__kmpc_task_reduction_get_th_data` with a null descriptor and the original reduction variable address. This lets the runtime find the enclosing taskgroup reduction registration and return the per-task private reduction storage.
The `in_reduction` block arguments are remapped to the returned private storage, so updates inside the explicit task body target the task-private reduction copy instead of the original shared variable.
Unsupported cases remain guarded, including byref `in_reduction` and richer `declare_reduction` forms such as two-argument initializers, cleanup regions, and missing combiners.
Commit: 1e0899794dd432c6c3c7bbba6940e8640e6a201c
https://github.com/llvm/llvm-project/commit/1e0899794dd432c6c3c7bbba6940e8640e6a201c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[DAG] visitEXTRACT_SUBVECTOR - Fold EXTRACT_SUBVECTOR(EXTRACT_SUBVECTOR(X,C1),C0) with nonzero indices (#204533)
Removed equivalent fold from x86 and added generic DAG fold to replace
it - net zero test changes
Refactored version of #200935
Commit: 4b2a02d47e31da4764aa6e204e6c502ccc69e201
https://github.com/llvm/llvm-project/commit/4b2a02d47e31da4764aa6e204e6c502ccc69e201
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/lib/CodeGen/TargetBuiltins/X86.cpp
M clang/test/CodeGen/X86/bmi2-builtins.c
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
M llvm/lib/Target/X86/X86InstrFragments.td
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/CodeGen/X86/bmi2.ll
M llvm/test/Instrumentation/MemorySanitizer/bmi.ll
M llvm/test/Instrumentation/MemorySanitizer/pdep.ll
M llvm/test/Instrumentation/MemorySanitizer/pext.ll
M llvm/test/Transforms/InstCombine/pdep.ll
M llvm/test/Transforms/InstCombine/pext.ll
Log Message:
-----------
[X86] Replace X86 specific PDEP/PEXT handling with generic intrinsics (#204144)
* Remove X86ISD::PDEP/PEXT and use ISD::PDEP/PEXT instead
* AutoUpgrade x86 pdep/pext intrinsics to llvm.pdep/pext generics
* Move X86 DAG knownbits/demandedbits handling to generic (unchanged)
* Move X86 InstCombine folds to generic (unchanged)
* Add memory sanitizer handling for generic pdep/pext intrinsics
* Updated clang builtins to emit generics
Fixes #204537
Commit: f0134cc7a5a56b53dfbe2887cd759806845c8797
https://github.com/llvm/llvm-project/commit/f0134cc7a5a56b53dfbe2887cd759806845c8797
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/lib/Basic/TargetID.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/test/Driver/invalid-target-id.cl
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
A llvm/test/CodeGen/AMDGPU/target-id-xnack-always-on.ll
Log Message:
-----------
AMDGPU: Add subtarget feature for controllable xnack modes (#204523)
This replaces the previously removed xnack-any-only feature,
with the inversion xnack-on-off-modes. All pre-gfx12.5 xnack
targets support the controllable mode. Ignore explicitly
set xnack settings the same way as is done for xnack requests
on other unsupported targets.
Commit: b65d5100d712e49abe85b337b03663ec1dcbd266
https://github.com/llvm/llvm-project/commit/b65d5100d712e49abe85b337b03663ec1dcbd266
Author: Kevin Sala Penades <salapenades1 at llnl.gov>
Date: 2026-06-18 (Thu, 18 Jun 2026)
Changed paths:
M offload/libomptarget/omptarget.cpp
M offload/plugins-nextgen/common/src/RecordReplay.cpp
A offload/test/tools/omp-kernel-replay/record-replay-empty-memory.cpp
M offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp
Log Message:
-----------
[offload][OpenMP] Fix record replay when no memory is used (#201771)
Progams that do not use any memory (e.g., no mappings) were failing
because we were trying to execute zero size transfers. This commit adds
handling for this case.
Commit: 9c50867e78707c7ad9b46b6c2c71ef45ac124bbb
https://github.com/llvm/llvm-project/commit/9c50867e78707c7ad9b46b6c2c71ef45ac124bbb
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/examples/OrcV2Examples/CMakeLists.txt
A llvm/examples/OrcV2Examples/LLJITWithSymbolAliases/CMakeLists.txt
A llvm/examples/OrcV2Examples/LLJITWithSymbolAliases/LLJITWithSymbolAliases.cpp
Log Message:
-----------
[ORC][examples] Add a new example showing basic symbolAliases usage. (#204733)
LLJITWithSymbolAliases shows how the symbolAliases function can be used
to introduce aliases for both JIT'd and precompiled symbols.
Commit: 0ad5d54be53f34f71e25575964785670720a5f4c
https://github.com/llvm/llvm-project/commit/0ad5d54be53f34f71e25575964785670720a5f4c
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
M llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.h
M llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp
Log Message:
-----------
[GlobalISel] TableGen memcpy-like prelegalizer combines (#203235)
This removes the corresponding handwritten C++ combine handling from the
AArch64 prelegalizer combiners.
Assisted-by: codex
Commit: d87e513d454714d08b6deeb055bf6f6cc959b450
https://github.com/llvm/llvm-project/commit/d87e513d454714d08b6deeb055bf6f6cc959b450
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/test/Sema/enable_if.c
M clang/test/SemaCXX/enable_if.cpp
Log Message:
-----------
[clang][test] Use #marker in enable_if tests (#204624)
I just wasted way too long trying to figure out why my newly added RUN
lines were randomly broken or not.
Stop using absolute line numbers.
Commit: 7d122c329944a6be4ed93929c99f5e8fc75b6892
https://github.com/llvm/llvm-project/commit/7d122c329944a6be4ed93929c99f5e8fc75b6892
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/test/Sema/LifetimeSafety/dangling-global.cpp
M clang/test/Sema/LifetimeSafety/safety-c.c
Log Message:
-----------
[LifetimeSafety] Propagate loans through pointer inc/dec and compound assignment (#204477)
Commit: 6352a584c409a4ad44804f06e06260be587866d3
https://github.com/llvm/llvm-project/commit/6352a584c409a4ad44804f06e06260be587866d3
Author: Matthias Springer <me at m-sp.org>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M mlir/include/mlir/IR/BuiltinAttributes.td
Log Message:
-----------
[mlir][IR] Fix typo in code example of DenseTypedElementsAttr (#204739)
There was a typo in the type-first syntax code example.
Commit: 3b1a922a6d02705ef30b1527e34af7b6208dc02f
https://github.com/llvm/llvm-project/commit/3b1a922a6d02705ef30b1527e34af7b6208dc02f
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/X86/pr36524.ll
M llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-with-uniform-ops.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads.ll
M llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization-2.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/metadata.ll
M llvm/test/Transforms/LoopVectorize/pr47343-expander-lcssa-after-cfg-update.ll
M llvm/test/Transforms/LoopVectorize/pr59319-loop-access-info-invalidation.ll
M llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
M llvm/test/Transforms/LoopVectorize/single-scalar-cast-minbw.ll
M llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll
Log Message:
-----------
[VPlan] Extend licm to sink replicate stores (#191026)
Follow up on hoisting replicate loads in VPlan-licm to also sink
replicate stores.
Commit: f8bd135b6faef0675f1b8cb088373337d0439bb8
https://github.com/llvm/llvm-project/commit/f8bd135b6faef0675f1b8cb088373337d0439bb8
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/utils/lit/lit/TestRunner.py
Log Message:
-----------
[lit] Make RecursionError less likely in internal shell (#204573)
The lit internal shell chains together the contents of multiple RUN:
lines by connecting them with implicit && nodes, forming a binary tree
structure which is then executed recursively by `_executeShCommand`.
However the tree structure is constructed in a very simple way which
makes it effectively just a linked list, so `_executeShCommand` must
recurse to a depth equal to the number of commands.
If a test file contains more than 1000 RUN: lines (e.g. running the
clang driver only, with lots of different options), then this causes a
RecursionError exception, which did not happen using the external shell.
Failures of this kind can be avoided by instead connecting the commands
together in a _balanced_ binary tree, which has equivalent behaviour,
since the && shell operator is associative.
Commit: 9361b3d9570596231ffa2b9a1a2ae4ee5fe7eb9d
https://github.com/llvm/llvm-project/commit/9361b3d9570596231ffa2b9a1a2ae4ee5fe7eb9d
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/widen-call-op-scalar-vector.ll
Log Message:
-----------
[LV] Add test for WidenCall with mixed scalar-vector operands (#203092)
Commit: b9587a78a090fa53bed1dc1b478502e3038a0028
https://github.com/llvm/llvm-project/commit/b9587a78a090fa53bed1dc1b478502e3038a0028
Author: Jiang Ning <jiangninghx at foxmail.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M lld/ELF/Arch/AArch64.cpp
M lld/test/ELF/aarch64-tls-le.s
M lld/test/ELF/aarch64-tlsld-ldst.s
Log Message:
-----------
[ELF][AArch64] Relax zero TLSLE add to nop (#204286)
Optimize AArch64 local-exec TLS relocation handling by replacing a
self-add R_AARCH64_TLSLE_ADD_TPREL_HI12 instruction with nop when the
high 12 bits are zero.
The optimization is disabled by --no-relax and avoids non-equivalent
forms such as non-self-adds and 32-bit destination registers.
Commit: b496d0623824060af20726f89bbf8fe662dd49e4
https://github.com/llvm/llvm-project/commit/b496d0623824060af20726f89bbf8fe662dd49e4
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/lib/Analysis/LifetimeSafety/Origins.cpp
M clang/test/Sema/LifetimeSafety/safety-c.c
M clang/test/Sema/LifetimeSafety/safety.cpp
Log Message:
-----------
[LifetimeSafety] Model bit_cast and atomic casts in the fact generator (#204591)
VisitCastExpr dropped several borrow-carrying cast kinds into its
default case. Propagate the borrow through
`__builtin_bit_cast`/`std::bit_cast` of a pointer and through
wrapping/unwrapping `_Atomic(T*)`, so a stack address laundered through
either is caught (matching reinterpret_cast). hasOrigins and
buildListForType now see through AtomicType, which is transparent for
lifetimes.
Assisted-by: Claude Opus 4.8
Co-authored-by: Gabor Horvath <gaborh at apple.com>
Commit: c327ab359a959de2e4241a5fcda409958f2c0d11
https://github.com/llvm/llvm-project/commit/c327ab359a959de2e4241a5fcda409958f2c0d11
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
A llvm/test/CodeGen/AArch64/windows-elf-frame-record-pairing.ll
Log Message:
-----------
[AArch64] Fix Windows target detection in FrameLowering (#204347)
In #156467, we switched to using `getMCAsmInfo()->usesWindowsCFI()` to
recognize "Windows". This does not include Windows triples with ELF
binary formats.
So, for aarch64-pc-windows-msvc-elf we would use the Windows callee-save
list in `AArch64RegisterInfo::getCalleeSavedRegs()`, but FrameLowering
would handle this like Linux, and fail to invalidate the (x29, x28)
pairing.
This patch switches back to using AArch64Subtarget::isTargetWindows(),
which aligns with getCalleeSavedRegs().
Note: We were using `usesWindowsCFI()` to include UEFI targets, however,
there does not seem to be tests/support for UEFI triples on AArch64
(basic examples that compile for x86 fail: https://godbolt.org/z/dPWdTrEG7).
So, this has been moved to a TODO.
Fixes #204060
Commit: 06137a53cc96643f17f34c6affa8838c5c86e2cb
https://github.com/llvm/llvm-project/commit/06137a53cc96643f17f34c6affa8838c5c86e2cb
Author: Fabrice de Gans <Steelskin at users.noreply.github.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/CAS/ActionCache.h
M llvm/include/llvm/CAS/MappedFileRegionArena.h
M llvm/include/llvm/CAS/OnDiskDataAllocator.h
M llvm/include/llvm/CAS/OnDiskGraphDB.h
M llvm/include/llvm/CAS/OnDiskKeyValueDB.h
M llvm/include/llvm/CAS/OnDiskTrieRawHashMap.h
M llvm/include/llvm/CAS/UnifiedOnDiskCache.h
M llvm/include/llvm/CGData/StableFunctionMap.h
M llvm/include/llvm/CodeGen/MIR2Vec.h
M llvm/include/llvm/IR/BasicBlock.h
M llvm/include/llvm/Option/ArgList.h
M llvm/include/llvm/SandboxIR/Argument.h
M llvm/include/llvm/SandboxIR/BasicBlock.h
M llvm/include/llvm/SandboxIR/Function.h
M llvm/include/llvm/SandboxIR/Instruction.h
M llvm/include/llvm/SandboxIR/Pass.h
M llvm/include/llvm/SandboxIR/Region.h
M llvm/include/llvm/SandboxIR/Tracker.h
M llvm/include/llvm/SandboxIR/Use.h
M llvm/include/llvm/Support/Compiler.h
M llvm/include/llvm/Support/GlobPattern.h
M llvm/include/llvm/Support/LSP/Logging.h
M llvm/include/llvm/Support/LSP/Protocol.h
M llvm/include/llvm/Support/LSP/Transport.h
M llvm/include/llvm/Support/VirtualOutputConfig.h
M llvm/include/llvm/Transforms/Utils/DebugSSAUpdater.h
M llvm/include/llvm/Transforms/Utils/SSAUpdaterBulk.h
Log Message:
-----------
[llvm] Remove LLVM_ABI_FOR_TEST in public headers (#204627)
These annotations were mistakenly set up as LLVM_ABI_FOR_TEST. Since
these are public headers, they should be using LLVM_ABI.
The effort to build LLVM as a dylib is tracked in #109483.
Commit: 47b29c2eadbd9d7ddfb26bd6104a0a1f9e4a13a1
https://github.com/llvm/llvm-project/commit/47b29c2eadbd9d7ddfb26bd6104a0a1f9e4a13a1
Author: Faijul Amin <md.faijul.amin at intel.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
A llvm/test/CodeGen/SPIRV/instructions/phi-large-vector-shader.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-large-vector.ll
Log Message:
-----------
[SPIR-V] Legalize G_PHI of oversized vectors via fewer-elements (#203993)
`G_PHI` on vectors wider than the SPIR-V max vector size previously
failed legalization. This PR adds a `fewerElementsIf` rule that splits
them down to `MaxVectorSize`, matching how other vector ops are handled
in `SPIRVLegalizerInfo.cpp`.
Added the following test
`llvm/test/CodeGen/SPIRV/instructions/phi-large-vector.ll` covering
spirv32 and spirv64.
Commit: 40cbc98bb17718eef5e0b1f47e3b58900aac354a
https://github.com/llvm/llvm-project/commit/40cbc98bb17718eef5e0b1f47e3b58900aac354a
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/AArch64/sve-masked-gather-64b-scaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-64b-unscaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter-64b-scaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter-64b-unscaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
Log Message:
-----------
[AArch64][SDAG] Legalise nxv1 gather/scatter nodes (#204620)
This updates WidenVecRes_MGATHER and WidenVecOp_MSCATTER to support
scalable vector types.
Commit: a5e83b9a9b16d770792f7cd02ebe30bcfd95cbfe
https://github.com/llvm/llvm-project/commit/a5e83b9a9b16d770792f7cd02ebe30bcfd95cbfe
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/include/clang/Basic/arm_neon.td
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
M clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
M clang/test/CodeGen/AArch64/bf16-ldst-intrinsics.c
M clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
M clang/test/CodeGen/AArch64/neon-luti.c
M clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
M clang/test/Sema/aarch64-neon-immediate-ranges/luti.c
M clang/test/Sema/aarch64-neon-target.c
M clang/test/Sema/aarch64-neon-without-target-feature.cpp
M clang/test/Sema/arm-neon-target.c
Log Message:
-----------
[Clang][NEON ACLE] Remove +bf16 requirement from opaque bfloat builtins. (#204201)
Builtins that only care about the size of the element type but not its
format (e.g loads, stores and shuffles) do not require any special
instructions to code generate beyond those already available to +neon.
Fixes https://github.com/llvm/llvm-project/issues/203159
Commit: fdf3d44c9004eaf2ed112ced60b3f0e384724281
https://github.com/llvm/llvm-project/commit/fdf3d44c9004eaf2ed112ced60b3f0e384724281
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/test/Transforms/InstCombine/pdep.ll
M llvm/test/Transforms/InstCombine/pext.ll
Log Message:
-----------
[InstCombine] Add tests showing failure to fold pdep(0,x) and pext(0,x) to 0 (#204783)
As noted on #204144
Commit: e6daa6810e5ed49104a0f409d51e953905c9752e
https://github.com/llvm/llvm-project/commit/e6daa6810e5ed49104a0f409d51e953905c9752e
Author: Garvit Gupta <garvgupt at qti.qualcomm.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M compiler-rt/test/builtins/Unit/lit.cfg.py
Log Message:
-----------
Revert "Revert "[Compiler-rt][test] Fix circular link dependency between builtins and libc"" (#204728)
Reverts llvm/llvm-project#203152
Commit: 500d1f848c9a5488b7ff5ab2aad09041935ae7ff
https://github.com/llvm/llvm-project/commit/500d1f848c9a5488b7ff5ab2aad09041935ae7ff
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-void-call-aggregate-arg.ll
Log Message:
-----------
[SPIR-V] Fix crash on void indirect call with aggregate argument (#204388)
removeAggregateTypesFromCalls named the call to key the type-restoration
metadata, which asserts for void-returning calls. Key the metadata via
instruction metadata on the call instead, which works for void results.
Commit: b90ec9c2747f336991f392dc843ecff1ca2faed7
https://github.com/llvm/llvm-project/commit/b90ec9c2747f336991f392dc843ecff1ca2faed7
Author: Ömer Sinan Ağacan <omeragacan at gmail.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/StackColoring.cpp
Log Message:
-----------
[StackColoring] Remove unused BB numbering state (#204414)
Commit: f6fd6ea3c1b59728c3c8f3443ef9a02d367ec8e0
https://github.com/llvm/llvm-project/commit/f6fd6ea3c1b59728c3c8f3443ef9a02d367ec8e0
Author: bogdan-petkovic <bpetkovi at amd.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M mlir/lib/ExecutionEngine/CMakeLists.txt
Log Message:
-----------
[mlir][ExecutionEngine] Fix dead -Wno-c++98-compat-extra-semi guard (#204524)
`check_cxx_compiler_flag` stores its result in
`CXX_SUPPORTS_NO_CXX98_COMPAT_EXTRA_SEMI_FLAG`, but the guarding `if()`
checked `CXX_SUPPORTS_CXX98_COMPAT_EXTRA_SEMI_FLAG` (without `_NO_`),
which is never set. The condition was therefore always false and the
`-Wno-c++98-compat-extra-semi` suppression for `mlir_rocm_runtime` was
never applied.
The sibling flag checks in the same block (`-Wno-return-type-c-linkage`,
`-Wno-nested-anon-types`, `-Wno-gnu-anonymous-struct`) already use
matching variable names, so this aligns the typo'd guard with the
established pattern.
No test is included, this is a build-system-only (CMake) change to a
warning-suppression guard and is not unit-testable.
Signed-off-by: bogdan-petkovic <bpetkovi at amd.com>
Commit: 3cc94639047973169a9874139b8d95e17cdba50b
https://github.com/llvm/llvm-project/commit/3cc94639047973169a9874139b8d95e17cdba50b
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Analysis/Delinearization.cpp
A llvm/test/Analysis/Delinearization/inconsistent-types.ll
Log Message:
-----------
[Delinearization] Narrow the scope of the term collection (#204145)
In parametric delinearization, it collects subexpressions whose SCEV
type is `SCEVUnknown` and uses them as candidates for the array
dimensions. When traversing these subexpressions, it may follow any kind
of expression. For example, if it follows a `sext` expression, this can
lead to type inconsistencies among the collected terms.
This patch fixes this issue by preventing traversal into subexpressions
other than `SCEVAddExpr` or `SCEVAddRecExpr`.
Note: I tried to minimize the test case, but this seems to be as far as
it can go.
Fix #204066.
Commit: 60a2d437bd040a494cfe87fa8f44ebad18db2196
https://github.com/llvm/llvm-project/commit/60a2d437bd040a494cfe87fa8f44ebad18db2196
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/CMakeLists.txt
A llvm/lib/Target/AArch64/SVEShuffleOpts.cpp
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
A llvm/test/CodeGen/AArch64/sve-tbl-folding-new-pm.ll
A llvm/test/CodeGen/AArch64/sve-tbl-folding-opts.ll
Log Message:
-----------
[AArch64] Add SVE shuffle optimization pass (#193951)
Add a pass to perform VLA shuffle optimizations for SVE.
First up is using tbl to replace deinterleave4+uunpk+zext/uitofp
by generating shuffle masks with index, exploiting the fact that
out-of-range indices in the mask produce zeroes in the result
vector. That way, we can easily zero-extend smaller elements
by using the destination type when generating the mask, and
having one index in range with several out-of-range for each
destination element.
Commit: 80c80e6d04515acf7dac8c256a1a3b3dc14cfa4d
https://github.com/llvm/llvm-project/commit/80c80e6d04515acf7dac8c256a1a3b3dc14cfa4d
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/cxx20.cpp
Log Message:
-----------
[clang][bytecode] Check const writes more thorougly (#204529)
We used to only have a list of blocks under construction, but now we
have a list of pointers, which gives us more information.
Use this new list to diagnose a case we couldn't previously diagnose.
The test case is from `constant-expression-cxx14.cpp` and shows that a
write to a const member is invalid, even if the parent object is being
constructed right now.
Commit: a6fe3c7422db83346c336346e0b7a56ff084b17f
https://github.com/llvm/llvm-project/commit/a6fe3c7422db83346c336346e0b7a56ff084b17f
Author: Xavier Roche <xavier.roche at algolia.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M libcxx/test/libcxx/concepts/concepts.arithmetic/__libcpp_signed_integer.compile.pass.cpp
M libcxx/test/libcxx/concepts/concepts.arithmetic/__libcpp_unsigned_integer.compile.pass.cpp
M libcxx/test/std/containers/views/mdspan/extents/bitint.pass.cpp
M libcxx/test/std/language.support/support.limits/limits/numeric.limits.members/digits.pass.cpp
M libcxx/test/std/language.support/support.limits/limits/numeric.limits.members/digits10.pass.cpp
M libcxx/test/std/language.support/support.limits/limits/numeric.limits.members/max.pass.cpp
M libcxx/test/std/language.support/support.limits/limits/numeric.limits.members/min.pass.cpp
M libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.pass.cpp
M libcxx/test/std/numerics/bit/bit.pow.two/bit_floor.pass.cpp
M libcxx/test/std/numerics/bit/bit.pow.two/bit_width.pass.cpp
M libcxx/test/std/numerics/bit/bit.pow.two/has_single_bit.pass.cpp
M libcxx/test/std/numerics/bit/bitops.count/countl_one.pass.cpp
M libcxx/test/std/numerics/bit/bitops.count/countl_zero.pass.cpp
M libcxx/test/std/numerics/bit/bitops.count/countr_one.pass.cpp
M libcxx/test/std/numerics/bit/bitops.count/countr_zero.pass.cpp
M libcxx/test/std/numerics/bit/bitops.count/popcount.pass.cpp
M libcxx/test/std/numerics/bit/bitops.rot/rotl.pass.cpp
M libcxx/test/std/numerics/bit/bitops.rot/rotr.pass.cpp
M libcxx/test/std/numerics/bit/byteswap.pass.cpp
M libcxx/test/std/numerics/bit/byteswap.verify.cpp
M libcxx/test/std/numerics/numeric.ops/numeric.ops.sat/saturating.bitint.pass.cpp
R libcxx/test/std/utilities/format/format.arguments/format.arg.store/make_format_args.bitint.verify.cpp
M libcxx/test/std/utilities/utility/utility.intcmp/intcmp.bitint.pass.cpp
M libcxx/test/support/test_macros.h
Log Message:
-----------
[libc++][test] Migrate _BitInt probe to __BITINT_MAXWIDTH__ and fix latent test bugs (#203876)
`libcxx` tests gate `_BitInt` blocks on `TEST_HAS_EXTENSION(bit_int)`,
which is not a recognized Clang extension and returns 0 in every
language mode. The blocks have been compiling as dead code, hiding
latent bugs across 23 files.
Migrate to a `TEST_HAS_BITINT` helper backed by the standard
`__BITINT_MAXWIDTH__`. The latent bugs the activation surfaces are fixed
in the same commit:
- overflow-safe `min`;
- post-P4052R0 saturating-arithmetic renames plus a
`clang-21`/`apple-clang-21` skip for `saturating.bitint.pass.cpp` (Clang
21 asserts in constexpr eval on non-byte-aligned `_BitInt`);
- an `intcmp` syntax fix;
- `byteswap.verify` directive tightening;
- a missing `<climits>` include in `byteswap.pass` (only visible under
`-fmodules`);
- C++03-compatible `static_assert` form in `digits10`; gating
`digits`/`digits10` `_BitInt` blocks behind
`!_LIBCPP_USE_FROZEN_CXX03_HEADERS` since the fix from #193002 was not
backported to the frozen snapshot; and
- `make_format_args` reduced to a placeholder pending a SFINAE-friendly
rejection path.
Discussion:
https://discourse.llvm.org/t/implementing-p3666r4-bit-precise-integers-in-libc/91070
Assisted-by: Claude (Anthropic)
---------
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
Commit: eb7ce80944ee06b09c0bd6474254a155461dddd9
https://github.com/llvm/llvm-project/commit/eb7ce80944ee06b09c0bd6474254a155461dddd9
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Log Message:
-----------
CodeGenPassBuilder: Use cl::boolOrDefault directly in CGPassBuilderOption (#204196)
Current implementation that uses std::optional<bool> captures cl::BOU_FALSE,
for example -global-isel=0, as true. Explictly setting option to 0 should be
false, forced option not set.
This could be fixed but I find it cleaner to use boolOrDefault directly and
use same logic as in TargetPassConfig.
Options EnableIPRA and EnableGlobalISelAbort are left as optional since for
them it is explicitly checked if they are set using getNumOccurrences.
boolOrDefault has encoded unset option.
Commit: 54a7896acfb97d7935e085eebbc18fd5e694f67d
https://github.com/llvm/llvm-project/commit/54a7896acfb97d7935e085eebbc18fd5e694f67d
Author: mkovacevic99 <mkovacevic at baylibre.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/ExecutionEngine/JITLink/COFF_x86_64.cpp
A llvm/test/ExecutionEngine/JITLink/x86-64/COFF_dllimport_iat.s
Log Message:
-----------
[JITLink][COFF] Synthesize __imp_ IAT entries (#203906)
Adds a default COFF/x86_64 JITLink pass that synthesizes `__imp_` Import
Address Table (IAT) entries for dllimport references. This allows COFF
objects using dllimport to be JIT-linked without a hand-built import library or
a special generator.
On COFF, `__declspec(dllimport)` codegen emits indirect accesses through a named
`__imp_X` symbol (`callq *__imp_bar(%rip)`; `movq __imp_g(%rip)` for data),
with `__imp_X` left undefined. JITLink had no handling for this. The new pass —
the COFF counterpart of the ELF/Mach-O GOT builder — defines each undefined
external `__imp_X` over an 8-byte slot holding the address of `X`, and leaves `X`
as an ordinary external to be resolved normally (import library, dynamic-library
search generator, etc.). Both the call and data-access forms then resolve
indirectly through the slot.
Rather than the `GOTTableManager` pattern (anonymous entry + edge redirection),
the pass defines the *named* `__imp_X` symbol over the slot. ELF GOT references
are nameless edge kinds, so that builder must create an anonymous entry and
redirect edges; COFF references `__imp_X` by name, so defining it is simpler —
no edge rewriting, no orphaned-external cleanup, sharing is automatic,
and the call/data-access forms are handled identically.
x86_64 only (runs in the COFF/x86_64 backend's default pass pipeline). New lit
test `COFF_dllimport_iat.s`: assembles an object referencing `__imp_bar` (call)
and `__imp_foo` (data load), supplies `foo`/`bar` via `-abs`, links with
`-noexec`, and uses `jitlink-check` to verify each `__imp_` slot holds the
target's address and that the references resolve through the slot.
Partly implements github issue:
https://github.com/llvm/llvm-project/issues/190122
In the comment section of the github issue there is this comment
https://github.com/llvm/llvm-project/issues/190122#issuecomment-4617328036
This PR implements point 2 Synthesis IAT entries.
Commit: 12ee71c377db385c4af0cfe92488406b9a8fa13c
https://github.com/llvm/llvm-project/commit/12ee71c377db385c4af0cfe92488406b9a8fa13c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/test/Driver/lto.c
Log Message:
-----------
[Clang] Respect `-fno-slp-vectorize` for the LTO pipeline (#201585)
Summary:
This is related to reported regressions in the GROMACS suite when
offloading to AMDGCN devices through the RDC / LTO interface. The
application intentionally passes `-fno-slp-vectorize` to disable that
pass, but there's currently no way to do this through the LTO pipline.
This PR causes the driver to emit `plugin-opt=` for the `-mllvm` option.
That means the pass is still enabled but it should be a no-op now.
Commit: 0390898335f9f32ea71ff288a5b4085cecc10391
https://github.com/llvm/llvm-project/commit/0390898335f9f32ea71ff288a5b4085cecc10391
Author: Jeremy Kun <jkun at google.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/Affine/Analysis/LoopAnalysis.h
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/lib/Dialect/Affine/Analysis/LoopAnalysis.cpp
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineLoopInvariantCodeMotion.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopTiling.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopUnroll.cpp
M mlir/lib/Dialect/Affine/Transforms/PipelineDataTransfer.cpp
M mlir/lib/Dialect/Affine/Utils/LoopFusionUtils.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
A mlir/test/Dialect/Affine/trip-count.mlir
Log Message:
-----------
[mlir][affine] Implement LoopLikeInterface::getStaticTripCount on AffineForOp (#204687)
LoopLikeInterface is useful, but missing `getStaticTripCount` requires
adding extra cases to check when processing otherwise dialect-agnostic
code.
There is an existing free function `getConstantTripCount`, which I
deprecated and replaced (NFC) with the new implementation. I believe the
new implementation is slightly more efficient than
`getConstantTripCount` because it checks if the expression is constant
and fast-fails before constructing the output `AffineMap` that was
returned by `getTripCountMapAndOperands`.
Assisted by Gemini
Commit: 72af16e1a1cc3e1db9a5cd458f4ed410ca90cb87
https://github.com/llvm/llvm-project/commit/72af16e1a1cc3e1db9a5cd458f4ed410ca90cb87
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/test/lit.cfg.py
Log Message:
-----------
[clang][FreeBSD] Re-enable the crash-recovery test on FreeBSD (#192608)
All of the tests work now on FreeBSD, so we re-enable the feature again
on FreeBSD.
Commit: 825950238fffb9549b7fd81700bb241e1473c866
https://github.com/llvm/llvm-project/commit/825950238fffb9549b7fd81700bb241e1473c866
Author: quic-k <kushpal at qti.qualcomm.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/OSTargets.h
M clang/test/Preprocessor/hexagon-predefines.c
Log Message:
-----------
[Clang][Hexagon] Predefine _GNU_SOURCE for C++ compilations (#201599)
Predefine _GNU_SOURCE in C++ mode for H2, QuRT, and baremetal
Hexagon targets.
Signed-off-by: Kushal Pal <kushpal at qti.qualcomm.com>
Commit: 8eae496effc992b28c12c23374e89474956b9860
https://github.com/llvm/llvm-project/commit/8eae496effc992b28c12c23374e89474956b9860
Author: Vinay Deshmukh <vinay_deshmukh at outlook.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M libcxx/include/map
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/for_each.associative.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/ranges.for_each.associative.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/move_alloc.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/move_assign.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/merge.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/contains.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/contains_transparent.pass.cpp
M libcxx/test/std/containers/associative/multimap/empty.pass.cpp
M libcxx/test/std/containers/associative/multimap/get_allocator.pass.cpp
M libcxx/test/std/containers/associative/multimap/incomplete_type.pass.cpp
M libcxx/test/std/containers/associative/multimap/iterator.pass.cpp
M libcxx/test/std/containers/associative/multimap/max_size.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/alloc.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/assign_initializer_list.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/compare.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/compare_alloc.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/copy.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/copy_alloc.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/copy_assign.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/deduct.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/deduct_const.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/default.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/default_noexcept.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/dtor_noexcept.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/from_range.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/initializer_list.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/initializer_list_compare.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/initializer_list_compare_alloc.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/iter_iter.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/iter_iter_comp.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/iter_iter_comp_alloc.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/move.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/move_alloc.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/move_assign.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/move_noexcept.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.erasure/erase_if.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/clear.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/emplace.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/emplace_hint.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/erase_iter.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/erase_iter_iter.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/erase_key.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/extract_iterator.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/extract_key.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_allocator_requirements.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_cv.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_initializer_list.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_iter_cv.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_iter_iter.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_iter_rv.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_node_type.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_node_type_hint.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_range.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_rv.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/merge.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.nonmember/compare.three_way.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.nonmember/op_compare.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.observers/key_comp.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.observers/value_comp.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/count.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/count0.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/count_transparent.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/equal_range.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/equal_range0.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/equal_range_transparent.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/find.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/find0.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/lower_bound.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/lower_bound0.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/upper_bound.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/upper_bound0.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.special/member_swap.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.special/non_member_swap.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.special/swap_noexcept.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.value_compare/invoke.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.value_compare/types.pass.cpp
M libcxx/test/std/containers/associative/multimap/size.pass.cpp
M libcxx/test/std/containers/associative/multimap/types.pass.cpp
M libcxx/test/std/containers/container.node/node_handle.pass.cpp
Log Message:
-----------
[libc++] Make std::multimap constexpr as part of P3372R3 (#161901)
Fixes #128661
Co-authored-by: Nikolas Klauser <nikolasklauser at berlin.de>
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Commit: 46ece19eef8199137c0df10b492cadcb91060846
https://github.com/llvm/llvm-project/commit/46ece19eef8199137c0df10b492cadcb91060846
Author: Takuto Ikuta <tikuta at google.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M libcxx/include/string.h
Log Message:
-----------
[libc++] Add a missing include in string.h (#135134)
`stddef.h` is necessary for `size_t` in explicit Clang modules build.
Commit: 8ca5830992768650b77ee318dad5402108e8bed3
https://github.com/llvm/llvm-project/commit/8ca5830992768650b77ee318dad5402108e8bed3
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M libcxx/include/string
Log Message:
-----------
[libc++] Default the allocator argument for most string constructors (#169901)
Allocators are generally very cheap to copy, so avoiding copies by
having separate overloads is not that useful. Defaulting them
significanlty reduces the overload set the compiler has to consider and
simplifies the code, since we can remove some functions in the future.
Closes #87368
Commit: d6ccc29cb3a79631818e30f2f523fc6a91718f8a
https://github.com/llvm/llvm-project/commit/d6ccc29cb3a79631818e30f2f523fc6a91718f8a
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/cxx20.cpp
Log Message:
-----------
[clang][bytecode] Take AccessKinds into account in diagnoseNonConstVa… (#204824)
…riable
And diagnose it as a modification and not a read if applicable.
Commit: bf18f6f43052cb558502e3e6f4db6a7368fe7b61
https://github.com/llvm/llvm-project/commit/bf18f6f43052cb558502e3e6f4db6a7368fe7b61
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Support/CommandLine.h
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/lib/CodeGen/BranchFolding.cpp
M llvm/lib/CodeGen/GlobalMerge.cpp
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/MC/MCAsmInfo.cpp
M llvm/lib/MC/MCAsmInfoXCOFF.cpp
M llvm/lib/Remarks/RemarkStreamer.cpp
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/WithColor.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Transforms/ObjCARC/ObjCARCContract.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/tools/llvm-cov/CodeCoverage.cpp
M llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/tools/llvm-readobj/ObjDumper.h
M llvm/tools/llvm-readobj/llvm-readobj.cpp
M llvm/utils/yaml-bench/YAMLBench.cpp
Log Message:
-----------
[CommandLine] Make cl::boolOrDefault a scoped enum (#204553)
Prevents implicit conversion to bool/int, where BOU_FALSE wrongly
evaluated as true. All uses qualified as cl::boolOrDefault::BOU_*.
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude <noreply at anthropic.com>
Commit: 8c7b7dda518a28447660256c44c39d94d0c7e793
https://github.com/llvm/llvm-project/commit/8c7b7dda518a28447660256c44c39d94d0c7e793
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M lldb/source/Target/Target.cpp
Log Message:
-----------
[lldb] Fix format string (#204837)
GetLoadAddress() returns an integer value, not a null-terminated string.
Commit: 16a0a1042f7e4e5a0c667096fcdeb5803e06d120
https://github.com/llvm/llvm-project/commit/16a0a1042f7e4e5a0c667096fcdeb5803e06d120
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/SVEShuffleOpts.cpp
Log Message:
-----------
[NFC] Remove SVEShuffleOpts variable unused in release build (#204833)
Fixes a warning-as-error build failure for #193951
Commit: 5bb3690d08fd89b3bba9866fc68df56f02379294
https://github.com/llvm/llvm-project/commit/5bb3690d08fd89b3bba9866fc68df56f02379294
Author: Tim Gymnich <tim at gymni.ch>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
Log Message:
-----------
[llvm][Target] Avoid premature Twine .str() materialization (#204836)
Call sites in the AMDGPU and SPIRV parsers and the SystemZ AsmPrinter /
InstrInfo pass `expr.str()` (or `.str().c_str()`) to parameters of type
`const llvm::Twine &`, forcing a throwaway heap std::string that is
immediately rewrapped into a Twine. Drop the materialization and let
Twine accept the concatenation directly.
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: 467a5fe378edfce2d495417c1b224cc2967570a2
https://github.com/llvm/llvm-project/commit/467a5fe378edfce2d495417c1b224cc2967570a2
Author: Tim Gymnich <tim at gymni.ch>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/lib/Analysis/FlowSensitive/FormulaSerialization.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Frontend/DependencyFile.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/StaticAnalyzer/Checkers/Yaml.h
Log Message:
-----------
[clang] Avoid premature Twine .str() materialization (#204830)
Several call sites pass `expr.str()` to parameters of type `const
llvm::Twine &`, forcing a throwaway heap std::string that is immediately
rewrapped into a Twine. Drop the `.str()` and let Twine accept the
StringRef/concatenation directly.
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: 22dce64361a23b954e5275b151cdbefc92eaa204
https://github.com/llvm/llvm-project/commit/22dce64361a23b954e5275b151cdbefc92eaa204
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
Log Message:
-----------
[AMDGPU] Remove some functions unused since #105645. NFC. (#204844)
Commit: 29692c150f86d76cfb58e8bf2c0e97dc6afd2088
https://github.com/llvm/llvm-project/commit/29692c150f86d76cfb58e8bf2c0e97dc6afd2088
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/CMakeLists.txt
M libc/docs/headers/index.rst
M libc/include/CMakeLists.txt
A libc/include/libgen.yaml
M libc/src/CMakeLists.txt
M libc/src/__support/CPP/string_view.h
A libc/src/libgen/CMakeLists.txt
A libc/src/libgen/basename.cpp
A libc/src/libgen/basename.h
A libc/src/libgen/dirname.cpp
A libc/src/libgen/dirname.h
M libc/test/src/CMakeLists.txt
A libc/test/src/libgen/CMakeLists.txt
A libc/test/src/libgen/basename_death_test.cpp
A libc/test/src/libgen/basename_test.cpp
A libc/test/src/libgen/dirname_death_test.cpp
A libc/test/src/libgen/dirname_test.cpp
A libc/utils/docgen/libgen.yaml
Log Message:
-----------
[libc] Implement basename and dirname in libgen.h (#204554)
Added the POSIX standard functions basename and dirname under a new
libgen.h header. The implementations modify the input path in-place
using cpp::string_view to determine boundaries safely.
Added find_last_not_of to cpp::string_view to support trailing slash
removal.
Implemented:
* libc/include/libgen.yaml, libgen.h.def: Public API definitions.
* libc/src/libgen/basename.cpp, dirname.cpp: Generic implementations.
* libc/test/src/libgen/: Unit and hermetic tests.
Registered the new entrypoints for all active Linux targets (x86_64,
aarch64, arm, riscv) and added docgen configuration.
Assisted-by: Automated tooling, human reviewed.
Commit: fd6a30b11da2bcbce657aa26a362e7d24aa9cd44
https://github.com/llvm/llvm-project/commit/fd6a30b11da2bcbce657aa26a362e7d24aa9cd44
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M libcxx/test/libcxx/gdb/gdb_pretty_printer_test.sh.cpp
M libcxx/utils/gdb/libcxx/printers.py
Log Message:
-----------
[libcxx] Make std::pair pretty-printer ABI-independent (#201768)
std::pair is printed explicitly instead of relying on GDB's default
struct formatting to keep output stable across ABI configurations.
With _LIBCPP_DEPRECATED_ABI_DISABLE_PAIR_TRIVIAL_COPY_CTOR (default on
some platforms, e.g. FreeBSD), std::pair gains an empty
__non_trivially_copyable_base base class. GDB would otherwise render
this as <...__non_trivially_copyable_base<...>> = {<No data fields>},
which makes output ABI-dependent.
Only first and second are meaningful, so print them directly.
Commit: d43b360c0625f930fc9bc3bfedb9419bd4acf928
https://github.com/llvm/llvm-project/commit/d43b360c0625f930fc9bc3bfedb9419bd4acf928
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/reduced-value-replace-extractelement-cost.ll
Log Message:
-----------
[SLP] Fix reduction cost crash for reduced values replaced by extractelement
A reduced value may be replaced by an extractelement while vectorizing a
previous subvector, so it is no longer a key in ReducedValsToOps.
Look through replaced values to the reduction operation among their users.
Fixes #204814
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/204847
Commit: 8c922aa493a3357ef9a9fab28e903b12fc2250ce
https://github.com/llvm/llvm-project/commit/8c922aa493a3357ef9a9fab28e903b12fc2250ce
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Log Message:
-----------
[MemorySanitizer] Merge x86 BMI and PackedBits handlers into handleGenericBitManipulation (#204786)
As discussed on #204144 - its not necessary to have separate handlers, just because some are target intrinsics
Commit: abbb031d386908d4274306f77c9c2cdc3e34d28d
https://github.com/llvm/llvm-project/commit/abbb031d386908d4274306f77c9c2cdc3e34d28d
Author: David CARLIER <devnexen at gmail.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/binary-analysis/AArch64/cfg-warning.s
Log Message:
-----------
[BOLT][rewrite] warn about functions without CFG before binary analyses. (#197294)
Commit: 85c81a23e759d9f45da28d074beacffe14c2ba99
https://github.com/llvm/llvm-project/commit/85c81a23e759d9f45da28d074beacffe14c2ba99
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/MC/MCWin64EH.cpp
M llvm/lib/Target/X86/X86WinEHUnwindV3.cpp
A llvm/test/CodeGen/X86/win64-eh-unwindv3-split-large.ll
M llvm/test/MC/COFF/seh-unwindv3-inheritance.s
M llvm/test/MC/COFF/seh-unwindv3-large.s
M llvm/test/MC/COFF/seh-unwindv3-nonmirror.s
Log Message:
-----------
[x64][win] Windows x64 unwind v3: Use tail-relative epilog offsets and add size-based splitting (#203108)
Win64 Unwind v3 encodes each epilog's EpilogOffset as a signed 16-bit
field. The encoder previously measured the first epilog offset from the
fragment start, which overflowed for large functions and produced a
cryptic "<unknown>:0: value too large for field" error (and, on the
early .seh_handlerdata path, an assertion failure).
Two changes:
- MCWin64EH.cpp: Always emit epilog offsets tail-relative. The first
epilog descriptor is measured from the fragment end and subsequent ones
as deltas from the previous epilog, so descriptors are emitted in
descending address order (all non-positive, per spec). A new lazy
MCUnwindV3EpilogOffsetTargetExpr resolves the fragment-end-relative
value at layout time (it may not have a symbol yet when emitted via
.seh_handlerdata) and reports a clean, function-named diagnostic on
genuine overflow.
- X86WinEHUnwindV3.cpp: Add Unwind-v2-style size-based sub-fragment
splitting. In addition to the existing >7-epilog split, the pass now
splits a funclet into chained fragments when an epilog is too far from
its fragment tail (using the V2 approximate-instruction-count heuristic,
tunable via -x86-wineh-unwindv3-epilog-distance-threshold). Splits use
SEH_SplitChainedAtEndOfBlock so the split lands after the epilog,
keeping every epilog close to its tail; a long trailing region becomes
its own epilog-free chained fragment.
Updates seh-unwindv3-large.s expectations to the new tail-relative
values and adds win64-eh-unwindv3-split-large.ll covering size-based
splitting.
Commit: e995171352b00123961e5c55600dd96bd11e7b60
https://github.com/llvm/llvm-project/commit/e995171352b00123961e5c55600dd96bd11e7b60
Author: Vicky Nguyen <vicky.trucviennguyen at gmail.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/add.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[CIR][AArch64] Upstream widening-addition and vector-shift-left-and-widen NEON builtins (#204285)
Related to https://github.com/llvm/llvm-project/issues/185382
CIR lowering for
- widening-addition intrinsics
(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#widening-addition)
- vector-shift-left-and-widen intrinsics
(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-left-and-widen)
Port tests:
- `clang/test/CodeGen/AArch64/neon_intrinsics.c` to
`clang/test/CodeGen/AArch64/neon/add.c`
- `clang/test/CodeGen/AArch64/neon_intrinsics.c` to
`clang/test/CodeGen/AArch64/neon/intrinsics.c`
Commit: ae60782c82682d20764f888321efb5d53df18a4a
https://github.com/llvm/llvm-project/commit/ae60782c82682d20764f888321efb5d53df18a4a
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/CMakeLists.txt
M libc/docs/headers/index.rst
M libc/include/CMakeLists.txt
R libc/include/libgen.yaml
M libc/src/CMakeLists.txt
M libc/src/__support/CPP/string_view.h
R libc/src/libgen/CMakeLists.txt
R libc/src/libgen/basename.cpp
R libc/src/libgen/basename.h
R libc/src/libgen/dirname.cpp
R libc/src/libgen/dirname.h
M libc/test/src/CMakeLists.txt
R libc/test/src/libgen/CMakeLists.txt
R libc/test/src/libgen/basename_death_test.cpp
R libc/test/src/libgen/basename_test.cpp
R libc/test/src/libgen/dirname_death_test.cpp
R libc/test/src/libgen/dirname_test.cpp
R libc/utils/docgen/libgen.yaml
Log Message:
-----------
Revert "[libc] Implement basename and dirname in libgen.h (#204554)" (#204856)
Reverted due to death tests failing with ASan on buildbots. Reverts
commit 29692c150f86d76cfb58e8bf2c0e97dc6afd2088.
Commit: 403ce0dc4bf3b288323a6e62d7d9056befdde483
https://github.com/llvm/llvm-project/commit/403ce0dc4bf3b288323a6e62d7d9056befdde483
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/declarative-directive01.f90
M flang/test/Semantics/OpenMP/requires01.f90
M flang/test/Semantics/OpenMP/requires03.f90
M flang/test/Semantics/OpenMP/requires04.f90
M flang/test/Semantics/OpenMP/requires05.f90
M flang/test/Semantics/OpenMP/requires06.f90
M flang/test/Semantics/OpenMP/requires07.f90
M flang/test/Semantics/OpenMP/requires08.f90
M flang/test/Semantics/OpenMP/requires10.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[flang][OpenMP] Emit warning that REVERSE_OFFLOAD is not supported (#204647)
Right now we quietly ignore it, whereas the OpenMP spec mandates a
compilation error for requirements that the implementation does not
support.
The REVERSE_OFFLOAD was not causing a compilation error to allow testing
of incremental implementation improvements, but we should at least warn
about not supporting it.
Commit: ef5d544f9bc18c41941e0a701ed11124623fb480
https://github.com/llvm/llvm-project/commit/ef5d544f9bc18c41941e0a701ed11124623fb480
Author: Carlos Seo <carlos.seo at linaro.org>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/test/Lower/OpenMP/Todo/multiple-types-declare_reduction.f90
M flang/test/Lower/OpenMP/declare-reduction-character-allocatable.f90
M flang/test/Lower/OpenMP/declare-reduction-finalizer.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-component.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-defined-assign.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-rhs-call.f90
M flang/test/Lower/OpenMP/declare-reduction-no-initializer-intrinsic.f90
M flang/test/Lower/OpenMP/declare-reduction-no-initializer-target-derived.f90
A flang/test/Lower/OpenMP/declare-reduction-same-name-different-scope.f90
M flang/test/Lower/OpenMP/declare-reduction-target-intrinsic.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-combsub.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-derivedtype.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-initsub.f90
M flang/test/Lower/OpenMP/omp-declare-reduction.f90
Log Message:
-----------
[flang][OpenMP] Scope-qualify user-defined reduction names in lowering (#202474)
A named !$omp declare reduction was lowered to an omp.declare_reduction
operation whose symbol name was just the bare reduction name (e.g.
`@a`), without any scope qualification. Semantic name resolution was
correct and gave each scope its own reduction symbol, but lowering
deduplicates the declare reduction op by name, so two subroutines that
declared a reduction with the same name collapsed onto a single op.
As a result, a reduction(name:var) clause could bind to a declaration
that leaked in from a different scope.
Per OpenMP 6.0 7.6.14, a user-defined reduction has the same visibility
and accessibility as a variable declared at the same location.
Qualify the generated op name with the scope in which the reduction is
declared using mangleName, the same approach already used for
omp.private and declare mapper. This is applied consistently when the op
is created, when a clause references it, and when its existence is
checked, so the names always agree.
Fixes #181270
Commit: fa135bb8cb8c4adf9fb7d5eb93143182dd632cd4
https://github.com/llvm/llvm-project/commit/fa135bb8cb8c4adf9fb7d5eb93143182dd632cd4
Author: Zhige Chen <zhige_chen at outlook.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/test/tools/llubi/assume_invalid_align.ll
M llvm/test/tools/llubi/controlflow.ll
M llvm/test/tools/llubi/intr_vector_manip.ll
M llvm/test/tools/llubi/invoke_poison.ll
M llvm/test/tools/llubi/metadata.ll
A llvm/test/tools/llubi/verify.ll
M llvm/tools/llubi/lib/Interpreter.cpp
M llvm/tools/llubi/llubi.cpp
Log Message:
-----------
[llubi] Run verifier on the input IR (#204095)
This PR runs the IR verifier in llubi by default and adds a
`--disable-verify` opt-out.
Commit: eb21e784ce4a9ade6f00fad259889f9ab3f25d1a
https://github.com/llvm/llvm-project/commit/eb21e784ce4a9ade6f00fad259889f9ab3f25d1a
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86WinEHUnwindV3.cpp
Log Message:
-----------
Mark LastEpilogIdx as maybe_unused (#204857)
#203108 added a variable which is read only in debug builds, so we are
seeing warning in release builds without asserts.
Commit: d10349cb51e19e25697be1ce19324274a8570d07
https://github.com/llvm/llvm-project/commit/d10349cb51e19e25697be1ce19324274a8570d07
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/test/Transforms/InstCombine/pdep.ll
M llvm/test/Transforms/InstCombine/pext.ll
Log Message:
-----------
[InstSimplify] Add fold for pdep(0,x) -> 0 and pext(0,x) -> 0 (#204810)
As noted on #204144
Commit: bb87fbb82b93fec4f1f39015a1d9262746a4e62f
https://github.com/llvm/llvm-project/commit/bb87fbb82b93fec4f1f39015a1d9262746a4e62f
Author: Tim Gymnich <tim at gymni.ch>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/CAS/OnDiskGraphDB.cpp
M llvm/lib/CAS/OnDiskKeyValueDB.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/ObjCopy/COFF/COFFObjcopy.cpp
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/Transforms/IPO/InstrumentorConfigFile.cpp
M llvm/lib/Transforms/IPO/InstrumentorUtils.cpp
M llvm/tools/llvm-debuginfod/llvm-debuginfod.cpp
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
Log Message:
-----------
[llvm] Avoid premature Twine .str() materialization (#204828)
Commit: 394aa60e5678f07de7ad2f1923ddb2290f9ad7c6
https://github.com/llvm/llvm-project/commit/394aa60e5678f07de7ad2f1923ddb2290f9ad7c6
Author: Amr Hesham <amr96 at programmer.net>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
Log Message:
-----------
[CIR][NFC] Sync AArch64 NEON intrinsics with Clang (#204862)
Sync AArch64 NEON intrinsics with Clang after changes merged from
#204201
Commit: 7319a3cf812f487728a6f1de4f70846f9fee7513
https://github.com/llvm/llvm-project/commit/7319a3cf812f487728a6f1de4f70846f9fee7513
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/include/llvm/DebugInfo/DWARF/LowLevel/DWARFDataExtractorSimple.h
M llvm/include/llvm/Support/DataExtractor.h
M llvm/lib/DWP/DWP.cpp
M llvm/tools/llvm-dwarfdump/Statistics.cpp
M llvm/tools/llvm-objdump/SourcePrinter.cpp
M llvm/tools/llvm-readobj/DwarfCFIEHPrinter.h
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/tools/obj2yaml/elf2yaml.cpp
M llvm/unittests/DebugInfo/DWARF/DWARFExpressionCompactPrinterTest.cpp
M llvm/unittests/Support/DataExtractorTest.cpp
Log Message:
-----------
[Support] Remove unused parameter of DataExtractor constructor (#204840)
#190519 removed the uses of the parameter, and several follow-up patches
cleaned up call sites. This is the last patch in the series that finally
removes the parameter.
While here, also remove the unused "truncating constructor".
Commit: 95e321951ad3041998e49bc0353482bcd27c65db
https://github.com/llvm/llvm-project/commit/95e321951ad3041998e49bc0353482bcd27c65db
Author: lonely eagle <2020382038 at qq.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M mlir/lib/Conversion/PtrToLLVM/PtrToLLVM.cpp
M mlir/test/Conversion/PtrToLLVM/ptr-to-llvm.mlir
Log Message:
-----------
[mlir][ptr] Add constantop convertion (#204846)
Previously, Ptr.ConstantOp was missing the lowering pattern to LLVM IR.
This PR adds the missing conversion logic. See
https://github.com/llvm/llvm-project/pull/190527#issuecomment-4751141164.
---------
Co-authored-by: Fabian Mora <fmora.dev at gmail.com>
Commit: f4043dbcafc93f9107b7c93ee8740cdb0fe22d7c
https://github.com/llvm/llvm-project/commit/f4043dbcafc93f9107b7c93ee8740cdb0fe22d7c
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
A lldb/test/API/macosx/deny-attach/Makefile
A lldb/test/API/macosx/deny-attach/TestDenyAttach.py
A lldb/test/API/macosx/deny-attach/main.c
M lldb/tools/debugserver/source/MacOSX/MachProcess.mm
Log Message:
-----------
[lldb] Survive ptrace(PT_DENY_ATTACH) when attaching (#204688)
A process can opt out of being debugged with ptrace(PT_DENY_ATTACH). The
XNU kernel enforces this by delivering SIGSEGV to the *attaching*
process while it is still inside the ptrace(PT_ATTACHEXC) syscall. This
means debugserver gets killed before it can inspect the result. LLDB
only sees the dropped connection ("error: attach failed: lost
connection").
The condition can't be detected up front: the target's P_LNOATTACH flag
is not exposed to userspace. To work around this, install a temporary
SIGSEGV handler around the ptrace(PT_ATTACHEXC) call in AttachForDebug
and siglongjmp back out if it fires, turning the fatal signal into an
EPERM that propagates to lldb as a clear message:
```
error: attach failed: cannot attach to process N because it has
disabled debugging via ptrace(PT_DENY_ATTACH)
```
The handler only acts on a SIGSEGV that arrives on the attaching thread
while the guard is armed. Any other SIGSEGV restores the default handler
and re-raises. Genuine, unrelated, crashes still report normally.
rdar://44542907
Assisted-by: Claude
Commit: 6b7dbd8f485dc710f41fe5383ac99c2c42f9f6b9
https://github.com/llvm/llvm-project/commit/6b7dbd8f485dc710f41fe5383ac99c2c42f9f6b9
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for gfx950 mfmas (#204696)
Commit: d1c306c5ef9fc687df3630145b256f0d67a767b2
https://github.com/llvm/llvm-project/commit/d1c306c5ef9fc687df3630145b256f0d67a767b2
Author: Amr Hesham <amr96 at programmer.net>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
A clang/test/CIR/CodeGen/agg-atomic-cast.cpp
Log Message:
-----------
[CIR] Implement Aggregate non-atomic to atomic cast (#204653)
Implement support for Aggregate non-atomic to atomic cast
Commit: e6a92e0d2dbe413f994ad743f3f94cc9f0281b82
https://github.com/llvm/llvm-project/commit/e6a92e0d2dbe413f994ad743f3f94cc9f0281b82
Author: Kevin Sala Penades <salapenades1 at llnl.gov>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/RecordReplay.cpp
M offload/test/tools/omp-kernel-replay/record-replay-diff-teams-threads.cpp
M offload/test/tools/omp-kernel-replay/record-replay-diff-threads.cpp
M offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp
Log Message:
-----------
[offload] Fix teams/threads limits in record replay (#200639)
The recording phase now sets the teams and threads limits provided by
the user (in the corresponding OpenMP clauses) or zero if not specified.
Additionally, the PR #199483 already enforces that replay's configuration
of threads and teams are respected.
This commit also changes the way we test record and replay when multiple
kernels are recorded in the same test. We use the record report to know how
to associate a json record descriptor file to the target region in the code. We
do not rely anymore on the modification time of the files to know the order,
which was problematic.
Commit: f1931891a9fe19c4b003b7dd2665ddc887f91a0d
https://github.com/llvm/llvm-project/commit/f1931891a9fe19c4b003b7dd2665ddc887f91a0d
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M libcxx/include/__cstddef/byte.h
M libcxx/test/libcxx/language.support/nodiscard.verify.cpp
Log Message:
-----------
[libc++][byte] Apply [[nodiscard]] to std::byte (#204674)
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
Towards: #172124
Commit: fe9521d11834f9c408406b5a5d6c617c6156d1b8
https://github.com/llvm/llvm-project/commit/fe9521d11834f9c408406b5a5d6c617c6156d1b8
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[LV] Unify header phi fixup and remove fixNonInductionPHIs (NFC). (#204886)
Unify the execute logic for VPPhi and VPWidenPHIRecipe into a shared
executePhiRecipe helper that handles both scalar and vector phis. For
header phis, only the preheader incoming value is added during execute;
the backedge is fixed up later by VPlan::execute().
This allows generalizing the VPlan::execute() fixup loop to handle all
loop headers (not just the first), removing the VPWidenPHIRecipe skip,
and eliminating fixNonInductionPHIs entirely.
Commit: 39f8f90cc9d8cf650823f397e56244b4d84168ff
https://github.com/llvm/llvm-project/commit/39f8f90cc9d8cf650823f397e56244b4d84168ff
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/test/CodeGen/SPIRV/instructions/undef-composite.ll
Log Message:
-----------
[SPIR-V] Lower undef nested in a constant aggregate (#204377)
A constant aggregate whose element is itself an aggregate `undef` was
never lowered to a placeholder. The raw aggregate operand reached
IRTranslator on the llvm.spv.const.composite call and aborted with
"unable to translate instruction".
A similar issue was found and fixed during SPV_KHR_poison_freeze
implementation. So instead of re-inventing a wheel - unify lowering with
poison.
Addresses the following observation:
https://github.com/llvm/llvm-project/pull/198037#discussion_r3304013315
Commit: 4195b294cb82f50fdfb980434439a22a0f5be315
https://github.com/llvm/llvm-project/commit/4195b294cb82f50fdfb980434439a22a0f5be315
Author: Tom Stellard <tstellar at redhat.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M .github/workflows/subscriber.yml
Log Message:
-----------
workflows/subscriber: Update to latest github automation container (#204692)
This one is about 33% smaller than the previous version.
Commit: 086f6331a5a904da8de84b30dcdaddc0a6220ed1
https://github.com/llvm/llvm-project/commit/086f6331a5a904da8de84b30dcdaddc0a6220ed1
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.async.to.lds.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for load_async_to_lds (#204683)
Commit: f9fa59867f663d965dd7a6a72777477c4decee4d
https://github.com/llvm/llvm-project/commit/f9fa59867f663d965dd7a6a72777477c4decee4d
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/addsub64_carry.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
A llvm/test/CodeGen/AMDGPU/i128-add-carry-chain.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
Log Message:
-----------
[AMDGPU] Use explicit carry nodes for i64 wide integer lowering (#204694)
This PR switches widened i64 add/sub lowering to use explicit
UADDO/USUBO carry
nodes instead of glue-based carry chains.
Commit: 90b204888de4da58d4f3b68355658c16a14a1e46
https://github.com/llvm/llvm-project/commit/90b204888de4da58d4f3b68355658c16a14a1e46
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
A llvm/test/Bitcode/Inputs/invalid-summary-version.bc
A llvm/test/Bitcode/invalid-summary-version.test
Log Message:
-----------
bitcode: Improve invalid summary version error (#204888)
Commit: c890f4dbc248cf5f22e9f5b212d03be44b77d499
https://github.com/llvm/llvm-project/commit/c890f4dbc248cf5f22e9f5b212d03be44b77d499
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 95e3219 (#204873)
This fixes 95e321951ad3041998e49bc0353482bcd27c65db.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: a8aba704b0972253ffb6d7bda770ecef43f5b131
https://github.com/llvm/llvm-project/commit/a8aba704b0972253ffb6d7bda770ecef43f5b131
Author: Steve Scalpone <sscalpone at nvidia.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/MultiImageFortran.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Transforms/MIFOpConversion.cpp
M flang/test/Lower/MIF/coarray_allocation3.f90
M flang/test/Lower/MIF/coarray_allocation4.f90
M flang/test/Lower/MIF/coarray_allocation5.f90
Log Message:
-----------
[Flang] Standardize coarray TODO() diagnostic messages (#204708)
Commit: ba5384a3e154e6f43ddc951ebc81b4b5edafcc1b
https://github.com/llvm/llvm-project/commit/ba5384a3e154e6f43ddc951ebc81b4b5edafcc1b
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/include/llvm/Support/CommandLine.h
M llvm/lib/Support/CommandLine.cpp
M llvm/unittests/Support/CommandLineTest.cpp
Log Message:
-----------
[Support] Add a parser for cl::opt<ElementCount> (#203969)
This adds command-line option parsing support for ElementCount.
This allows the following syntax:
```
--my-option=4 ; Maps to ElementCount::getFixed(4)
--my-option="vscale x 8" ; Maps to ElementCount::getScalable(8)
```
This is intended to unify fixed/scalable option handling in the loop
vectorizer. Currently, we have options like
'`EpilogueVectorizationForceVF`' defined as `cl::opt<unsigned>` which do
not allow specifying scalable VFs.
Assisted-by: Codex
Commit: b32488f78b6c029aa0b0a011dbc8c593f2e8cb34
https://github.com/llvm/llvm-project/commit/b32488f78b6c029aa0b0a011dbc8c593f2e8cb34
Author: Hubert Tong <hubert.reinterpretcast at gmail.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/test/CodeGen/ubsan-aggregate-null-align-bounds.c
Log Message:
-----------
[Clang][UBSan] Use EmitCheckedLValue for C++ trivial operator= operands (#203737)
Further to https://github.com/llvm/llvm-project/pull/190739, use
EmitCheckedLValue for trivial operator= operands
* for the LHS (`lhs->` not handled yet), and
* for the RHS also for function call syntax.
Commit: e47530b9f4d6c2417aeb578af615710cdce50597
https://github.com/llvm/llvm-project/commit/e47530b9f4d6c2417aeb578af615710cdce50597
Author: YongKang Zhu <yongzhu at fb.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M bolt/include/bolt/Core/BinaryContext.h
M bolt/lib/Passes/Aligner.cpp
M bolt/lib/Passes/LongJmp.cpp
M bolt/lib/Rewrite/BinaryPassManager.cpp
Log Message:
-----------
[BOLT][AArch64] Align tentative layout bases using per-section alignment (#204262)
Move `AssignSections` pass before `AlignerPass` so it can record the max
code alignment per output section, then align the tentative hot/cold
section bases using the recorded alignment, which makes tentative layout
better match actually emitted.
Commit: 092858485f00e6786da8a88c0c4d462247e64571
https://github.com/llvm/llvm-project/commit/092858485f00e6786da8a88c0c4d462247e64571
Author: owenca <owenpiano at gmail.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/FormatTokenLexer.h
Log Message:
-----------
[clang-format][NFC] Clean up FormatTokenLexer (#203825)
Commit: 359bfe62ed1b1cd498cee558ed8699b2b88ae58b
https://github.com/llvm/llvm-project/commit/359bfe62ed1b1cd498cee558ed8699b2b88ae58b
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M clang/docs/LifetimeSafety.rst
M clang/include/clang/Basic/LangOptions.h
M clang/include/clang/Options/Options.td
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/test/Sema/LifetimeSafety/annotation-suggestions-fixits.cpp
M clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-intra-tu.cpp
Log Message:
-----------
[LifetimeSafety] Allow configuring lifetimebound fix-it spelling (#204045)
When suggesting `[[clang::lifetimebound]]` fix-its, allow users to
provide a project-specific macro spelling with
`-lifetime-safety-lifetimebound-macro=...`.
If no spelling is configured, use a visible macro whose replacement
tokens spell the attribute, preferring the most recently defined
matching macro, and fall back to `[[clang::lifetimebound]]` or
`__attribute((lifetimebound))` otherwise.
Closes https://github.com/llvm/llvm-project/issues/200232
Commit: 2678b8f51e10df0beacade724b781ee214ec58f6
https://github.com/llvm/llvm-project/commit/2678b8f51e10df0beacade724b781ee214ec58f6
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2026-06-19 (Fri, 19 Jun 2026)
Changed paths:
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILResourceAccess.cpp
A llvm/test/CodeGen/DirectX/ResourceAccess/load-constant-buffer-t.ll
Log Message:
-----------
[DirectX] Handle llvm.dx.resource.getbasepointer intrinsic in DXILResourceAccess pass (#204732)
The `llvm.dx.resource.getbasepointer` intrinsic is emitted for
`Constantbuffer<T>` element access and needs to be translated to
`llvm.dx.resource.load.cbufferrow` calls in the `DXILResourceAccess`
pass. The handling is identical to `llvm.dx.resource.getpointer` with a
0 offset.
Fixes #204234
Commit: e9acb01904be7c32e98dedee27b68f939d79549a
https://github.com/llvm/llvm-project/commit/e9acb01904be7c32e98dedee27b68f939d79549a
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Options/Options.td
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/test/Driver/openmp-offload-gpu.c
M clang/test/OpenMP/bug60602.cpp
M clang/test/OpenMP/declare_target_local_codegen.cpp
M clang/test/OpenMP/distribute_codegen.cpp
M clang/test/OpenMP/distribute_firstprivate_codegen.cpp
M clang/test/OpenMP/distribute_lastprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_if_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp
M clang/test/OpenMP/distribute_private_codegen.cpp
M clang/test/OpenMP/distribute_simd_codegen.cpp
M clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/distribute_simd_private_codegen.cpp
M clang/test/OpenMP/distribute_simd_reduction_codegen.cpp
M clang/test/OpenMP/map_struct_ordering.cpp
M clang/test/OpenMP/nvptx_lambda_capturing.cpp
R clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp
M clang/test/OpenMP/reduction_implicit_map.cpp
M clang/test/OpenMP/spirv_target_teams_reduction_addrspace.c
M clang/test/OpenMP/target_codegen_global_capture.cpp
M clang/test/OpenMP/target_default_codegen.cpp
M clang/test/OpenMP/target_defaultmap_codegen_03.cpp
M clang/test/OpenMP/target_dyn_groupprivate_codegen.cpp
M clang/test/OpenMP/target_firstprivate_codegen.cpp
M clang/test/OpenMP/target_has_device_addr_codegen.cpp
M clang/test/OpenMP/target_has_device_addr_codegen_01.cpp
M clang/test/OpenMP/target_is_device_ptr_codegen.cpp
M clang/test/OpenMP/target_map_array_of_structs_with_nested_mapper_codegen.cpp
M clang/test/OpenMP/target_map_array_section_no_length_codegen.cpp
M clang/test/OpenMP/target_map_array_section_of_structs_with_nested_mapper_codegen.cpp
M clang/test/OpenMP/target_map_codegen_03.cpp
M clang/test/OpenMP/target_map_codegen_hold.cpp
M clang/test/OpenMP/target_map_deref_array_codegen.cpp
M clang/test/OpenMP/target_map_member_expr_codegen.cpp
M clang/test/OpenMP/target_offload_mandatory_codegen.cpp
M clang/test/OpenMP/target_ompx_dyn_cgroup_mem_codegen.cpp
M clang/test/OpenMP/target_parallel_codegen.cpp
M clang/test/OpenMP/target_parallel_for_codegen.cpp
M clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/target_parallel_generic_loop_codegen-1.cpp
M clang/test/OpenMP/target_parallel_generic_loop_codegen-2.cpp
M clang/test/OpenMP/target_parallel_generic_loop_uses_allocators_codegen.cpp
M clang/test/OpenMP/target_parallel_if_codegen.cpp
M clang/test/OpenMP/target_parallel_num_threads_codegen.cpp
M clang/test/OpenMP/target_parallel_num_threads_strict_codegen.cpp
M clang/test/OpenMP/target_task_affinity_codegen.cpp
M clang/test/OpenMP/target_teams_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_proc_bind_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_private_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen-1.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_collapse_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_if_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_order_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_uses_allocators_codegen.cpp
M clang/test/OpenMP/target_teams_map_codegen.cpp
M clang/test/OpenMP/target_teams_num_teams_codegen.cpp
A clang/test/OpenMP/target_teams_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_thread_limit_codegen.cpp
M clang/test/OpenMP/teams_codegen.cpp
M clang/test/OpenMP/teams_distribute_codegen.cpp
M clang/test/OpenMP/teams_distribute_collapse_codegen.cpp
M clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_proc_bind_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_private_codegen.cpp
M clang/test/OpenMP/teams_distribute_reduction_codegen.cpp
M clang/test/OpenMP/teams_distribute_simd_codegen.cpp
M clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp
M clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp
M clang/test/OpenMP/teams_distribute_simd_reduction_codegen.cpp
M clang/test/OpenMP/teams_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_generic_loop_codegen-1.cpp
M clang/test/OpenMP/teams_generic_loop_collapse_codegen.cpp
M clang/test/OpenMP/teams_generic_loop_private_codegen.cpp
M clang/test/OpenMP/teams_generic_loop_reduction_codegen.cpp
M clang/test/OpenMP/teams_private_codegen.cpp
M llvm/include/llvm/Frontend/OpenMP/OMPConstants.h
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
M llvm/test/Transforms/OpenMP/add_attributes.ll
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/allocatable_gpu_reduction_teams.mlir
M mlir/test/Target/LLVMIR/omptarget-multi-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-region-device-llvm.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction-array-descriptor.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-reduction.mlir
M mlir/test/Target/LLVMIR/openmp-target-launch-device.mlir
M offload/include/Shared/Environment.h
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M openmp/device/include/Interface.h
M openmp/device/src/Reduction.cpp
Log Message:
-----------
[OpenMP][offload] Cross-team reductions with variable number of teams (#195102)
This is a part of a series of patches that rework OpenMP cross-team
reductions.
This patch changes the cross-team reduction runtime to no longer work
through larger number of teams in chunks. Instead, we allocate a
suitable-sized global buffer for the team values and let all teams run
at once. The last team that finishes uses a strided loop to reduce the
team values from the global buffer.
We also use `mapping::getNumberOfThreadsInBlock()` instead of
`omp_get_num_threads()` because the reduction of the team values runs
outside of the parallel region device code, which would make
`omp_get_num_threads()` always return 1. For Generic-SPMD mode, we also
want to use all available threads, which means that we need to copy the
reduction data from LDS (where it lives in that mode by default) to
scratch in codegen before calling the cross-team reduction.
Performance:
All performance tests can be reproduced with
https://github.com/ro-i/xteam-test @ commit
2f09ae1f566f13189d20b414d8b83bf2986564d2. To reproduce, simply create a
`local.mk` file in the cloned directory with a suitable `OFFLOAD_ARCH`
for your machine and `CXX_trunk` + `CXX_trunk_dev` set to the paths of
the clang++ binaries for llvm/main and this patch. (llvm/main should
best be at the commit that is currently the base for this PR. At the
moment, this is fe87c971bf07eb38af97ca96bf2810e94e7549dc). Then, run
`make trunk trunk_dev` to build the benchmark binaries for 208 and 10400
teams. Run them with `./run_bench.sh -rq -n10 red_trunk_208
red_trunk_dev_208 red_trunk_10400 red_trunk_dev_10400` to get the avg
performance numbers over 10 rounds.
This tests multiple reduction workloads, including reductions that run
in the Generic-SPMD mode, with 208 teams and with 10400 teams, both à
512 threads, and with a reduction array size of 177,777,777. I tested on
a gfx942 and didn't find any regressions - here are some numbers showing
the performance of this patch relative to the baseline:
```
red_comb_sep_arr_32 double dev_208: +84.37% dev_10400: +54.06%
red_sum_arr_32 double dev_208: +9.72% dev_10400: +51.29%
red_comb double dev_208: +2.73% dev_10400: +8.73%
red_comb_sep double dev_208: +1.89% dev_10400: +87.13%
red_dot double dev_208: +1.46% dev_10400: +25.66%
red_indirect double dev_208: +1.51% dev_10400: +23.54%
red_kernel_part double dev_208: +1.27% dev_10400: +88.28%
red_max double dev_208: +1.29% dev_10400: +22.69%
red_mult double dev_208: +1.96% dev_10400: +22.02%
red_sum double dev_208: +2.03% dev_10400: +22.00%
red_pi double dev_208: +1.08% dev_10400: +1.22%
red_comb_sep_arr_32 uint dev_208: +139.10% dev_10400: +88.02%
red_sum_arr_32 uint dev_208: +49.70% dev_10400: +143.24%
red_dot uint dev_208: +0.77% dev_10400: +24.91%
red_max uint dev_208: +3.43% dev_10400: +36.61%
red_sum uint dev_208: +4.56% dev_10400: +36.95%
red_comb_sep_arr_32 ulong dev_208: +85.22% dev_10400: +58.17%
red_sum_arr_32 ulong dev_208: +9.01% dev_10400: +55.14%
red_dot ulong dev_208: +2.94% dev_10400: +26.89%
red_max ulong dev_208: +2.83% dev_10400: +23.10%
red_sum ulong dev_208: +1.59% dev_10400: +22.82%
red_comb_sep_arr_32 Value dev_208: +29.88% dev_10400: +24.17%
red_sum_arr_32 Value dev_208: +7.26% dev_10400: +38.14%
red_dot Value dev_208: +2.65% dev_10400: +8.60%
red_max Value dev_208: +2.86% dev_10400: +4.77%
red_sum Value dev_208: +0.47% dev_10400: +10.22%
```
This patch uses ideas from Johannes Doerfert, ideas from the AOMP
cross-team reduction implementation, and was assisted by Claude.
Commit: 4c16440e1edc00cd1b5a64944fc651064fe6425b
https://github.com/llvm/llvm-project/commit/4c16440e1edc00cd1b5a64944fc651064fe6425b
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Options/Options.td
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/test/Driver/openmp-offload-gpu.c
M clang/test/OpenMP/bug60602.cpp
M clang/test/OpenMP/declare_target_local_codegen.cpp
M clang/test/OpenMP/distribute_codegen.cpp
M clang/test/OpenMP/distribute_firstprivate_codegen.cpp
M clang/test/OpenMP/distribute_lastprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_if_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_proc_bind_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp
M clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp
M clang/test/OpenMP/distribute_private_codegen.cpp
M clang/test/OpenMP/distribute_simd_codegen.cpp
M clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/distribute_simd_private_codegen.cpp
M clang/test/OpenMP/distribute_simd_reduction_codegen.cpp
M clang/test/OpenMP/map_struct_ordering.cpp
M clang/test/OpenMP/nvptx_lambda_capturing.cpp
A clang/test/OpenMP/nvptx_teams_reduction_codegen.cpp
M clang/test/OpenMP/reduction_implicit_map.cpp
M clang/test/OpenMP/spirv_target_teams_reduction_addrspace.c
M clang/test/OpenMP/target_codegen_global_capture.cpp
M clang/test/OpenMP/target_default_codegen.cpp
M clang/test/OpenMP/target_defaultmap_codegen_03.cpp
M clang/test/OpenMP/target_dyn_groupprivate_codegen.cpp
M clang/test/OpenMP/target_firstprivate_codegen.cpp
M clang/test/OpenMP/target_has_device_addr_codegen.cpp
M clang/test/OpenMP/target_has_device_addr_codegen_01.cpp
M clang/test/OpenMP/target_is_device_ptr_codegen.cpp
M clang/test/OpenMP/target_map_array_of_structs_with_nested_mapper_codegen.cpp
M clang/test/OpenMP/target_map_array_section_no_length_codegen.cpp
M clang/test/OpenMP/target_map_array_section_of_structs_with_nested_mapper_codegen.cpp
M clang/test/OpenMP/target_map_codegen_03.cpp
M clang/test/OpenMP/target_map_codegen_hold.cpp
M clang/test/OpenMP/target_map_deref_array_codegen.cpp
M clang/test/OpenMP/target_map_member_expr_codegen.cpp
M clang/test/OpenMP/target_offload_mandatory_codegen.cpp
M clang/test/OpenMP/target_ompx_dyn_cgroup_mem_codegen.cpp
M clang/test/OpenMP/target_parallel_codegen.cpp
M clang/test/OpenMP/target_parallel_for_codegen.cpp
M clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/target_parallel_generic_loop_codegen-1.cpp
M clang/test/OpenMP/target_parallel_generic_loop_codegen-2.cpp
M clang/test/OpenMP/target_parallel_generic_loop_uses_allocators_codegen.cpp
M clang/test/OpenMP/target_parallel_if_codegen.cpp
M clang/test/OpenMP/target_parallel_num_threads_codegen.cpp
M clang/test/OpenMP/target_parallel_num_threads_strict_codegen.cpp
M clang/test/OpenMP/target_task_affinity_codegen.cpp
M clang/test/OpenMP/target_teams_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_if_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_proc_bind_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_proc_bind_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_private_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen-1.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_collapse_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_if_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_order_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_uses_allocators_codegen.cpp
M clang/test/OpenMP/target_teams_map_codegen.cpp
M clang/test/OpenMP/target_teams_num_teams_codegen.cpp
R clang/test/OpenMP/target_teams_reduction_codegen.cpp
M clang/test/OpenMP/target_teams_thread_limit_codegen.cpp
M clang/test/OpenMP/teams_codegen.cpp
M clang/test/OpenMP/teams_distribute_codegen.cpp
M clang/test/OpenMP/teams_distribute_collapse_codegen.cpp
M clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_if_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_proc_bind_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_if_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_proc_bind_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_codegen.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_private_codegen.cpp
M clang/test/OpenMP/teams_distribute_reduction_codegen.cpp
M clang/test/OpenMP/teams_distribute_simd_codegen.cpp
M clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp
M clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp
M clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_simd_lastprivate_codegen.cpp
M clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp
M clang/test/OpenMP/teams_distribute_simd_reduction_codegen.cpp
M clang/test/OpenMP/teams_firstprivate_codegen.cpp
M clang/test/OpenMP/teams_generic_loop_codegen-1.cpp
M clang/test/OpenMP/teams_generic_loop_collapse_codegen.cpp
M clang/test/OpenMP/teams_generic_loop_private_codegen.cpp
M clang/test/OpenMP/teams_generic_loop_reduction_codegen.cpp
M clang/test/OpenMP/teams_private_codegen.cpp
M llvm/include/llvm/Frontend/OpenMP/OMPConstants.h
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
M llvm/test/Transforms/OpenMP/add_attributes.ll
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/allocatable_gpu_reduction_teams.mlir
M mlir/test/Target/LLVMIR/omptarget-multi-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-region-device-llvm.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction-array-descriptor.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-teams-reduction.mlir
M mlir/test/Target/LLVMIR/openmp-target-launch-device.mlir
M offload/include/Shared/Environment.h
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M openmp/device/include/Interface.h
M openmp/device/src/Reduction.cpp
Log Message:
-----------
Revert "[OpenMP][offload] Cross-team reductions with variable number of teams" (#204914)
Reverts llvm/llvm-project#195102 due to some missed debug info issue
revealed by https://lab.llvm.org/buildbot/#/builders/67/builds/7022
Commit: a38998941b2f57ffce38d6161a48d59d7d481964
https://github.com/llvm/llvm-project/commit/a38998941b2f57ffce38d6161a48d59d7d481964
Author: Ferdinand Lemaire <flscminecraft at gmail.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
A mlir/include/mlir/Conversion/RaiseWasm/RaiseWasmMLIR.h
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSAOps.td
M mlir/lib/Conversion/CMakeLists.txt
A mlir/lib/Conversion/RaiseWasm/CMakeLists.txt
A mlir/lib/Conversion/RaiseWasm/RaiseWasmMLIR.cpp
M mlir/lib/Dialect/WasmSSA/IR/WasmSSAOps.cpp
A mlir/test/Conversion/RaiseWasm/wasm-abs-to-math-abs.mlir
A mlir/test/Conversion/RaiseWasm/wasm-add-to-arith-add.mlir
A mlir/test/Conversion/RaiseWasm/wasm-and-to-arith-and.mlir
A mlir/test/Conversion/RaiseWasm/wasm-ceil-to-math-ceil.mlir
A mlir/test/Conversion/RaiseWasm/wasm-clz-to-math-clz.mlir
A mlir/test/Conversion/RaiseWasm/wasm-const-to-arith-const.mlir
A mlir/test/Conversion/RaiseWasm/wasm-convert-to-arith-tofp.mlir
A mlir/test/Conversion/RaiseWasm/wasm-copysign-to-math-copysign.mlir
A mlir/test/Conversion/RaiseWasm/wasm-ctz-to-math-ctz.mlir
A mlir/test/Conversion/RaiseWasm/wasm-demote-to-arith-trunc.mlir
A mlir/test/Conversion/RaiseWasm/wasm-div-to-arith-div.mlir
A mlir/test/Conversion/RaiseWasm/wasm-floor-to-math-floor.mlir
A mlir/test/Conversion/RaiseWasm/wasm-func-to-func.mlir
A mlir/test/Conversion/RaiseWasm/wasm-global-to-memref-global.mlir
A mlir/test/Conversion/RaiseWasm/wasm-local-to-memref.mlir
A mlir/test/Conversion/RaiseWasm/wasm-max-to-arith-maximumf.mlir
A mlir/test/Conversion/RaiseWasm/wasm-min-to-arith-minimumf.mlir
A mlir/test/Conversion/RaiseWasm/wasm-mul-to-arith-mul.mlir
A mlir/test/Conversion/RaiseWasm/wasm-neg-to-arith-neg.mlir
A mlir/test/Conversion/RaiseWasm/wasm-or-to-arith-or.mlir
A mlir/test/Conversion/RaiseWasm/wasm-popcnt-to-math-ctpop.mlir
A mlir/test/Conversion/RaiseWasm/wasm-promote-to-arith-ext.mlir
A mlir/test/Conversion/RaiseWasm/wasm-reinterpret-to-arith-bitcast.mlir
A mlir/test/Conversion/RaiseWasm/wasm-rem-to-arith-rem.mlir
A mlir/test/Conversion/RaiseWasm/wasm-shl-to-arith-shl.mlir
A mlir/test/Conversion/RaiseWasm/wasm-shr_s-to-arith-shrs.mlir
A mlir/test/Conversion/RaiseWasm/wasm-shr_u-to-arith-shru.mlir
A mlir/test/Conversion/RaiseWasm/wasm-sqrt-to-math-sqrt.mlir
A mlir/test/Conversion/RaiseWasm/wasm-sub-to-arith-sub.mlir
A mlir/test/Conversion/RaiseWasm/wasm-trunc-to-math-trunc.mlir
A mlir/test/Conversion/RaiseWasm/wasm-wrap-to-arith-trunc.mlir
A mlir/test/Conversion/RaiseWasm/wasm-xor-to-arith-xor.mlir
Log Message:
-----------
[MLIR][WASM] Introduce the RaiseWasmMLIRPass to convert WasmSSA MLIR to core dialects (#164562)
This is following https://github.com/llvm/llvm-project/pull/154674 and
still related to
https://discourse.llvm.org/t/rfc-mlir-dialect-for-webassembly/86758.
This PR introduces the RaiseWasmMLIRPass. This pass lowers WasmSSA MLIR
to other dialects of the LLVM ecosystem (namely: arith, math, cf and
memref).
This is the first PR of a series of 2 or 3 to introduce the lowering, as
an introduction it brings support for function calls, local and global
variables and handling of arithmetic operations. As explained in the
RFC, most WasmSSA operations have been made to stay close to other
dialects' semantics so that conversion is trivialized.
---------
Signed-off-by: Ferdinand Lemaire <flemairen6 at gmail.com>
Co-authored-by: Ferdinand Lemaire <ferdinand.lemaire at woven-planet.global>
Co-authored-by: Ferdinand Lemaire <flemairen6 at gmail.com>
Commit: ea9bae08990f581e9dce8f65844bc16b3249f91e
https://github.com/llvm/llvm-project/commit/ea9bae08990f581e9dce8f65844bc16b3249f91e
Author: Luc Forget <github at alias.lforget.fr>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
R mlir/include/mlir/Conversion/RaiseWasm/RaiseWasmMLIR.h
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSAOps.td
M mlir/lib/Conversion/CMakeLists.txt
R mlir/lib/Conversion/RaiseWasm/CMakeLists.txt
R mlir/lib/Conversion/RaiseWasm/RaiseWasmMLIR.cpp
M mlir/lib/Dialect/WasmSSA/IR/WasmSSAOps.cpp
R mlir/test/Conversion/RaiseWasm/wasm-abs-to-math-abs.mlir
R mlir/test/Conversion/RaiseWasm/wasm-add-to-arith-add.mlir
R mlir/test/Conversion/RaiseWasm/wasm-and-to-arith-and.mlir
R mlir/test/Conversion/RaiseWasm/wasm-ceil-to-math-ceil.mlir
R mlir/test/Conversion/RaiseWasm/wasm-clz-to-math-clz.mlir
R mlir/test/Conversion/RaiseWasm/wasm-const-to-arith-const.mlir
R mlir/test/Conversion/RaiseWasm/wasm-convert-to-arith-tofp.mlir
R mlir/test/Conversion/RaiseWasm/wasm-copysign-to-math-copysign.mlir
R mlir/test/Conversion/RaiseWasm/wasm-ctz-to-math-ctz.mlir
R mlir/test/Conversion/RaiseWasm/wasm-demote-to-arith-trunc.mlir
R mlir/test/Conversion/RaiseWasm/wasm-div-to-arith-div.mlir
R mlir/test/Conversion/RaiseWasm/wasm-floor-to-math-floor.mlir
R mlir/test/Conversion/RaiseWasm/wasm-func-to-func.mlir
R mlir/test/Conversion/RaiseWasm/wasm-global-to-memref-global.mlir
R mlir/test/Conversion/RaiseWasm/wasm-local-to-memref.mlir
R mlir/test/Conversion/RaiseWasm/wasm-max-to-arith-maximumf.mlir
R mlir/test/Conversion/RaiseWasm/wasm-min-to-arith-minimumf.mlir
R mlir/test/Conversion/RaiseWasm/wasm-mul-to-arith-mul.mlir
R mlir/test/Conversion/RaiseWasm/wasm-neg-to-arith-neg.mlir
R mlir/test/Conversion/RaiseWasm/wasm-or-to-arith-or.mlir
R mlir/test/Conversion/RaiseWasm/wasm-popcnt-to-math-ctpop.mlir
R mlir/test/Conversion/RaiseWasm/wasm-promote-to-arith-ext.mlir
R mlir/test/Conversion/RaiseWasm/wasm-reinterpret-to-arith-bitcast.mlir
R mlir/test/Conversion/RaiseWasm/wasm-rem-to-arith-rem.mlir
R mlir/test/Conversion/RaiseWasm/wasm-shl-to-arith-shl.mlir
R mlir/test/Conversion/RaiseWasm/wasm-shr_s-to-arith-shrs.mlir
R mlir/test/Conversion/RaiseWasm/wasm-shr_u-to-arith-shru.mlir
R mlir/test/Conversion/RaiseWasm/wasm-sqrt-to-math-sqrt.mlir
R mlir/test/Conversion/RaiseWasm/wasm-sub-to-arith-sub.mlir
R mlir/test/Conversion/RaiseWasm/wasm-trunc-to-math-trunc.mlir
R mlir/test/Conversion/RaiseWasm/wasm-wrap-to-arith-trunc.mlir
R mlir/test/Conversion/RaiseWasm/wasm-xor-to-arith-xor.mlir
Log Message:
-----------
Revert "[MLIR][WASM] Introduce the RaiseWasmMLIRPass to convert WasmSSA MLIR to core dialects" (#204917)
Reverts llvm/llvm-project#164562
Co-authored-by: Luc Forget <lforg37 at users.noreply.github.com>
Commit: ec3b4186a0f5bd182692721d14ed50af1f4af47d
https://github.com/llvm/llvm-project/commit/ec3b4186a0f5bd182692721d14ed50af1f4af47d
Author: A. Jiang <de34 at live.cn>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
A libcxx/test/std/language.support/support.types/byte.compile.pass.cpp
R libcxx/test/std/language.support/support.types/byte.pass.cpp
M libcxx/test/std/language.support/support.types/byteops/and.assign.pass.cpp
M libcxx/test/std/language.support/support.types/byteops/and.pass.cpp
R libcxx/test/std/language.support/support.types/byteops/enum_direct_init.pass.cpp
R libcxx/test/std/language.support/support.types/byteops/lshift.assign.compile.fail.cpp
M libcxx/test/std/language.support/support.types/byteops/lshift.assign.pass.cpp
R libcxx/test/std/language.support/support.types/byteops/lshift.compile.fail.cpp
M libcxx/test/std/language.support/support.types/byteops/lshift.pass.cpp
M libcxx/test/std/language.support/support.types/byteops/not.pass.cpp
M libcxx/test/std/language.support/support.types/byteops/or.assign.pass.cpp
M libcxx/test/std/language.support/support.types/byteops/or.pass.cpp
R libcxx/test/std/language.support/support.types/byteops/rshift.assign.compile.fail.cpp
M libcxx/test/std/language.support/support.types/byteops/rshift.assign.pass.cpp
R libcxx/test/std/language.support/support.types/byteops/rshift.compile.fail.cpp
M libcxx/test/std/language.support/support.types/byteops/rshift.pass.cpp
R libcxx/test/std/language.support/support.types/byteops/to_integer.compile.fail.cpp
M libcxx/test/std/language.support/support.types/byteops/to_integer.pass.cpp
M libcxx/test/std/language.support/support.types/byteops/xor.assign.pass.cpp
M libcxx/test/std/language.support/support.types/byteops/xor.pass.cpp
Log Message:
-----------
[libc++][test] Rewrite tests for `std::byte` (#204116)
Previously, test files for `std::byte` were less than ideal. There were
many issues.
- `byte.pass.cpp` tested many properties which hold for enumeration
types, but failed to verity that `std::byte` is a scoped enumeration
type. Also, it was not a `.compile.pass.cpp`.
- `enum_direct_init.pass.cpp` seemed to be completely redundant.
- It was not tested that compound assignment operators return references
to their left operands.
- Return types of operators were rarely tested.
- Constraints of functions were not tested using SFINAE techniques.
- Test cases were not made run in both constant evaluation and at run
time in the conventional way.
This patch
- rewrites tests for `std::byte` to address these issues,
- expands test coverage for integer types listed in `type_algorithms.h`,
and
- updates lit comments to new-style `// REQUIRES: std-at-least-c++17`.
Commit: 9f578bc595ca7c1a5ce35b17c483fd6c557d11ef
https://github.com/llvm/llvm-project/commit/9f578bc595ca7c1a5ce35b17c483fd6c557d11ef
Author: Damian Höster <damian.hoester at posteo.de>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Format/UnwrappedLineParser.h
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Reset `Line->IsModuleOrImportDecl` in `addUnwrappedLine` (#204565)
The `IsModuleOrImportDecl` flag was not reset in `addUnwrappedLine`.
Since the parser recycles the `Line` object, this flag remained `true`
for all subsequent lines in the file, which disabled wrapping
(`CanBreakBefore` in `TokenAnnotator.cpp`) for expression-level
constructs after any C++20 module or import statement, causing some
formatting rules to not be applied in places. This patch fixes the issue
by resetting the flag to `false`.
---------
Co-authored-by: Owen Pan <owenpiano at gmail.com>
Commit: f21080724d2067b5acf01893bf2d544b49239161
https://github.com/llvm/llvm-project/commit/f21080724d2067b5acf01893bf2d544b49239161
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
Log Message:
-----------
[LoopCacheAnalysis] Drop isLoopSimplifyForm check (NFCI) (#204822)
This patch removes the isLoopSimplifyForm() check from
LoopCacheAnalysis. This check was problematic when I tried migrating
LoopCachePrinterPass from a loop pass to a function pass (i.e.,
#204807), because the former applies the loop-simplify pass via
FunctionToLoopPassAdapter, whereas the latter does not. I believe this
check is meaningless because the analysis doesn't pay attention to the
details of the actual loop structure. So this change should not affect
the behavior of the pass.
Commit: 342de06a7692e76a23b30761e576e58e675b65d8
https://github.com/llvm/llvm-project/commit/342de06a7692e76a23b30761e576e58e675b65d8
Author: Hazarath <92698778+hazarathayya at users.noreply.github.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/Reassociate.cpp
A llvm/test/Transforms/Reassociate/reassociate-distribute.ll
Log Message:
-----------
[Reassociate] Distribute multiply over add to enable factorization (#178201)
### This patch improves ReassociatePass to handle patterns like:
(x*C1) - ((y+x)*C2) → x*(C1-C2) - (y*C2)
The optimization consists of two changes:
1. Distribution pre-processing: Transform (A+B)*C → A*C + B*C when:
- The add has exactly one use (avoids code bloat)
- Both add operands are non-constant (avoids unprofitable cases)
This exposes common factors that would otherwise be hidden inside
the addition, enabling subsequent factorization.
2. Factorization heuristic: Prefer extracting non-constant factors
(Instructions/Arguments) over constant factors when occurrence
counts are equal. This enables better constant folding opportunities.
Note: undef is excluded from this preference to maintain existing
test expectations.
Example transformation:
Input IR:
```
%add = add nsw i16 %y, %x
%mul1 = mul nsw i16 %x, 8697
%mul2 = mul nsw i16 %add, 6436
%sub = sub nsw i16 %mul1, %mul2
ret i16 %sub
```
After distribution:
```
%1 = mul nsw i16 %y, 6436
%2 = mul nsw i16 %x, 6436
%3 = add nsw i16 %1, %2
%sub = sub nsw i16 %mul1, %3
```
After reassociation (factors %x, folds 8697-6436):
```
%neg = mul i16 %y, -6436
%reass.mul = mul i16 %x, 2261
%result = add i16 %reass.mul, %neg
```
The transformation preserves nsw/nuw flags during distribution.
Note that flags may be dropped by subsequent reassociation passes;
comprehensive flag preservation can be addressed in future work.
Fixes #167190
Commit: 56262f29ea23c50e82640c8bdc50cc17e9498688
https://github.com/llvm/llvm-project/commit/56262f29ea23c50e82640c8bdc50cc17e9498688
Author: Tom Stellard <tstellar at redhat.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M .github/workflows/new-prs.yml
Log Message:
-----------
workflows/new-prs: Use github-automation container (#204706)
Commit: 68079bb518dcdaec15ee3b202f45701d3a78fa91
https://github.com/llvm/llvm-project/commit/68079bb518dcdaec15ee3b202f45701d3a78fa91
Author: Jan Schultke <me at eisenwave.net>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Builtins.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/CodeGen/builtins-elementwise-math.c
M clang/test/Sema/builtins-elementwise-math.c
Log Message:
-----------
[clang] Implement `__builtin_elementwise_pext` and `__builtin_elementwise_pdep` (#204296)
Closes #204126
This PR adds `__builtin_elementwise_pext` to emit `@llvm.pext` and `__builtin_elementwise_pdep` to emit `@llvm.pdep`.
Commit: 9019eff661e2c0e93f2389cf25a59fd24b0dd18a
https://github.com/llvm/llvm-project/commit/9019eff661e2c0e93f2389cf25a59fd24b0dd18a
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/test/Transforms/InstCombine/scmp.ll
M llvm/test/Transforms/InstCombine/select-to-cmp.ll
M llvm/test/Transforms/InstCombine/ucmp.ll
Log Message:
-----------
[InstCombine] Fold trunc scmp/ucmp -> scmp/ucmp with the target type being what we truncate (#196847)
I don't think I need an alive2 for this, since this is basically a
tautology/self-definition.
Commit: d186503ccc7ad93f695f60302c5def5efc3ac2dd
https://github.com/llvm/llvm-project/commit/d186503ccc7ad93f695f60302c5def5efc3ac2dd
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
Log Message:
-----------
[clang][bytecode][NFC] Remove dead code (#204910)
Unions can't have base classes so this is never used.
Commit: 465c904272709002665bd86765d8f11dc9390a98
https://github.com/llvm/llvm-project/commit/465c904272709002665bd86765d8f11dc9390a98
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineX86ShufflesRecursively - delay widening shuffle inputs. NFC. (#204931)
Perform resolveTargetShuffleInputsAndMask earlier as widening shouldn't
merge any inputs (we canonicalize small shuffle inputs earlier).
We should be able to move the widenSubVector calls inside
combineX86ShuffleChain in a future commit, but this patch should be NFC.
Commit: e26ff5491b91c66bb27bfd2b2ca8afe76bb7489d
https://github.com/llvm/llvm-project/commit/e26ff5491b91c66bb27bfd2b2ca8afe76bb7489d
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
Log Message:
-----------
[InstCombine] Remove fold with OneUse as there is fold without the check (NFC) (#204925)
Commit: 2ec6f2870e13bb8807360f2278108b7d5240fe40
https://github.com/llvm/llvm-project/commit/2ec6f2870e13bb8807360f2278108b7d5240fe40
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/test/Transforms/InstCombine/set.ll
Log Message:
-----------
[InstCombine] Fold sext(and/or/xor(trunc nsw x), y) -> and/or/xor(sext(y), x) (#204928)
Proof: https://alive2.llvm.org/ce/z/ntVE_8
Commit: f6296fb4507e80f507024a28a21654e12543b62e
https://github.com/llvm/llvm-project/commit/f6296fb4507e80f507024a28a21654e12543b62e
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/test/Transforms/InstCombine/zext.ll
Log Message:
-----------
[InstCombine] Fold zext(and/or/xor(trunc nuw x), y) -> and/or/xor(zext(y), x) (#204927)
proof: https://alive2.llvm.org/ce/z/ZORvJ6
Commit: b2c0c48595ab840c5b949d871302b0d1186acf53
https://github.com/llvm/llvm-project/commit/b2c0c48595ab840c5b949d871302b0d1186acf53
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/add.ll
M llvm/test/Transforms/InstCombine/and-or-icmps.ll
M llvm/test/Transforms/InstCombine/or.ll
Log Message:
-----------
[InstCombine] Fold or (ashr X, BW-1), zext (icmp ne|sgt X, 0) to scmp(X, 0) (#196828)
Recognize the bitwise signum encoding
or (ashr X, BW-1), zext (icmp ne X, 0) --> llvm.scmp(X, 0)
or (ashr X, BW-1), zext (icmp sgt X, 0) --> llvm.scmp(X, 0)
Alive2: https://alive2.llvm.org/ce/z/UZ7a7Q
Commit: bae51e7ffb767d08d684290d34515b91f2cbb2ed
https://github.com/llvm/llvm-project/commit/bae51e7ffb767d08d684290d34515b91f2cbb2ed
Author: Arda Serdar Pektezol <arda at pektezol.dev>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/IR/Instructions.cpp
M llvm/test/Transforms/InstCombine/alloca-big.ll
Log Message:
-----------
[IR] handle oversized constant alloca counts in getAllocationSize (#204540)
AllocaInst::getAllocationSize() unconditionally calls getZExtValue() for
array allocas, which asserts when the constant element count is wider
than 64 bits.
Use tryZExtValue() when reading the constant array size instead. If the
count cannot be represented in uint64_t, return std::nullopt rather than
asserting, matching the existing contract.
Fixes #203519
Commit: c888371ff0a3e10f8472676dc992f4347fca58d9
https://github.com/llvm/llvm-project/commit/c888371ff0a3e10f8472676dc992f4347fca58d9
Author: player <playerc at msn.cn>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M clang-tools-extra/clangd/CompileCommands.cpp
Log Message:
-----------
[clangd] Look for resource-dir relative to detected compiler path as a fallback (#203332)
If the standard resource directory (which is searched for relative to the clangd
executable) does not exist, look for one relative to the detected compiler as a
fallback. This handles some packaging schemes where clangd and clang are
installed in different prefixes and the resource directory is only located in the
latter.
Also print an error message to the log if the fallback didn't find an existing
directory either.
Commit: 0c3c664f32d5b15ae542ed66fa52ebf86974ccaa
https://github.com/llvm/llvm-project/commit/0c3c664f32d5b15ae542ed66fa52ebf86974ccaa
Author: Adam Scott <88979030+as4230 at users.noreply.github.com>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/PhaseOrdering/X86/madd.ll
M llvm/test/Transforms/PhaseOrdering/X86/sad.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
M llvm/test/Transforms/VectorCombine/AArch64/partial-reduce-crash.ll
M llvm/test/Transforms/VectorCombine/X86/extract-binop-inseltpoison.ll
M llvm/test/Transforms/VectorCombine/X86/extract-binop.ll
A llvm/test/Transforms/VectorCombine/X86/shuffle-chain-reduction-subvector.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-chain-reduction-umin.ll
M llvm/test/Transforms/VectorCombine/fold-shuffle-chains-to-reduce.ll
Log Message:
-----------
[VectorCombine] Add subvector reduction support to foldShuffleChainsToReduce (#199872)
Extends foldShuffleChainsToReduce to recognise subvector reductions
where the chain narrows through shuffles before extracting lane 0.
The matcher tracks per output lane attribution as the chain is walked.
Each lane carries a per source bitmask of contributing source lanes plus
a poison flag. Shuffles permute these records. Binops union them. At the
extract, lane 0's bitmasks rebuild the reduction as one or more partial
reduce intrinsics. The walk is capped at 32 chain nodes.
Also added new test file with 11 tests:
| Test | Reason |
| ------------------------------------------------------ |
--------------------------------------------- |
| `_add_v4i32`, `_add_v8i16`, `_add_v16i8`, `_add_v64i8` | basic
subvector reductions across types/sizes |
| `_mul_v16i8` | non-add reduction |
| `_swapped_v8i16` | root operand swap |
| `_deinterleave_v8i16` | non-contiguous shuffle masks |
| `_multishuffle_accumulator_v8i32` | reduction with multiple shuffle
leaves |
| `_multisource_full_plus_scalar_v4i32` | multi-source reduction chain |
| `_neg_overlapping_masks_v8i16` | overlapping-mask reject case |
| `_neg_different_sources_v8i16` | non-profitable fold reject |
A few patterns the old matcher didn't fold get caught by the new one. In
`extract-binop.ll`, `ext_ext_partial_add_reduction_and_extra_add_v4i32`
mixes two source vectors. The old matcher walked a single chain
bottom-up assuming one source at the leaves so it bailed. The partial
reduction patterns in `load-extractelement-scalarization.ll` fold for
the same reason.
Fixes #197919
---------
Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>
Commit: 2c022e8d946619602e967924a7291f197119e8a5
https://github.com/llvm/llvm-project/commit/2c022e8d946619602e967924a7291f197119e8a5
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/IR/Verifier.cpp
M llvm/test/CodeGen/AArch64/lower-range-metadata-func-call.ll
M llvm/test/CodeGen/X86/legalize-vec-assertzext.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fma.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maxnum.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minnum.ll
M llvm/test/Verifier/nofpclass-metadata.ll
A llvm/test/Verifier/nonnull-metadata.ll
R llvm/test/Verifier/nonnull_metadata.ll
A llvm/test/Verifier/noundef-metadata.ll
R llvm/test/Verifier/range-1.ll
A llvm/test/Verifier/range-metadata.ll
M llvm/test/tools/llubi/metadata.ll
Log Message:
-----------
[Verifier] Only accept noundef metadata on loads and update metadata tests (#204922)
noundef metadata has been accepted everywhere so far, which seems to be
an oversight. This patch rejects it everywhere except for load
instructions, which seem to be the only ones where it's supposed to be
supported. The other metadata tests are also updated so they are
somewhat similar to each other.
Commit: cd532fe7fbcb72b6ca7a73f15cc8cb0023e7a9de
https://github.com/llvm/llvm-project/commit/cd532fe7fbcb72b6ca7a73f15cc8cb0023e7a9de
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/LoopCacheAnalysis.h
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/LoopnestFixedSize.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost-m32.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/loads-store.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/matmul.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/matvecmul.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/multi-store.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/single-store.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/stencil.ll
M llvm/test/Analysis/LoopCacheAnalysis/compute-cost.ll
M llvm/test/Analysis/LoopCacheAnalysis/interchange-cost-beneficial.ll
M llvm/test/Analysis/LoopCacheAnalysis/interchange-refcost-overflow.ll
M llvm/test/Analysis/LoopCacheAnalysis/partially-perfect-nest.ll
M llvm/utils/UpdateTestChecks/common.py
Log Message:
-----------
[LoopCacheAnalysis] Generate tests by update_analyze_test_checks.py (#204807)
Since loop interchange has been enabled in the default pipeline,
development on LoopCacheAnalysis, which is used by LoopInterchange, is
becoming more active. So I think it's a good time to support automatic
test generation for LoopCacheAnalysis.
This patch does two things. First, it changes LoopCachePrinterPass from
a loop pass to a function pass to make it possible to use
update_analyze_test_checks.py. Second, it rewrites all the CHECK
directives in the existing LoopCacheAnalysis tests using the script.
Commit: 6619aa70071db7d3a589fe50474e19c58dbca8f9
https://github.com/llvm/llvm-project/commit/6619aa70071db7d3a589fe50474e19c58dbca8f9
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUBarrierLatency.cpp
A llvm/test/CodeGen/AMDGPU/fence-barrier-latency.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
Log Message:
-----------
[AMDGPU] Use SchedModel latencies for Fence barrier edges (#204657)
For memory->fence dependencies, this PR sets the latency of the edge to
the instr latency of the predecessor memory instruction.
During lowering of these fences, we insert the necessary waitcnts, and
we end up waiting for any outstanding memory op at these fences. Thus,
the latency of the edges should be based on latency of the associated
load/stores.
Commit: b9c334de33a9a0b5713b191f214de8c3c8990507
https://github.com/llvm/llvm-project/commit/b9c334de33a9a0b5713b191f214de8c3c8990507
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/insertvalue-reordered-operands.ll
Log Message:
-----------
[SLP] Fix scheduling crash for reordered insertvalue buildvector nodes
Insertvalue nodes keep scalars in program order but reorder operands, like
stores. Remap the operand lane via ReorderIndices for InsertValueInst (not
just StoreInst) in scheduling and the copyable helpers, fixing the
"Operand not found" assertion.
Fixes https://github.com/llvm/llvm-project/pull/200274#issuecomment-4753792761
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/204941
Commit: cb85dfeb3275dce8f00ab7bf18f6ef3734222069
https://github.com/llvm/llvm-project/commit/cb85dfeb3275dce8f00ab7bf18f6ef3734222069
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
A llvm/test/Transforms/LoopVectorize/shl-shift-amount-out-of-range-scev.ll
Log Message:
-----------
[VPlan] Skip shl->mul SCEV rewrite for out-of-range shift amounts. (#204921)
getSCEVExprForVPValue rewrites `shl x, c` as `x * (1 << c)` using
ScalarEvolution::getPowerOfTwo, which asserts that the power is less
than the type's bit width.
Only perform the rewrite when the shift amount is less than the
operand's bit width, to avoid assertion.
Commit: 18c1cbce6874a7341f357014befb66d4c11a04a9
https://github.com/llvm/llvm-project/commit/18c1cbce6874a7341f357014befb66d4c11a04a9
Author: Sungbin Jo <goranmoomin at daum.net>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp
M llvm/lib/ObjCopy/MachO/MachOWriter.cpp
A llvm/test/tools/llvm-objcopy/MachO/linkedit-alignment.test
M llvm/test/tools/llvm-objcopy/MachO/linkedit-order-1.test
M llvm/test/tools/llvm-objcopy/MachO/linkedit-order-2.test
M llvm/test/tools/llvm-objcopy/MachO/symbol-table.test
Log Message:
-----------
[llvm-objcopy][MachO] Align __LINKEDIT entries to pointer size (#203680)
Align Mach-O __LINKEDIT entries to the target pointer size when building
the tail layout. This matches the behavior of ld64 and lld-macho.
dyld on macOS 27 rejects loading dylibs with misaligned __LINKEDIT
entries.
See #203678 for details and the motivation of this fix.
AI Tool Use Disclosure:
Regarding the PR and the linked issue, I have personally wrote every
single part of the PR by myself, and have/ran/verified every single part
of the issue report as well without any AI tool usage.
I have used LLM-based coding agents only for debugging purposes, e.g. to
figure out why the dylib was not loading (from the original bug report),
and figuring out how to build, run, and test my local `llvm-objcopy`.
Commit: a891d7b38b31fd7e229f88c2555184713935ea60
https://github.com/llvm/llvm-project/commit/a891d7b38b31fd7e229f88c2555184713935ea60
Author: Daniel Rodríguez Troitiño <danielrodriguez at meta.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp
M llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.h
M llvm/lib/ObjCopy/MachO/MachOObjcopy.cpp
Log Message:
-----------
[llvm-objcopy][MachO] Use alignToPowerOf2 instead of alignTo (#204033)
During the review of #203680 I noticed that Mach-O objcopy files seems
to use `alignTo` and import `Alignment.h` to align some offsets to page
boundaries and similar requirements. However, the `alignTo` in
`Alignment.h`, while being intended for powers of 2, requires using an
alignment of type `llvm::Align`, and needs explicit conversion from
`uint64_t` and similar. Single `Alignment.h` includes `MathExtras.h`,
the `alignTo` being invoked ends up being a generic `alignTo` that does
not require powers of 2, and perform divisions and multiplications.
While some of those might be optimized by the compiler into efficient
power of 2 operations, there's an explicit `alignToPowerOf2` version
that is optimized and asserts the alignment is a power of 2 (with
asserts enabled). Since all the alignments should be power of 2 for the
Mach-O binary format, change from `alignTo` to `alignToPowerOf2` to make
the fact more visible (and get the extra safety net of the assertions).
As expected, the test suite of objcopy doesn't show any regressions, but
I have not done a performance benchmark around this either.
Commit: d0c27761d4f1e25d1ab4b672d23bc7e46f517bcd
https://github.com/llvm/llvm-project/commit/d0c27761d4f1e25d1ab4b672d23bc7e46f517bcd
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/test/Analysis/BasicAA/phi-aa.ll
M llvm/test/Analysis/BasicAA/phi-and-select.ll
M llvm/test/Analysis/BasicAA/recphi.ll
Log Message:
-----------
[BasicAA] Add additional tests with GEPs with phi/select pointer ops (NFC) (#204947)
Commit: 5502491546363465ef2b58dbf5821a67a3be6164
https://github.com/llvm/llvm-project/commit/5502491546363465ef2b58dbf5821a67a3be6164
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-with-wide-ops-and-casts.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-with-wide-ops.ll
Log Message:
-----------
[VPlan] Properly check predicates and types in canNarrowOps. (#204948)
Update canNarrowOps to properly check the types of all members match.
Similarly, for recipes with predicates, the predicates must match.
Commit: 3c5f0c2d3e00a22a275f404bac29ce62c69d95d5
https://github.com/llvm/llvm-project/commit/3c5f0c2d3e00a22a275f404bac29ce62c69d95d5
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-memory-op-decisions.ll
Log Message:
-----------
[VPlan] Add memory op decision test for scalarizing loads. (NFC) (#204949)
VPlan printing tests for
https://github.com/llvm/llvm-project/pull/196842
Commit: 959f069f442d75dd7c365cb608140693e834b93e
https://github.com/llvm/llvm-project/commit/959f069f442d75dd7c365cb608140693e834b93e
Author: jofrn <jo7frn1 at gmail.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/X86/atomic-load-store.ll
Log Message:
-----------
[SelectionDAG] Keep split vector atomic store value in a vector register (#201566)
When the value of an ATOMIC_STORE has a vector type whose legalization
action is split (e.g. <4 x half>/<4 x bfloat> on X86 without F16C),
SplitVecOp_ATOMIC_STORE bitcast the value straight to a scalar integer
spanning the memory width. For a split vector that bitcast is expanded
element by element, reassembling the value in GPRs (a long pextrw/shl/or
sequence) before the store.
Instead, keep the value in a vector register when a legal vector form
exists: reinterpret it as a same-shaped integer-element vector (an FP
element type may have no legal vector form, e.g. bfloat on SSE2, while
the integer-of-element-size form does), widen that to a legal vector,
and extract the low integer element of the memory width. This issues the
store directly from a vector register (a single MOVQ/MOVD on X86),
matching the widen-path codegen already produced on AVX targets. Falls
back to the scalar bitcast when no suitable legal vector type exists.
Stacked on top of https://github.com/llvm/llvm-project/pull/197861; and
below of #197862.
Commit: 61d601e796beef1b891ca437dd3167fbabad4451
https://github.com/llvm/llvm-project/commit/61d601e796beef1b891ca437dd3167fbabad4451
Author: Zach Goldthorpe <Zach.Goldthorpe at amd.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
Log Message:
-----------
[AMDGPU][VOPD] Cache load reachability checks in VOPDpairing (#204854)
#201930 causes significant compilation time regression when building
ROCm mathlibs.
Major regressions are caused by repeated queries to `DAG->IsReachable`
to detect possible scalarisation of loads when fusing a pair of
VOPD-capable instructions.
This patch caches the set of reachable loads for every potentially
hazardous load instruction to avoid the need to invoke
`DAG->IsReachable` at all.
Commit: afac572cd4c58b02ebe9a72c04f63a91dccc7901
https://github.com/llvm/llvm-project/commit/afac572cd4c58b02ebe9a72c04f63a91dccc7901
Author: owenca <owenpiano at gmail.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M clang/test/CMakeLists.txt
Log Message:
-----------
[clang] Add clang-format-check-format instead to CLANG_TEST_DEPS (#204908)
Ensure that clang-format doesn't break the existing format of its own
source.
Reverts #199169 and #199638.
Commit: ec56065709fe771c90da191f107126ac71bc09ad
https://github.com/llvm/llvm-project/commit/ec56065709fe771c90da191f107126ac71bc09ad
Author: Tom Stellard <tstellar at redhat.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M .github/workflows/new-prs.yml
Log Message:
-----------
workflows/new-prs: Remove obsolete code (#204955)
This was left over after 57e4352de0d2617bae1656dc2e2b3ca430e83c4c and
causing the jobs to fail.
Commit: 9d6c686a8a77e8c5ff9b42803c1bf07bcc1b66b3
https://github.com/llvm/llvm-project/commit/9d6c686a8a77e8c5ff9b42803c1bf07bcc1b66b3
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M orc-rt/include/orc-rt/Session.h
M orc-rt/lib/executor/Session.cpp
Log Message:
-----------
[orc-rt] Sink Session::sendWrapperResult into Session.cpp. NFC. (#204956)
This function is never called inline (except by Session::wrapperReturn,
which is also in Session.cpp), so there's no need for it to be in the
header.
Commit: 7376a706150289cf60fb3648e75e909ab6e86f68
https://github.com/llvm/llvm-project/commit/7376a706150289cf60fb3648e75e909ab6e86f68
Author: Tamir Duberstein <tamird at gmail.com>
Date: 2026-06-20 (Sat, 20 Jun 2026)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_platform.h
Log Message:
-----------
[tsan] fit Go/s390x mapping under QEMU (#204503)
QEMU linux-user first tries guest_base=0. In that identity-mapped mode,
fixed guest mappings use the same host addresses. On an x86-64 host
with four-level page tables, the Go/s390x meta shadow starts at
144 TiB, beyond the 128 TiB userspace limit, and its mmap fails with
ENOMEM during TSan initialization.
Move the meta shadow down by 32 TiB to
[0x700000000000, 0x780000000000), restoring the 16 TiB gap after the
shadow and placing all Go/s390x TSan regions below 2^47. Correct the
mapping comment's shadow size and ratio.
Failure report and native s390x comparison:
https://github.com/golang/go/issues/67881
QEMU identity guest-base selection:
https://github.com/qemu/qemu/blob/v10.2.3/linux-user/elfload.c#L1036-L1042
QEMU guest-to-host address translation:
https://github.com/qemu/qemu/blob/v10.2.3/include/user/guest-host.h#L46-L50
QEMU fixed-mapping implementation:
https://github.com/qemu/qemu/blob/v10.2.3/linux-user/mmap.c#L600-L628
x86-64 four-level paging documentation:
https://docs.kernel.org/arch/x86/x86_64/5level-paging.html
Commit: f42072ed8de552ce25b7a978c052acca6ab13246
https://github.com/llvm/llvm-project/commit/f42072ed8de552ce25b7a978c052acca6ab13246
Author: Jan Schultke <me at eisenwave.net>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M llvm/include/llvm/Support/KnownBits.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Support/KnownBits.cpp
A llvm/test/Analysis/ValueTracking/knownbits-pdep.ll
A llvm/test/Analysis/ValueTracking/knownbits-pext.ll
M llvm/unittests/Support/KnownBitsTest.cpp
Log Message:
-----------
[Analysis] Add `KnownBits` optimization for `pdep` and `pext` (#204223)
Fixes #204136
Commit: 8947e494f92e37d036ec22b79464368292eae177
https://github.com/llvm/llvm-project/commit/8947e494f92e37d036ec22b79464368292eae177
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/assume.ll
Log Message:
-----------
[InstCombine] Move alignment assumptions to the base of constant offset GEPs (#204602)
Commit: 71c2feb30426af725dd93297b9dccc18f8210a0e
https://github.com/llvm/llvm-project/commit/71c2feb30426af725dd93297b9dccc18f8210a0e
Author: shivaramaarao <58245296+shivaramaarao at users.noreply.github.com>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M flang/test/Integration/split-lto-unit-2.f90
Log Message:
-----------
Support for -fsplit-lto-unit option in flang driver (#204904)
Fix for buildbot failures in #202858
This commit fixes a regression introduced in commit
12aefe26cedd9a8f94546cc1f2be285cfddcc861 (Support for -fsplit-lto-unit
option in flang driver). When the compiler is built only for aarch64 one
of the testcase failed.
Added explicit check %if x86-registered-target for this testcase to
resolve the issue.
Commit: 441725611d0e166a144ac85665bf0ac3611851de
https://github.com/llvm/llvm-project/commit/441725611d0e166a144ac85665bf0ac3611851de
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
A llvm/test/Transforms/LoopVectorize/AArch64/vplan-native-outer-loop-wide-type.ll
Log Message:
-----------
[LV] Avoid zero-width VF in computeVPlanOuterloopVF. (#204918)
RegSize / WidestType may be 0 for types wider than the vector register
size. Clamp VF to at least 1 (scalar), to avoid a crash. This matches
inner loop behavior.
Commit: 9b36e4fbc789201228ca9b40524996e13959505a
https://github.com/llvm/llvm-project/commit/9b36e4fbc789201228ca9b40524996e13959505a
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M orc-rt/include/CMakeLists.txt
A orc-rt/include/orc-rt/QueueingRunner.h
R orc-rt/include/orc-rt/QueueingTaskDispatcher.h
M orc-rt/include/orc-rt/Session.h
R orc-rt/include/orc-rt/TaskDispatcher.h
A orc-rt/include/orc-rt/ThreadPoolRunner.h
R orc-rt/include/orc-rt/ThreadPoolTaskDispatcher.h
M orc-rt/lib/executor/CMakeLists.txt
R orc-rt/lib/executor/QueueingTaskDispatcher.cpp
M orc-rt/lib/executor/Session.cpp
R orc-rt/lib/executor/TaskDispatcher.cpp
A orc-rt/lib/executor/ThreadPoolRunner.cpp
R orc-rt/lib/executor/ThreadPoolTaskDispatcher.cpp
M orc-rt/unittests/BootstrapInfoTest.cpp
M orc-rt/unittests/CMakeLists.txt
M orc-rt/unittests/CommonTestUtils.h
M orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
M orc-rt/unittests/NativeDylibManagerTest.cpp
A orc-rt/unittests/QueueingRunnerTest.cpp
R orc-rt/unittests/QueueingTaskDispatcherTest.cpp
M orc-rt/unittests/SessionTest.cpp
M orc-rt/unittests/SimpleNativeMemoryMapSPSCITest.cpp
M orc-rt/unittests/SimpleNativeMemoryMapTest.cpp
A orc-rt/unittests/ThreadPoolRunnerTest.cpp
R orc-rt/unittests/ThreadPoolTaskDispatcherTest.cpp
Log Message:
-----------
[orc-rt] Replace TaskDispatcher with Session-supplied wrapper-runner. (#204965)
TaskDispatcher was only used to run wrapper-function calls that
originated from the controller. Replace it with a callable type:
Session::RunWrapperCall = move_only_function<void(
orc_rt_SessionRef, uint64_t, orc_rt_WrapperFunctionReturn,
orc_rt_WrapperFunction, WrapperFunctionBuffer)>
Each call carries an outstanding ManagedCodeTaskGroup token; the runner
must eventually invoke Fn (which calls Return) or call Return directly
to bail out, otherwise Session shutdown blocks indefinitely.
Clients can supply any callable that satisfies the contract above. The
new QueueingRunner and ThreadPoolRunner classes (replacing
QueueingTaskDispatcher and ThreadPoolTaskDispatcher, respectively) are
provided as off-the-shelf options.
Commit: a12b7af17a70f810ac3abe906b42930307efdaf0
https://github.com/llvm/llvm-project/commit/a12b7af17a70f810ac3abe906b42930307efdaf0
Author: Harishankar.1 <88716735+Harishankar14 at users.noreply.github.com>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/test/CodeGen/X86/bmi.ll
Log Message:
-----------
[X86] Select BLSI for i8 operands (#202344) (#204746)
Adds a tablegen pattern to select BLSI 32 for `and (neg x), x` at i8.
Fixes #202344
Commit: e0cc08dc1121126392df2b832ee060a60cca6dc3
https://github.com/llvm/llvm-project/commit/e0cc08dc1121126392df2b832ee060a60cca6dc3
Author: Akash Deo <AkashDeo2025 at u.Northwestern.edu>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Headers/avx512vlvnniintrin.h
M clang/lib/Headers/avx512vnniintrin.h
M clang/lib/Headers/avxvnniintrin.h
M clang/test/CodeGen/X86/avx512vlvnni-builtins.c
M clang/test/CodeGen/X86/avx512vnni-builtins.c
M clang/test/CodeGen/X86/avxvnni-builtins.c
Log Message:
-----------
[clang][x86] Add constexpr support for VNNI intrinsics (#190549)
Fixes #161340.
It adds constexpr support for VNNI
intrinsics by modifying their header files, their TableGen definitions,
how they're interpreted in InterpBuiltin.cpp and ExprConstant.cpp, and
adds unit tests in the headers' corresponding unit test files.
Commit: 4f3eb803343711c69e287da8a3272ab9449b53a9
https://github.com/llvm/llvm-project/commit/4f3eb803343711c69e287da8a3272ab9449b53a9
Author: Kern Handa <kernhanda at users.noreply.github.com>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
Log Message:
-----------
[Xtensa] Call isUInt<8> in range-check asserts (#204731)
`printOffset8m8_AsmOperand` and `getSelect_256OpValue` assert on
`isUInt<8>` without calling it, so the expression takes the function's
address and the range check never runs. This also trips
`-Werror,-Wpointer-bool-conversion` in builds with assertions enabled.
Pass the operand value so the bound is actually checked.
Commit: 3b46feb29499a3a43a166b36ce59bb6d49ec6682
https://github.com/llvm/llvm-project/commit/3b46feb29499a3a43a166b36ce59bb6d49ec6682
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
A llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-tail-folding.ll
Log Message:
-----------
[VPlan] Allow plain active lane mask in LastActiveLane verifier. (#204982)
Active lane masks are prefix masks. After simplifying the backedge, we
may end up with an active-lane-mask operand of LastActiveLane that does
not match the header mask predicate.
This fixes a verifier failure for the new test.
Commit: d6d4921b71e66540bcf582e41b202d533fbfe762
https://github.com/llvm/llvm-project/commit/d6d4921b71e66540bcf582e41b202d533fbfe762
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M llvm/utils/gn/build/write_cmake_config.gni
M llvm/utils/gn/secondary/llvm/lib/Transforms/IPO/BUILD.gn
Log Message:
-----------
[gn] Fix missing dependency (#204991)
This fixes an oversight in 27d344d36ecac364.
Commit: 6542d6dec0110452ede41f58938b4225f2d92a98
https://github.com/llvm/llvm-project/commit/6542d6dec0110452ede41f58938b4225f2d92a98
Author: David Green <david.green at arm.com>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/test/CodeGen/Thumb2/cmpxchg.mir
Log Message:
-----------
[ARM] Use lo tCMPr opcode when expanding CMP_SWAP (#204567)
We were always generating the tCMPhir even when the registers were both
low, which is an unpredictable instruction. Generating tCMPr instead
when both the registers are low.
Fixes #204519.
Commit: 48c0a2a551bc0116298a28e67c368b052469641d
https://github.com/llvm/llvm-project/commit/48c0a2a551bc0116298a28e67c368b052469641d
Author: AZero13 <gfunni234 at gmail.com>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/ucmp.ll
Log Message:
-----------
Revert "[Legalizer] Add support for promoting integers for s/ucmp (#198554) (#204978)
This reverts commit 91edd87a801fc5c9d12c7f5c6863edd50327cef8.
It was causing CI failures for Linux.
Commit: 47fd9ed9e958bf6df1d2fdaa50f70501271f27af
https://github.com/llvm/llvm-project/commit/47fd9ed9e958bf6df1d2fdaa50f70501271f27af
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
Log Message:
-----------
[gn build] Port 60a2d437bd04 (#204996)
Commit: d3b48ccccb3a826515e8bc0def3c9fa3b24880a2
https://github.com/llvm/llvm-project/commit/d3b48ccccb3a826515e8bc0def3c9fa3b24880a2
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
Log Message:
-----------
[gn build] Port a64928f267f3 (#204997)
Commit: a3230900a8809a45ac3952af186cf03d87183cfb
https://github.com/llvm/llvm-project/commit/a3230900a8809a45ac3952af186cf03d87183cfb
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
Log Message:
-----------
[VPlan] Add VPReplicateRecipe::getNumOperandsWithoutMask (NFC) (#205004)
Add a getNumOperandsWithoutMask helper to VPReplicateRecipe, mirroring
the existing VPInstruction::getNumOperandsWithoutMask, and use it to
replace some hand-rolled code.
Commit: 5bb5410d5b6d289a0a402ed4de052eb86e8bce5f
https://github.com/llvm/llvm-project/commit/5bb5410d5b6d289a0a402ed4de052eb86e8bce5f
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
Log Message:
-----------
[VPlan] Use pattern matching in isUsedByLoadStoreAddress (NFC) (#205008)
Replace the hand-written check for a VPReplicateRecipe load/store using
the value as its address with VPlan pattern matching via
m_Unary/m_Binary, which also handle masked recipes uniformly.
Commit: d1744cf76fbea0c407c5e793a380ffca4e5829be
https://github.com/llvm/llvm-project/commit/d1744cf76fbea0c407c5e793a380ffca4e5829be
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M orc-rt/include/CMakeLists.txt
A orc-rt/include/orc-rt/InProcessControllerAccess.h
M orc-rt/lib/executor/CMakeLists.txt
A orc-rt/lib/executor/InProcessControllerAccess.cpp
M orc-rt/unittests/CMakeLists.txt
A orc-rt/unittests/InProcessControllerAccessTest.cpp
Log Message:
-----------
[orc-rt] Add InProcessControllerAccess class. (#204976)
Adds a Session::ControllerAccess implementation for in-process JIT
setups, where the controller (LLVM-side) and the executor (orc-rt) live
in the same address space.
The two sides communicate through a refcounted C-ABI struct (Connection)
of function pointers. The C-only interface avoids assuming a common C++
ABI between the two sides and supports symmetric, graceful disconnect:
when either side calls Connection::Disconnect, in-flight cross-calls are
drained and pending continuations are surfaced as out-of-band errors,
after which further cross-calls fail cleanly.
This is intended to be paired with a new ExecutorProcessControl
implementation (llvm::orc::InProcessEPC) on the LLVM side, landing in a
follow-up commit. Unit tests are included covering construction without
connect, attach via Session, OnConnect-failure detach, successful and
out-of-band-error call cases, and the disconnect-drains-pending
behavior.
Commit: 2e87cf8c2b8ec6453ccfa7e448d5b33f1d71a2ca
https://github.com/llvm/llvm-project/commit/2e87cf8c2b8ec6453ccfa7e448d5b33f1d71a2ca
Author: jofrn <jo7frn1 at gmail.com>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/test/CodeGen/ARM/atomic-load-store.ll
M llvm/test/CodeGen/X86/atomic-load-store.ll
M llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
Log Message:
-----------
[AtomicExpand] Add bitcasts when expanding store atomic vector (#197862)
AtomicExpand fails for aligned `store atomic <n x T>` because it
does not find a compatible library call. This change adds appropriate
ptrtoint + bitcast so that the call can be lowered, mirroring the
load-side handling.
Store-side counterpart to #148900. Stacked on top of
https://github.com/llvm/llvm-project/pull/201566.
Commit: bc047d40eb3a17451af586a973d6a0e5e4f0fd5c
https://github.com/llvm/llvm-project/commit/bc047d40eb3a17451af586a973d6a0e5e4f0fd5c
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M orc-rt/include/orc-rt/ScopeExit.h
M orc-rt/lib/executor/AllocAction.cpp
M orc-rt/unittests/ScopeExitTest.cpp
Log Message:
-----------
[orc-rt]R Align scope-exit with LLVM (rename to scope_exit, use CTAD) (#205020)
This renames the orc_rt::detail::ScopeExitRunner class to
orc_rt::scope_exit and adds a class template argument deduction guide.
Commit: 75fbd791638e583eb5bf483906fb5a75b7ab18b0
https://github.com/llvm/llvm-project/commit/75fbd791638e583eb5bf483906fb5a75b7ab18b0
Author: Zhaoxuan Jiang <jiangzhaoxuan94 at gmail.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M lld/MachO/ICF.cpp
A lld/test/MachO/icf-safe-data-addrsig.s
Log Message:
-----------
[lld-macho] Relax safe ICF's keepUnique for ld64-coalesced data sections (#193125)
#188400 regressed data-section folding under --icf=safe{,_thunks}:
no-addrsig fallback, and over-broad compiler-emitted addrsig entries
covering data symbols, both caused markSymAsAddrSig to set keepUnique on
data sections, after which foldIdenticalSections refused to fold them.
ld64 coalesces __cfstring, __objc_classrefs and __objc_selrefs
unconditionally regardless of addrsig, so ignore keepUnique for them as
a workaround for the imprecise addrsig payload.
Commit: fc7bcd0ce864c631b7429f795249ea8cef6634a7
https://github.com/llvm/llvm-project/commit/fc7bcd0ce864c631b7429f795249ea8cef6634a7
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
M clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
Log Message:
-----------
[clang][RISCV] Handle VLS CC on unsupported primitive type in aggregate type (#203898)
We handled this for pure vector type before but missed the aggregate
types, this patch try to apply same mechanism on them where unsupported
vector types are converted to same size i8 vector types.
Commit: f571abab7c49a57cbb0fbaa6e5a0d65c39ab0c03
https://github.com/llvm/llvm-project/commit/f571abab7c49a57cbb0fbaa6e5a0d65c39ab0c03
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M clang/include/clang/Basic/riscv_sifive_vector.td
M clang/include/clang/Basic/riscv_vector_common.td
M clang/include/clang/Support/RISCVVIntrinsicUtils.h
M clang/lib/Support/RISCVVIntrinsicUtils.cpp
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
M clang/test/Sema/sifive-xsfmm.c
Log Message:
-----------
[llvm][RISCV] Revise xsfmm intrinsic interface. (#201527)
This patch does 2 things:
1. Change matmul interface to use newly defined OFP8 RVV types.
2. change all of matmul overloaded interfaces to only keep only widen
information and eliminate types information.
Commit: b68b8232ff72535ca1bb43832029cbb480bcbf3f
https://github.com/llvm/llvm-project/commit/b68b8232ff72535ca1bb43832029cbb480bcbf3f
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.td
M llvm/test/MC/Mips/mips64r6/invalid.s
Log Message:
-----------
[Mips] Fix Clang crashes when assembling MIPS64r6 LDPC with non-8-byte-aligned offset (#204320)
Fix #184959.
Commit: 72b891b75f85cd8be4ac125f36f1bc9a97c8e185
https://github.com/llvm/llvm-project/commit/72b891b75f85cd8be4ac125f36f1bc9a97c8e185
Author: Fan Mo <w007878 at hotmail.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaTemplate.cpp
M clang/test/SemaTemplate/instantiate-member-template.cpp
Log Message:
-----------
[clang] Avoid assertion on invalid member template specialization (#201506)
fixes #201490
It would be possible to have `PrevClassTemplate == false` when `SS` was
invalid.
Since it is already invalid, it would be safe to skip
`setMemberSpecialization` for `NewTemplate`. When the qualified scope
specifier is invalid, Sema may have already diagnosed the declaration
and marked it invalid. In that case there may be no previous class
template declaration, so the assertion is too strong. Avoid marking the
new declaration as a member specialization unless the previous class
template exists.
Commit: 6f98573ebdd8fa826aa841f48e6ed7e671900ecc
https://github.com/llvm/llvm-project/commit/6f98573ebdd8fa826aa841f48e6ed7e671900ecc
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M orc-rt/include/CMakeLists.txt
R orc-rt/include/orc-rt/ScopeExit.h
A orc-rt/include/orc-rt/scope_exit.h
M orc-rt/lib/executor/AllocAction.cpp
M orc-rt/unittests/CMakeLists.txt
R orc-rt/unittests/ScopeExitTest.cpp
A orc-rt/unittests/scope_exit-test.cpp
Log Message:
-----------
[orc-rt] Rename scope_exit header, add nodiscard attribute. (#205030)
The rename brings the scope_exit type's header name into alignment with
other ORC runtime snake_case types.
The [[nodiscard]] attribute should help to prevent accidental misuse of
the type.
Commit: 6a2128a933cbeaccfbff2b81cd9ee2ed80e6071d
https://github.com/llvm/llvm-project/commit/6a2128a933cbeaccfbff2b81cd9ee2ed80e6071d
Author: Kazu Hirata <kazu at google.com>
Date: 2026-06-21 (Sun, 21 Jun 2026)
Changed paths:
M llvm/include/llvm/ProfileData/SampleProfReader.h
M llvm/lib/ProfileData/SampleProfReader.cpp
Log Message:
-----------
[ProfileData] Lazy-load fixed-length MD5 name table (#202014)
When reading extensible binary format profiles with fixed-length MD5
name tables, the reader eagerly allocates and populates a
std::vector<FunctionId> to store the name table. This eager loading
is particularly wasteful when ProfileIsCS is false, as we populate the
entire name table just to support lookups during profile ingestion,
even though we may only use a subset of the profile. Since FunctionId
is 16 bytes on 64-bit systems, a name table containing 10 million MD5
hash values would consume 160MB of heap memory.
This patch implements lazy loading for the name table in extensible
binary format profiles when the fixed-length MD5 layout is used.
Specifically, this patch introduces SampleProfileNameTable to
encapsulate the name table representation, supporting both lazy
loading (pointing directly to the memory-mapped buffer) and eager
loading (using a vector). Eager loading is retained as a fallback for
layouts that do not support O(1) random access (such as
variable-length string tables).
The reader transitions between these modes using setLazy and
resetToEager. The getNameTable interface is updated to return an
iterator_range of SampleProfileNameTable::iterator, which reads the
MD5 values directly from the buffer on-demand when lazy-loaded.
- Heap consumption: Saves 16 bytes of heap memory for each name table
entry by avoiding the std::vector allocation.
- Compilation performance: Saves about 4% on ThinLTO pre-link and 10%
on ThinLTO backend on shared and non-shared profiles.
Commit: 1092b2bad2edf9ee11a9d8e641a22f5b46922a4c
https://github.com/llvm/llvm-project/commit/1092b2bad2edf9ee11a9d8e641a22f5b46922a4c
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/docs/AMDGPUAsyncOperations.rst
Log Message:
-----------
[AMDGPU] Improve the description of asyncmark semantics (#202579)
- The semantics of asyncmarks is now defined purely in terms of
sequences, without referring to the implementation.
- The examples incorrectly used (post)dominance. Fixed that with wording
in terms of asyncmark sequences.
Commit: 9f0b22c61153e8390e3eed74e4a9cf1160bd71fe
https://github.com/llvm/llvm-project/commit/9f0b22c61153e8390e3eed74e4a9cf1160bd71fe
Author: lrzlin <linrunze at loongson.cn>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll
Log Message:
-----------
[LoongArch] Custom scalar UINT_TO_FP and FP_TO_UINT with LSX instructions (#200901)
Using `vftintrz.lu.d` for converting scalar double/float values to
unsigned 64-bit integers, and `vffint.d.lu` vice versa.
Commit: de045d579791d978cce109f9348d20560e112d74
https://github.com/llvm/llvm-project/commit/de045d579791d978cce109f9348d20560e112d74
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M orc-rt/include/orc-rt/SimplePackedSerialization.h
Log Message:
-----------
[orc-rt] Tidy up some SPS tag types. NFC. (#205038)
Replaces class definitions with decls for tag types that don't need a
body, and moves the SPSError tag down to just above it's
serialization-traits class.
Commit: 15a3238566e799e3dd0e473672307712be8528e6
https://github.com/llvm/llvm-project/commit/15a3238566e799e3dd0e473672307712be8528e6
Author: Weiwen He <60433849+he-weiwen at users.noreply.github.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/extend-bool-vector-load.ll
Log Message:
-----------
[AArch64] Lower extends of boolean vector loads via scalar load (#203394)
Replace a `load <N x i1>` under a sext/zext with a scalar load +
bitcast, so the `combineToExtendBoolVectorInReg` helper can apply,
avoiding scalarization.
Optimisation for the SVE case with a predicate load to be added in a
follow up.
Fixes #200325
Commit: 6d66cc1e0e953e996048e93a9fa3e1c6b9a27642
https://github.com/llvm/llvm-project/commit/6d66cc1e0e953e996048e93a9fa3e1c6b9a27642
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M orc-rt/include/orc-rt/SimplePackedSerialization.h
M orc-rt/unittests/SimplePackedSerializationTest.cpp
Log Message:
-----------
[orc-rt] Add SPS serialization for ExecutorAddrRange. (#205041)
Allows SPS serialization to/from ExecutorAddrRange. This will be used in
upcoming patches for compact-unwind registration support.
Commit: 25e4057d49055a645dc6a51ae1f40ac647aaed5b
https://github.com/llvm/llvm-project/commit/25e4057d49055a645dc6a51ae1f40ac647aaed5b
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/AST/ByteCode/command-line-options.cpp
Log Message:
-----------
[clang] Respect `CLANG_USE_EXPERIMENTAL_CONST_INTERP` (#200716)
Seems like https://github.com/llvm/llvm-project/pull/199396 had no
effect at all, even though the patch itself seems pretty obvious.
Change the semantics of the command-line option to support
`-fno-experimental-constant-interpreter` as well. This way, the cmake
option can be used to set the default and the `-f`/`-fno-` command-line
options can be used to override the default behavior.
Commit: 64ad10fcda6952b78b81075d93a31364337ef8f4
https://github.com/llvm/llvm-project/commit/64ad10fcda6952b78b81075d93a31364337ef8f4
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/docs/AMDGPUExecutionSynchronization.rst
Log Message:
-----------
[AMDGPU][doc] Refactor Barrier Execution Model (#204566)
Remove everything that has to do with named barriers and put it in a
series of model extensions specific to /sbarrier/named-barriers.
I had to change a few things to make it fit, in summary:
Base Model:
- (~) Stylistic changes that make it easier to refer to specific rules.
Each rule is in a rubric instead of a bullet point.
- (-) No longer defines `barrier-mutually-exclusive`
- (-) No longer defines barrier `join` and any associated rule.
New named barrier extensions
- (+) Define "named barrier" as a sub-type of barrier objects. This
makes barrier-mutually-exclusive redundant.
- (+) Define barrier join as an op that can exclusively be done on
`named barrier objects`.
- (+) Define rules relating to join and its ordering with other barrier
operations
Following these changes, the target tables changed a bit as well.
Motive: Barrier _join_ + `barrier-mutually-exclusive` only ever makes
sense when considering named barriers in the ISA. They are an alien
concept to higher-level barrier abstractions.
_Join_ has especially been a pain to deal with and explain in the
general, high-level execution model. Kicking it down into an extension
allows to keep the base model much more concise. As the model extension
is defined w.r.t. the ISA, it's an appropriate place to surface
ISA-specific restrictions. For example we don't need to dance around the
concept of "each thread is a member of at most one named barrier" with
`barrier-mutually-exclusive`. We can just say it straight away when
describing the behavior of _join_ in the model extension.
Commit: ff0e4f0830f7913a3c66b28cafcc7dae2a6e10d6
https://github.com/llvm/llvm-project/commit/ff0e4f0830f7913a3c66b28cafcc7dae2a6e10d6
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64][NFC] Refactor duplicate code into getCmpOrCmnOperandFoldingProfit (#198981)
Commit: 5492d06d4fb99795b3b7247be374cdcb47f5ac03
https://github.com/llvm/llvm-project/commit/5492d06d4fb99795b3b7247be374cdcb47f5ac03
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/ConstantFolding.h
M llvm/include/llvm/Analysis/InstSimplifyFolder.h
M llvm/include/llvm/Analysis/InstructionSimplify.h
M llvm/include/llvm/Analysis/TargetFolder.h
M llvm/include/llvm/IR/ConstantFolder.h
M llvm/include/llvm/IR/IRBuilderFolder.h
M llvm/include/llvm/IR/NoFolder.h
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/IR/IRBuilder.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/CodeGen/VE/Scalar/atomic.ll
M llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll
M llvm/test/Transforms/IRCE/correct-loop-info.ll
M llvm/test/Transforms/IndVarSimplify/lcssa-preservation.ll
M llvm/test/Transforms/LoopUnroll/runtime-loop-multiexit-dom-verify.ll
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/trip-count-expansion-may-introduce-ub.ll
M llvm/test/Transforms/LoopVectorize/version-mem-access.ll
M llvm/test/Transforms/VectorCombine/AArch64/shuffle-of-intrinsics.ll
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
M llvm/test/Transforms/VectorCombine/RISCV/shuffle-of-intrinsics.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-intrinsics.ll
M polly/test/CodeGen/scop_expander_insert_point.ll
Log Message:
-----------
[IRBuilder] (Target|InstSimplify)-fold intrinsics (#204967)
Includes changes to guard against a nullptr TLI and Call. TargetFold or
InstSimplify fold in IRBuilderBase::CreateIntrinsic, in the same way we
fold in Create(Unary|Binary)Intrinsic.
Commit: 5951daf0f0cf67a0c75ced322c88aef86c9349de
https://github.com/llvm/llvm-project/commit/5951daf0f0cf67a0c75ced322c88aef86c9349de
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/narrow-interleave-groups-scalable-vf.ll
M llvm/test/Transforms/LoopVectorize/narrow-to-single-scalar-widen-gep-scalable.ll
M llvm/test/Transforms/LoopVectorize/scalable-assume.ll
M llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/scalable-iv-outside-user.ll
M llvm/test/Transforms/LoopVectorize/scalable-lifetime.ll
M llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll
M llvm/test/Transforms/LoopVectorize/scalable-noalias-scope-decl.ll
M llvm/test/Transforms/LoopVectorize/scalable-reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/vector-freeze.ll
M llvm/test/Transforms/LoopVectorize/vscale-cost.ll
Log Message:
-----------
[LV] Allow scalable VFs in `-force-vector-width` (and use in tests) (#204953)
This updates `-force-vector-width=VF` to accept scalable VFs. If a
scalable width is specified it is assumed the target supports scalable
vectors.
So for example, `-force-vector-width="vscale x 4"` works as a shorthand
for `-scalable-vectorization=always -force-target-supports-scalable-vectors=true -force-vector-width=4`.
Commit: e4df7391e49f0d1188d544f22db265ba9c30da3e
https://github.com/llvm/llvm-project/commit/e4df7391e49f0d1188d544f22db265ba9c30da3e
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/R600ISelLowering.h
M llvm/lib/Target/AMDGPU/SIMachineScheduler.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Log Message:
-----------
[AMDGPU] Remove stale declarations. NFC. (#205047)
Remove declarations of functions that are never defined. Also remove
unused field AMDGPUInstructionSelector::TM.
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: 0972d5c5c11a5dfd8c6a60ef018129157522e139
https://github.com/llvm/llvm-project/commit/0972d5c5c11a5dfd8c6a60ef018129157522e139
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M clang/include/clang/AST/Decl.h
Log Message:
-----------
[clang][NFC] Add LLVM_PREFERRED_TYPE to EvaluatedStmt bitfields (#205026)
Commit: 6be53ab5da701ca6939c818fbe8cdbb633ab2409
https://github.com/llvm/llvm-project/commit/6be53ab5da701ca6939c818fbe8cdbb633ab2409
Author: Nathan Corbyn <n_corbyn at apple.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/pr204118.mir
A llvm/test/CodeGen/AArch64/pr204118.ll
Log Message:
-----------
[AArch64][GISel] Remove hard-coded operand index from FCVT renderers (#204118)
Commit: 6daa02101815f4b2a6851fba8d8bedbfffd1e72c
https://github.com/llvm/llvm-project/commit/6daa02101815f4b2a6851fba8d8bedbfffd1e72c
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Check same input/output types in pooling ops verifier (#203565)
Adds a missing check to make sure the input and output types of pooling
ops have the same element type.
Commit: b0bf2c796915821d8bda7d136fe4eec62603454f
https://github.com/llvm/llvm-project/commit/b0bf2c796915821d8bda7d136fe4eec62603454f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M clang/docs/ConstantInterpreter.rst
Log Message:
-----------
[clang][bytecode] Update high-level documentation (#202596)
Commit: 3aeb6c1f3322b57fe102b7c87d8fd17f87454195
https://github.com/llvm/llvm-project/commit/3aeb6c1f3322b57fe102b7c87d8fd17f87454195
Author: Dmitriy Smirnov <dmitriy.smirnov at arm.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCompositeOps.td
M mlir/test/Dialect/SPIRV/IR/composite-ops.mlir
Log Message:
-----------
[mlir][spirv] Re-enable bf16/fp8 for vector composite ops (#204848)
Allow bf16 and fp8 vector element types in VectorExtractDynamic,
VectorInsertDynamic, and VectorShuffle.
Commit: b5dfea08588fc64b0ce5cea685b275ed3de400de
https://github.com/llvm/llvm-project/commit/b5dfea08588fc64b0ce5cea685b275ed3de400de
Author: Deepak Shirke <117824396+deepakshirkem at users.noreply.github.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMRegisterInfo.td
A llvm/test/CodeGen/ARM/machine-outliner-thunk-tcgpr.mir
Log Message:
-----------
[ARM] Fix Machine Outliner crash when tBLXr uses non-tcGPR register (#200684)
When the Machine Outliner selects MachineOutlinerThunk mode for a
sequence ending in tBLXr/tBLXr_noip, it converts the indirect call to
tTAILJMPr in buildOutlinedFrame. However tTAILJMPr requires its operand
to be in tcGPR (R0-R3, R12), while tBLXr accepts any GPR.
If the register is callee-saved (e.g. r4), the Machine Verifier crashes
with 'Illegal physical register for instruction'.
Fixes #188076
Commit: 0b1fe74f079fd330e4d4d85ce33b7f5702da1be7
https://github.com/llvm/llvm-project/commit/0b1fe74f079fd330e4d4d85ce33b7f5702da1be7
Author: Andrei Golubev <andrey.golubev at intel.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/Bufferization/IR/UnstructuredControlFlow.h
M mlir/lib/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/test/Dialect/Arith/one-shot-bufferize-memory-space-invalid.mlir
M mlir/test/Dialect/Bufferization/Transforms/test-one-shot-module-bufferize.mlir
M mlir/test/Dialect/ControlFlow/one-shot-bufferize-invalid.mlir
M mlir/test/Dialect/SCF/one-shot-bufferize-invalid.mlir
M mlir/test/lib/Dialect/Bufferization/TestOneShotModuleBufferize.cpp
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
Log Message:
-----------
[mlir][bufferization] Introduce reconcileBufferTypeMismatchFn hook (#202667)
This PR is the first part of the work that aims to allow customizations
in resolving mismatching buffer types.
Add a new bufferization hook that lets downstream bufferization
implementations define how to handle buffer mismatches that appear
during type inference in various upstream scenarios.
The hook is used as a fallback mechanism in several upstream operations.
For example, when bufferizing block signatures (scf.execute_region), and
resolving "branch" conflicts (scf.if, scfl.index_switch, scf.for,
arith.select).
The hook returns a valid buffer type when reconciliation succeeded;
failure indicates reconciliation failure and should be treated as
bufferization failure. The caller of the hook is expected to use the
returned buffer type. By default, a memref with fully-dynamic layout map
is returned (for unranked case, buffers are assumed to match).
---------
Co-authored-by: Dmitrii Makarenko <dmitrii.makarenko at intel.com>
Commit: 75440ed24c4e656cef53f0d2419a885eb7c908f7
https://github.com/llvm/llvm-project/commit/75440ed24c4e656cef53f0d2419a885eb7c908f7
Author: Nashe Mncube <nashe.mncube at arm.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
A llvm/test/tools/llvm-mca/AArch64/Cortex/A55-in-order-bottleneck-analysis.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/A57-direct-branch.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/A57-forwarding.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/A57-shifted-register.s
R llvm/test/tools/llvm-mca/AArch64/Cortex/direct-branch.s
R llvm/test/tools/llvm-mca/AArch64/Cortex/forwarding-A57.s
R llvm/test/tools/llvm-mca/AArch64/Cortex/in-order-bottleneck-analysis.s
R llvm/test/tools/llvm-mca/AArch64/Cortex/shifted-register.s
Log Message:
-----------
[NFC][AArch64][MCA] Rename A55/A57 mca tests (#204551)
Rename several llvm-mca tests for cortex-a55 and cortex-a57 to follow
the same pattern as the other testss
Commit: 9e8615f5268a4aa0298d615e6c79391174dcc8da
https://github.com/llvm/llvm-project/commit/9e8615f5268a4aa0298d615e6c79391174dcc8da
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/include/llvm/Support/ConvertUTF.h
M llvm/lib/Support/ConvertUTFWrapper.cpp
Log Message:
-----------
[NFC][llvm] simplify convertWideToUTF8 overloads (#204552)
Remove the C-String overload of `convertWideToUTF8` and convert the
`ArrayRef` one to use `std::wstring_view` in order to simplify the API.
Commit: 283514b070fd2ae647f56cf046ea74be15a887b1
https://github.com/llvm/llvm-project/commit/283514b070fd2ae647f56cf046ea74be15a887b1
Author: jpwang <jpwang at smail.nju.edu.cn>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
R llvm/test/tools/llvm-objcopy/ELF/compress-debug-sections-zstd-err.test
M llvm/test/tools/llvm-objcopy/ELF/compress-sections-within-segment.s
A llvm/test/tools/llvm-objcopy/ELF/compress-sections-zlib-unsupported.test
A llvm/test/tools/llvm-objcopy/ELF/compress-sections-zstd-unsupported.test
R llvm/test/tools/llvm-objcopy/ELF/decompress-debug-sections-unsupported-zlib.test
A llvm/test/tools/llvm-objcopy/ELF/decompress-sections-unsupported-zlib.test
A llvm/test/tools/llvm-objcopy/ELF/decompress-sections-unsupported-zstd.test
M llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
Log Message:
-----------
[llvm-objcopy] Report unsupported formats before compression (#202357)
Fixes #197877.
`llvm-objcopy --compress-sections` now reports unavailable compression
support while parsing the option, matching the behavior of
`--compress-debug-sections`. This avoids reaching compression code with
an unavailable format.
Decompression (either via `--decompress-debug-sections` or
`--compress-sections` with a `none` format) is still checked when the
relevant compressed section is processed, because the required
compression format is determined from the section header rather than
from the command-line option.
The `compress-sections-within-segment` test now requires zlib because
`--compress-sections .text=zlib` is diagnosed during option parsing when
zlib support is unavailable, before the test can reach the intended
"section within a segment" diagnostic.
Commit: 00086d64086043269c3ed1c15dc08f5b6d517292
https://github.com/llvm/llvm-project/commit/00086d64086043269c3ed1c15dc08f5b6d517292
Author: sipher <110331483+sipher-01 at users.noreply.github.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/test/Sema/LifetimeSafety/dangling-global.cpp
Log Message:
-----------
[LifetimeSafety] Add `LifetimeSafetyDanglingGlobalMoved` to strict diagnostic group (#204891)
Fixes #204213
`-Wlifetime-safety-dangling-global-moved` was defined but not included
in any parent diagnostic group, meaning `-Wlifetime-safety-all` and
`-Wno-lifetime-safety-all` had no effect on it.
`LifetimeSafetyDanglingGlobal` (the non-moved variant) was already
correctly placed under `LifetimeSafetyPermissive`. Following the same
pattern as the other `-moved` sibling warnings
(`DanglingFieldMoved`, `ReturnStackAddrMoved`, `UseAfterScopeMoved`),
this patch adds `LifetimeSafetyDanglingGlobalMoved` to
`LifetimeSafetyStrict`, which is part of the `lifetime-safety-all`
hierarchy.
Assisted-by: Claude (Anthropic) — used for learning and understanding
the codebase, not for generating code directly.
Commit: 192ef559fbfeeba2f9cc43252db3da1303e8f00b
https://github.com/llvm/llvm-project/commit/192ef559fbfeeba2f9cc43252db3da1303e8f00b
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
R llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.ll
R llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
Log Message:
-----------
AMDGPU/GlobalISel: Use AMDGPURegBankSelect + AMDGPURegBankLegalize by default (#203928)
AMDGPU/GlobalISel: Use AMDGPURegBankSelect + AMDGPURegBankLegalize by default
Change AMDGPU's default -global-isel pipeline to use AMDGPURegBankSelect
and AMDGPURegBankLegalize (previously -global-isel -new-reg-bank-select)
by default instead of RegBankSelect which uses AMDGPURegisterBankInfo.
-global-isel pipeline that used RegBankSelect/AMDGPURegisterBankInfo is
now deprecated, since it could not generate functionally correct code in
some cases involving divergent control flow and phis.
-new-reg-bank-select option does nothing and will be removed in followup
patch.
Delete regbankselect-mui.ll and regbankselect-mui-salu-float.ll, which
existed to compare the -global-isel vs -global-isel -new-reg-bank-select.
Temporarily disable a couple of tests that are missing AMDGPURegBankLegalize
support.
Commit: a2289b7336a299c2a5d6c4fb8b6fc074297acf88
https://github.com/llvm/llvm-project/commit/a2289b7336a299c2a5d6c4fb8b6fc074297acf88
Author: Raphael Isemann <rise at apple.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
R lldb/test/API/macosx/deny-attach/Makefile
R lldb/test/API/macosx/deny-attach/TestDenyAttach.py
R lldb/test/API/macosx/deny-attach/main.c
M lldb/tools/debugserver/source/MacOSX/MachProcess.mm
Log Message:
-----------
Revert "[lldb] Survive ptrace(PT_DENY_ATTACH) when attaching" (#205075)
Reverts llvm/llvm-project#204688
This breaks green dragon where the error message is `error: attach
failed: this is a non-interactive debug session, cannot get permission
to debug processes.`
Commit: 05d84fd3f92355d7f4a0c90ac4fd4229f3e19133
https://github.com/llvm/llvm-project/commit/05d84fd3f92355d7f4a0c90ac4fd4229f3e19133
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
Log Message:
-----------
[AMDGPU] Run update script on test. NFC (#204570)
There's some bogus whitespace in the generated CHECKs that changes when
touching the test.
Commit: 2a1f306515b67036a44b16e569a9f26f57520c54
https://github.com/llvm/llvm-project/commit/2a1f306515b67036a44b16e569a9f26f57520c54
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/dynamic-cast.cpp
Log Message:
-----------
[clang][bytecode] Add more sanity checks for pointers used in `dynamic_cast` (#205070)
Make sure it's initialized and that it points to a record.
Commit: b95e1e890c025ab4eee3583b7b1e2497991145db
https://github.com/llvm/llvm-project/commit/b95e1e890c025ab4eee3583b7b1e2497991145db
Author: Fangrui Song <i at maskray.me>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/include/llvm/Support/Allocator.h
M llvm/unittests/Support/AllocatorTest.cpp
Log Message:
-----------
[Allocator] Keep bump pointer at a minimum alignment (#203718)
Add a `MinAlign` template parameter (default 8, sizeof(size_t) on 64-bit
platforms) so that the common case `Alignment <= MinAlign` can skip
realigning `CurPtr`.
This is achieved by rounding each allocation's size up to MinAlign, so
the bump pointer stays MinAlign-aligned between allocations.
SpecificBumpPtrAllocator::DestroyAll() walks objects at a fixed
sizeof(T) stride and needs tight packing, so it uses MinAlign=1. (alignof(T) would
pack just as tightly and reuse the default instantiation, but T may be
incomplete here, e.g. `SpecificBumpPtrAllocator<MCSectionELF>`.)
Its `Allocate` still skips the realign: the slab is max_align_t-aligned
and every size is a multiple of alignof(T), so the bump pointer stays
alignof(T)-aligned and we can just request alignment 1. Over-aligned
types (alignof(T) > alignof(max_align_t)) keep requesting alignof(T).
Also use `bit_ceil` instead of `NextPowerOf2` in the placement operator
new alignment heuristic. NextPowerOf2 is strictly greater, so an 8-byte
pointer-sized object asked for alignment 16 and missed the fast path;
bit_ceil(8) == 8 keeps it on the fast path.
Aided by Claude Opus 4.8
Commit: c56e892f5c520b4474158837d7968e5c8dc3e4c1
https://github.com/llvm/llvm-project/commit/c56e892f5c520b4474158837d7968e5c8dc3e4c1
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_store_local.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-add-sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-and.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-xchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-xor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_minmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/br-constant-invalid-sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug_shuffle_vector_to_scalar.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combiner-crash.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value-addrspaces.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.illegal.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/icmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.frexp.mant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.p1.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.live.mask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mul24.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.softwqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.strictwqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.swap.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wwm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant32bit.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-divergent.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-divergent.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mmra.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.subdword.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sbfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shader-epilogs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-divergent-addr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-uniform-addr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ubfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/v_bfe_i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
M llvm/test/CodeGen/AMDGPU/allow-check.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-break-large-phis.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
M llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-max-pregfx12.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/barrier-elimination-gfx12.ll
M llvm/test/CodeGen/AMDGPU/barrier-elimination.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bitop3-shared-operand.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-c-function.ll
M llvm/test/CodeGen/AMDGPU/call-constant.ll
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M llvm/test/CodeGen/AMDGPU/call-defs-mode-register.ll
M llvm/test/CodeGen/AMDGPU/call-encoding.ll
M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
M llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-return-types.ll
M llvm/test/CodeGen/AMDGPU/call-skip.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callbr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/cc-inreg-sgpr0-3-mismatch.ll
M llvm/test/CodeGen/AMDGPU/check-subtarget-features.ll
M llvm/test/CodeGen/AMDGPU/cluster-dims.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ctpop.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cube.ll
M llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll
M llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs-v2f32.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-image-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-flat-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-global-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpenv.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
M llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll
M llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/global-address.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/gws_agpr.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/intrinsic-amdgcn-s-alloc-vgpr.ll
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/invariant-image-load.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/lds-barrier-memoperand.ll
M llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll
M llvm/test/CodeGen/AMDGPU/lds-size.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.addrspacecast.nonnull.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load-last-use.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.lds.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.flat.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-agent.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-basic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-singlethread.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-system.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-wavefront.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-workgroup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f32.fp8.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.off.f32.i4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.add.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.append.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.async.barrier.arrive.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.fi.b32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.consume.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-bundle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add-errors.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.sub.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.flt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.direct.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.param.load.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.i24.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.monitor.sleep.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.nop.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sethalt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.inc.wg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.ttracedata.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
M llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/load-range-metadata-sign-bits.ll
M llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-opt.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/make-buffer-rsrc-lds-fails.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/med3-knownbits.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx942.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/overlapping-tuple-copy-implicit-op-failure.ll
M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll
M llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-register.ll
M llvm/test/CodeGen/AMDGPU/read_register.ll
M llvm/test/CodeGen/AMDGPU/readcyclecounter.ll
M llvm/test/CodeGen/AMDGPU/readsteadycounter.ll
M llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
M llvm/test/CodeGen/AMDGPU/ret.ll
M llvm/test/CodeGen/AMDGPU/returnaddress.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/scratch-pointer-sink.ll
M llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll
M llvm/test/CodeGen/AMDGPU/shlN_add.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
M llvm/test/CodeGen/AMDGPU/stackguard.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.invalid.ll
M llvm/test/CodeGen/AMDGPU/store-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/store-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/store-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll
M llvm/test/CodeGen/AMDGPU/swizzle.bit.extract.ll
M llvm/test/CodeGen/AMDGPU/tail-call-amdgpu-gfx.ll
M llvm/test/CodeGen/AMDGPU/target-mem-intrinsic-metadata.ll
M llvm/test/CodeGen/AMDGPU/trap.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
M llvm/test/CodeGen/AMDGPU/unaligned-buffer.ll
M llvm/test/CodeGen/AMDGPU/unsupported-cs-chain.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.ll
M llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
M llvm/test/CodeGen/AMDGPU/write-register-invalid-register.ll
M llvm/test/CodeGen/AMDGPU/write_register.ll
Log Message:
-----------
AMDGPU/GlobalISel: Remove -new-reg-bank-select option (#203929)
AMDGPU's -global-isel pipeline that uses AMDGPURegBankSelect and
AMDGPURegBankLegalize, previously -global-isel -new-reg-bank-select,
is now the default -global-isel pipeline.
Remove -new-reg-bank-select option from the compiler.
Remove -new-reg-bank-select from all llvm regression tests.
Edit a couple comments to reference RegBankLegalize instead of
-new-reg-bank-select.
Commit: f3fb6fe3099887ce1538c1dbbe3694f740f9f126
https://github.com/llvm/llvm-project/commit/f3fb6fe3099887ce1538c1dbbe3694f740f9f126
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/new-delete.cpp
Log Message:
-----------
[clang][bytecode] Check for block pointers in Free() (#205043)
We need a block pointer here for the following operations, and non-block
pointers aren't valid anyway.
Commit: 4fd464061536f1bb7d12ee9524712d202c2b4488
https://github.com/llvm/llvm-project/commit/4fd464061536f1bb7d12ee9524712d202c2b4488
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
A llvm/test/Analysis/DependenceAnalysis/find-gcd-overflow.ll
Log Message:
-----------
[DA] Add overflow check before calculating absolute value (#201964)
In findGCD, we call APInt::abs, which can overflow when the value is a
signed minimum one. Such overflow can lead miscompilation, so this patch
adds an overflow check for absolute value calculations and bail out
early if it actually overflows.
Fix #201559.
Commit: 8b723503336f094afb92f00cb73378321914f6cf
https://github.com/llvm/llvm-project/commit/8b723503336f094afb92f00cb73378321914f6cf
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
Log Message:
-----------
[NFC][analyzer] Eliminate some simple node builders (#204187)
Replace four `NodeBuilder`s with direct use of the `makeNode` method
family. This is part of my commit series that simplifies the engine by
gradually eliminating the class `NodeBuilder`.
Commit: b6a0f6c79fee527a5ef2826e30949cd8f27db889
https://github.com/llvm/llvm-project/commit/b6a0f6c79fee527a5ef2826e30949cd8f27db889
Author: Jiaqi He <heturing at gmail.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/test/Sema/LifetimeSafety/lifetimebound-violation.cpp
Log Message:
-----------
[LifetimeSafety] resolved lifetimeBound violation in constructor (#204797)
Fix https://github.com/llvm/llvm-project/issues/203839.
Constructor body does not produce `ReturnEscapeFact`, but a constructor
parameter marked [[clang::lifetimebound]] may still be valid if it
escapes into a field of the constructed object.
Update the `LifetimeBound` logic to accept `FieldEscapeFact` for
constructors, and add a test case for this pattern.
Commit: b3022110d84dabf5ddbbecd7db4e943791d5320c
https://github.com/llvm/llvm-project/commit/b3022110d84dabf5ddbbecd7db4e943791d5320c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
Log Message:
-----------
clang/AMDGPU: Use effective triple instead of raw toolchain triple (#205054)
Start using the effective triple instead of the raw toolchain triple.
For the moment this is NFC, but will change when new uses of the subarch
field are introduced.
Commit: c5f4abf97938cc1d4615baf1f45bef4e38e0dd91
https://github.com/llvm/llvm-project/commit/c5f4abf97938cc1d4615baf1f45bef4e38e0dd91
Author: Sushant Gokhale <sgokhale at nvidia.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/revec-ordered-reductions.ll
M llvm/test/Transforms/SLPVectorizer/revec.ll
Log Message:
-----------
[SLP][Revec] Fix SLP crash when trying to fold trailing scalars into the reduced value (#203477)
Cost modelling change introduced by commit SHA f15666d is enabling revec
of test shown in the above issue. This is introducing a crash as the
reduced value(a scalar) is being added to a vector tail value.
Patch tries to address this.
Fixes #203195
Commit: f8cb6be61b995fc64d696c42fdb3eb88d2ed3a9e
https://github.com/llvm/llvm-project/commit/f8cb6be61b995fc64d696c42fdb3eb88d2ed3a9e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
Log Message:
-----------
clang: Use the effective triple string for offload jobs (#205065)
Track the future effective triple for the job, rather than
the toolchain's default triple. In the future this will
change the result when amdgpu starts adjusting the triples
to contain subarches.
Commit: 6019657c6a4528e92887bec4b52222f9c0fc6a8b
https://github.com/llvm/llvm-project/commit/6019657c6a4528e92887bec4b52222f9c0fc6a8b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M offload/ci/openmp-offload-amdgpu-libc-runtime.py
Log Message:
-----------
Reapply "[AMDGPU] Add compiler-rt checks for the GPU runtime" (#204898)
The original issue should've been solved by
https://github.com/llvm/llvm-project/pull/204694
Reverts llvm/llvm-project#204370
Commit: 4f5c444227c76c41146b7a91c1a1cab460c74112
https://github.com/llvm/llvm-project/commit/4f5c444227c76c41146b7a91c1a1cab460c74112
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M orc-rt/include/orc-rt/QueueingRunner.h
M orc-rt/unittests/InProcessControllerAccessTest.cpp
M orc-rt/unittests/QueueingRunnerTest.cpp
M orc-rt/unittests/SessionTest.cpp
Log Message:
-----------
[orc-rt] Default QueueingRunner to a synchronized queue. (#205088)
Adds orc_rt::detail::SynchronizedDeque<T>, a mutex-protected deque whose
pop_front / pop_back return std::optional<T> (std::nullopt indicates the
queue is empty), and makes it QueueingRunner's default WorkQueue type.
Using a synchronized queue type allows QueueingRunner to be used in
multi-threaded contexts.
Updates SessionTest and InProcessControllerAccessTest to use the new
default, and extends QueueingRunnerTest to cover the new contract.
Commit: 8616fad2fa5c772b7ebc254335e7c6be858a5182
https://github.com/llvm/llvm-project/commit/8616fad2fa5c772b7ebc254335e7c6be858a5182
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M lldb/source/Target/Memory.cpp
Log Message:
-----------
[lldb] Avoid tautological copying of a newly created object (NFC) (#204998)
Commit: 27af208fe5cbd7d6b9ba24b22d75f1abba42c111
https://github.com/llvm/llvm-project/commit/27af208fe5cbd7d6b9ba24b22d75f1abba42c111
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
A llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16-fake.txt
R llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
Log Message:
-----------
[AMDGPU][NFC] Templatise and roundtrip gfx12_asm_vop3_dpp16.s (#203953)
This is effectively the changes between the non-template versions of
gfx11/12_asm_vop3_dpp16.s applied on top of the templatised
gfx11_asm_vop3_dpp16.s.
Commit: a7808183c742b88065e912dd0b98ab446b01b7c0
https://github.com/llvm/llvm-project/commit/a7808183c742b88065e912dd0b98ab446b01b7c0
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/test/MC/AMDGPU/gfx13_asm_vop3_dpp16.s
Log Message:
-----------
[AMDGPU][NFC] Templatise and roundtrip gfx13_asm_vop3_dpp16.s (#204849)
Again, this is based on the templatised version of
gfx12_asm_vop3_dpp16.s with the GFX13-specific changes re-applied on top
of it.
gfx13_dasm_vop3_dpp16.txt was never upstreamed, so no changes for the
disassembler side.
Commit: 06dcba660904e041cca1d245e674f040bb04f454
https://github.com/llvm/llvm-project/commit/06dcba660904e041cca1d245e674f040bb04f454
Author: Tim <timothy.smith at hpe.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
A flang/test/Transforms/debug-fake-use-multiple-dimensions.fir
A flang/test/Transforms/debug-fake-use-multiple-returns.fir
M flang/test/Transforms/debug-fake-use.fir
Log Message:
-----------
[flang][debug] Add fake use ops for dynamic array dimension variables (#200061)
In cases where the upper or lower bounds of a dynamic array are not
explicitly referenced in code, flang can optimize away the internal
variables that represent these values. This causes missing values to
appear in the debugger when examining the dynamic array's type. Adding
an llvm.fake.use op for each bound preserves it for use by a debugger,
similar to the fix for #185432.
Resolves #119474
Commit: b0c2017bcff5ae07fe44d3271a269e50e1c98cbd
https://github.com/llvm/llvm-project/commit/b0c2017bcff5ae07fe44d3271a269e50e1c98cbd
Author: Adam Siemieniuk <adam.siemieniuk at intel.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M mlir/lib/Dialect/X86/Transforms/VectorContractToAMXDotProduct.cpp
M mlir/test/Dialect/X86/AMX/vector-contract-to-tiled-dp.mlir
Log Message:
-----------
[mlir][x86] Fail on missing read source operation (#205077)
Adds an extra check to AMX lowering to fail gracefully when a source
operation for contraction input data is not found.
Commit: a7e3eda221412f798ae448c293217f49f4a5ebed
https://github.com/llvm/llvm-project/commit/a7e3eda221412f798ae448c293217f49f4a5ebed
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/include/llvm/Support/Allocator.h
M llvm/unittests/Support/AllocatorTest.cpp
Log Message:
-----------
Revert "[Allocator] Keep bump pointer at a minimum alignment" (#205091)
Arithmetic on nullptr is UB and gets flagged by UBSan.
Reverts llvm/llvm-project#203718
Commit: d8657e1bb196d52892365da5cf917f8ed90932f8
https://github.com/llvm/llvm-project/commit/d8657e1bb196d52892365da5cf917f8ed90932f8
Author: Sean Perry <perry at ca.ibm.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/unittests/CMakeLists.txt
Log Message:
-----------
Don't test JIT's on z/OS (#196580)
The JIT's aren't supported on z/OS so no need to run the unit tests on
them.
Commit: 685af3ab083c71c32172fb7116176b55a6c26b25
https://github.com/llvm/llvm-project/commit/685af3ab083c71c32172fb7116176b55a6c26b25
Author: Akshay Kumar Dubey <123586645+akshaydubey05 at users.noreply.github.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M clang-tools-extra/clangd/tool/ClangdMain.cpp
Log Message:
-----------
[clangd] Log environment variables that influence compilation at startup (#204990)
When users face missing system include issues (especially on Windows),
it's difficult to diagnose whether the problem is caused by missing
environment variables like `INCLUDE`, `CPATH`, etc.
This patch logs the values of environment variables that influence how the
compiler finds headers and libraries, at startup alongside the existing
version/PID/argv logs. Only variables that are actually set are printed.
Variables logged:
- MSVC (set by vcvarsall.bat): `INCLUDE`, `LIB`, `LIBPATH`, `CL`, `_CL_`
- GCC/Clang: `CPATH`, `C_INCLUDE_PATH`, `CPLUS_INCLUDE_PATH`,
`OBJC_INCLUDE_PATH`, `LIBRARY_PATH`, `GCC_EXEC_PREFIX`
Fixes https://github.com/clangd/clangd/issues/2657
Commit: 079683b7e1d0cb39cbb2205d38425d56030d31b2
https://github.com/llvm/llvm-project/commit/079683b7e1d0cb39cbb2205d38425d56030d31b2
Author: Reinhard Stahn <rainij36 at proton.me>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
Log Message:
-----------
[mlir][scf] Tighten description of scf.for (#203713)
The previous description was vague in the case that the
one-past-the-last value for the induction variable is not representable
in the used integer type. Current passes implicitly exploit this by
implementing non-equivalent semantics (e.g. terminating vs
non-terminating loops).
We tighten the specification of `scf.for` by first stating the desired
ideal semantics, but deeming overflow undefined behavior. This fixes all
inconsistencies I am aware of.
Documentation only; no behavioral change.
Commit: 8062e6dc822b7832d8d988bd9cc70a04a327848a
https://github.com/llvm/llvm-project/commit/8062e6dc822b7832d8d988bd9cc70a04a327848a
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/bypass-div.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
Log Message:
-----------
[AMDGPU] Remove support for ADDC/ADDE/SUBC/SUBE DAG nodes (#205082)
Since #204694 we should be using UADDO/USUBO/UADDO_CARRY/USUBO_CARRY
instead.
Commit: fd1c4828f509921bc27d8620e7297f9dca0a9bf0
https://github.com/llvm/llvm-project/commit/fd1c4828f509921bc27d8620e7297f9dca0a9bf0
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-22 (Mon, 22 Jun 2026)
Changed paths:
M .github/workflows/new-prs.yml
M .github/workflows/spirv-tests.yml
M .github/workflows/subscriber.yml
M bolt/include/bolt/Core/BinaryContext.h
M bolt/lib/Passes/Aligner.cpp
M bolt/lib/Passes/LongJmp.cpp
M bolt/lib/Rewrite/BinaryPassManager.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/binary-analysis/AArch64/cfg-warning.s
M clang-tools-extra/clangd/CompileCommands.cpp
M clang-tools-extra/clangd/test/background-index.test
M clang-tools-extra/clangd/test/include-cleaner-batch-fix.test
M clang-tools-extra/clangd/test/path-mappings.test
M clang-tools-extra/clangd/tool/ClangdMain.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/header-include-cycle.cpp
M clang-tools-extra/test/clang-tidy/checkers/portability/restrict-system-includes-transitive.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming-symlink.cpp
M clang-tools-extra/test/clang-tidy/infrastructure/clang-tidy-mac-libcxx.cpp
M clang-tools-extra/test/clang-tidy/infrastructure/remarks.cpp
M clang/bindings/xml/comment-xml-schema.rng
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/docs/ConstantInterpreter.rst
M clang/docs/LanguageExtensions.rst
M clang/docs/LifetimeSafety.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/UsersManual.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/AST/Decl.h
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/LangOptions.h
M clang/include/clang/Basic/PragmaKinds.h
M clang/include/clang/Basic/arm_neon.td
M clang/include/clang/Basic/riscv_sifive_vector.td
M clang/include/clang/Basic/riscv_vector_common.td
M clang/include/clang/Options/Options.td
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/include/clang/Support/RISCVVIntrinsicUtils.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Analysis/FlowSensitive/FormulaSerialization.cpp
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/lib/Analysis/LifetimeSafety/Origins.cpp
M clang/lib/Basic/TargetID.cpp
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/OSTargets.h
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenModule.h
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/CodeGen/TargetBuiltins/X86.cpp
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/FormatTokenLexer.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Format/UnwrappedLineParser.h
M clang/lib/Frontend/DependencyFile.cpp
M clang/lib/Headers/avx512vlvnniintrin.h
M clang/lib/Headers/avx512vnniintrin.h
M clang/lib/Headers/avxvnniintrin.h
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Parse/ParsePragma.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/StaticAnalyzer/Checkers/Yaml.h
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/Support/RISCVVIntrinsicUtils.cpp
M clang/test/APINotes/module-cache.m
M clang/test/AST/ByteCode/builtin-functions.cpp
A clang/test/AST/ByteCode/command-line-options.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ByteCode/dynamic-cast.cpp
M clang/test/AST/ByteCode/new-delete.cpp
M clang/test/Analysis/analyzer-enabled-checkers.c
M clang/test/Analysis/bstring.c
M clang/test/Analysis/bstring.cpp
M clang/test/Analysis/bstring_UninitRead.c
M clang/test/Analysis/cstring-uninitread-notes.c
M clang/test/Analysis/infeasible-crash.c
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
M clang/test/Analysis/wstring.c
A clang/test/CIR/CodeGen/agg-atomic-cast.cpp
M clang/test/CMakeLists.txt
M clang/test/CXX/module/cpp.pre/module_decl.cpp
M clang/test/ClangScanDeps/build-session-validation-relocated-modules.c
M clang/test/ClangScanDeps/header-search-pruning.cpp
M clang/test/ClangScanDeps/modules-context-hash.c
M clang/test/ClangScanDeps/modules-relocated-mm-macro.c
M clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
M clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c
M clang/test/CodeGen/AArch64/bf16-ldst-intrinsics.c
M clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon-luti.c
M clang/test/CodeGen/AArch64/neon/add.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
A clang/test/CodeGen/PowerPC/pragma-comment-copyright-modules.cpp
A clang/test/CodeGen/PowerPC/pragma-comment.c
M clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
M clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
M clang/test/CodeGen/X86/avx512vlvnni-builtins.c
M clang/test/CodeGen/X86/avx512vnni-builtins.c
M clang/test/CodeGen/X86/avxvnni-builtins.c
M clang/test/CodeGen/X86/bmi2-builtins.c
M clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
M clang/test/CodeGen/builtins-elementwise-math.c
M clang/test/CodeGen/lto-newpm-pipeline.c
M clang/test/CodeGen/ubsan-aggregate-null-align-bounds.c
M clang/test/CodeGenHLSL/builtins/ddx-coarse-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-coarse.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-fine-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddx-fine.hlsl
M clang/test/CodeGenHLSL/builtins/ddx.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-coarse-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-coarse.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-fine-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/ddy-fine.hlsl
M clang/test/CodeGenHLSL/builtins/ddy.hlsl
A clang/test/CodeGenHLSL/resources/ConstantBufferT.hlsl
M clang/test/Driver/femit-dwarf-unwind.c
M clang/test/Driver/femit-dwarf-unwind.s
M clang/test/Driver/hip-runtime-libs-linux.hip
M clang/test/Driver/hip-toolchain-rdc-static-lib.hip
M clang/test/Driver/hip-toolchain-rdc.hip
M clang/test/Driver/hip-version.hip
M clang/test/Driver/invalid-target-id.cl
M clang/test/Driver/lto.c
M clang/test/Driver/rocm-detect-lib-llvm.hip
M clang/test/Driver/rocm-detect.hip
A clang/test/Index/Inputs/CommentXML/invalid-concept-01.xml
A clang/test/Index/Inputs/CommentXML/valid-concept-01.xml
A clang/test/Index/Inputs/CommentXML/valid-concept-02.xml
M clang/test/Index/comment-xml-schema.c
M clang/test/InstallAPI/binary-attributes.test
M clang/test/InstallAPI/diagnostics-zippered.test
M clang/test/InstallAPI/directory-scanning-dylib.test
M clang/test/InstallAPI/directory-scanning-frameworks.test
M clang/test/InstallAPI/directory-scanning-subdirectories.test
M clang/test/InstallAPI/exclusive-passes-zippered.test
M clang/test/InstallAPI/extra-exclude-headers.test
M clang/test/InstallAPI/forwarded-search-paths.test
M clang/test/InstallAPI/umbrella-headers-unix.test
M clang/test/InstallAPI/umbrella-headers.test
M clang/test/Modules/add-remove-private.m
M clang/test/Modules/build-session-validation-relocated-modules.c
M clang/test/Modules/dependent-module-different-location.m
M clang/test/Modules/implicit-invalidate-common.c
M clang/test/Modules/include-relative.c
M clang/test/Modules/relative-import-path.c
M clang/test/Preprocessor/hexagon-predefines.c
A clang/test/Preprocessor/pragma-comment.c
M clang/test/Sema/LifetimeSafety/annotation-suggestions-fixits.cpp
M clang/test/Sema/LifetimeSafety/dangling-global.cpp
M clang/test/Sema/LifetimeSafety/lifetimebound-violation.cpp
M clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-intra-tu.cpp
M clang/test/Sema/LifetimeSafety/safety-c.c
M clang/test/Sema/LifetimeSafety/safety.cpp
M clang/test/Sema/aarch64-neon-immediate-ranges/luti.c
M clang/test/Sema/aarch64-neon-target.c
M clang/test/Sema/aarch64-neon-without-target-feature.cpp
M clang/test/Sema/arm-neon-target.c
M clang/test/Sema/builtins-elementwise-math.c
M clang/test/Sema/enable_if.c
M clang/test/Sema/sifive-xsfmm.c
M clang/test/SemaCXX/enable_if.cpp
M clang/test/SemaTemplate/instantiate-member-template.cpp
M clang/test/Tooling/clang-check-mac-libcxx-abspath.cpp
M clang/test/Tooling/clang-check-mac-libcxx-fixed-compilation-db.cpp
M clang/test/Tooling/clang-check-mac-libcxx-relpath.cpp
M clang/test/lit.cfg.py
M clang/tools/driver/cc1as_main.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M compiler-rt/lib/builtins/cpu_model/riscv/hwprobe.inc
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/fuzz/CMakeLists.txt
R compiler-rt/lib/scudo/standalone/fuzz/get_error_info_fuzzer.cpp
M compiler-rt/lib/scudo/standalone/include/scudo/interface.h
M compiler-rt/lib/scudo/standalone/wrappers_c.cpp
M compiler-rt/lib/tsan/rtl/tsan_platform.h
M compiler-rt/test/builtins/Unit/lit.cfg.py
M compiler-rt/test/fuzzer/fork.test
M compiler-rt/test/fuzzer/fork_corpus_groups.test
A flang/docs/MeetingNotes/2026/2026-06-17.md
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/MultiImageFortran.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/Support/ReductionProcessor.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/lib/Optimizer/Transforms/MIFOpConversion.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Integration/split-lto-unit-2.f90
M flang/test/Lower/MIF/coarray_allocation3.f90
M flang/test/Lower/MIF/coarray_allocation4.f90
M flang/test/Lower/MIF/coarray_allocation5.f90
M flang/test/Lower/OpenMP/Todo/multiple-types-declare_reduction.f90
M flang/test/Lower/OpenMP/declare-reduction-character-allocatable.f90
M flang/test/Lower/OpenMP/declare-reduction-finalizer.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-component.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-defined-assign.f90
M flang/test/Lower/OpenMP/declare-reduction-initializer-rhs-call.f90
M flang/test/Lower/OpenMP/declare-reduction-no-initializer-intrinsic.f90
M flang/test/Lower/OpenMP/declare-reduction-no-initializer-target-derived.f90
A flang/test/Lower/OpenMP/declare-reduction-same-name-different-scope.f90
M flang/test/Lower/OpenMP/declare-reduction-target-intrinsic.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-combsub.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-derivedtype.f90
M flang/test/Lower/OpenMP/omp-declare-reduction-initsub.f90
M flang/test/Lower/OpenMP/omp-declare-reduction.f90
M flang/test/Semantics/OpenMP/declarative-directive01.f90
M flang/test/Semantics/OpenMP/requires01.f90
M flang/test/Semantics/OpenMP/requires03.f90
M flang/test/Semantics/OpenMP/requires04.f90
M flang/test/Semantics/OpenMP/requires05.f90
M flang/test/Semantics/OpenMP/requires06.f90
M flang/test/Semantics/OpenMP/requires07.f90
M flang/test/Semantics/OpenMP/requires08.f90
M flang/test/Semantics/OpenMP/requires10.f90
A flang/test/Transforms/debug-fake-use-multiple-dimensions.fir
A flang/test/Transforms/debug-fake-use-multiple-returns.fir
M flang/test/Transforms/debug-fake-use.fir
M libc/src/math/docs/add_math_function.md
M libcxx/include/__cstddef/byte.h
M libcxx/include/map
M libcxx/include/string
M libcxx/include/string.h
M libcxx/test/libcxx/concepts/concepts.arithmetic/__libcpp_signed_integer.compile.pass.cpp
M libcxx/test/libcxx/concepts/concepts.arithmetic/__libcpp_unsigned_integer.compile.pass.cpp
M libcxx/test/libcxx/gdb/gdb_pretty_printer_test.sh.cpp
M libcxx/test/libcxx/language.support/nodiscard.verify.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/for_each.associative.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/ranges.for_each.associative.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/move_alloc.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/move_assign.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/merge.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/contains.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/contains_transparent.pass.cpp
M libcxx/test/std/containers/associative/multimap/empty.pass.cpp
M libcxx/test/std/containers/associative/multimap/get_allocator.pass.cpp
M libcxx/test/std/containers/associative/multimap/incomplete_type.pass.cpp
M libcxx/test/std/containers/associative/multimap/iterator.pass.cpp
M libcxx/test/std/containers/associative/multimap/max_size.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/alloc.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/assign_initializer_list.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/compare.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/compare_alloc.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/copy.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/copy_alloc.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/copy_assign.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/deduct.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/deduct_const.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/default.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/default_noexcept.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/dtor_noexcept.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/from_range.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/initializer_list.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/initializer_list_compare.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/initializer_list_compare_alloc.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/iter_iter.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/iter_iter_comp.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/iter_iter_comp_alloc.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/move.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/move_alloc.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/move_assign.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.cons/move_noexcept.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.erasure/erase_if.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/clear.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/emplace.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/emplace_hint.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/erase_iter.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/erase_iter_iter.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/erase_key.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/extract_iterator.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/extract_key.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_allocator_requirements.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_cv.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_initializer_list.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_iter_cv.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_iter_iter.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_iter_rv.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_node_type.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_node_type_hint.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_range.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/insert_rv.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.modifiers/merge.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.nonmember/compare.three_way.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.nonmember/op_compare.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.observers/key_comp.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.observers/value_comp.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/count.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/count0.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/count_transparent.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/equal_range.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/equal_range0.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/equal_range_transparent.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/find.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/find0.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/lower_bound.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/lower_bound0.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/upper_bound.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.ops/upper_bound0.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.special/member_swap.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.special/non_member_swap.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.special/swap_noexcept.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.value_compare/invoke.pass.cpp
M libcxx/test/std/containers/associative/multimap/multimap.value_compare/types.pass.cpp
M libcxx/test/std/containers/associative/multimap/size.pass.cpp
M libcxx/test/std/containers/associative/multimap/types.pass.cpp
M libcxx/test/std/containers/container.node/node_handle.pass.cpp
M libcxx/test/std/containers/views/mdspan/extents/bitint.pass.cpp
M libcxx/test/std/language.support/support.limits/limits/numeric.limits.members/digits.pass.cpp
M libcxx/test/std/language.support/support.limits/limits/numeric.limits.members/digits10.pass.cpp
M libcxx/test/std/language.support/support.limits/limits/numeric.limits.members/max.pass.cpp
M libcxx/test/std/language.support/support.limits/limits/numeric.limits.members/min.pass.cpp
A libcxx/test/std/language.support/support.types/byte.compile.pass.cpp
R libcxx/test/std/language.support/support.types/byte.pass.cpp
M libcxx/test/std/language.support/support.types/byteops/and.assign.pass.cpp
M libcxx/test/std/language.support/support.types/byteops/and.pass.cpp
R libcxx/test/std/language.support/support.types/byteops/enum_direct_init.pass.cpp
R libcxx/test/std/language.support/support.types/byteops/lshift.assign.compile.fail.cpp
M libcxx/test/std/language.support/support.types/byteops/lshift.assign.pass.cpp
R libcxx/test/std/language.support/support.types/byteops/lshift.compile.fail.cpp
M libcxx/test/std/language.support/support.types/byteops/lshift.pass.cpp
M libcxx/test/std/language.support/support.types/byteops/not.pass.cpp
M libcxx/test/std/language.support/support.types/byteops/or.assign.pass.cpp
M libcxx/test/std/language.support/support.types/byteops/or.pass.cpp
R libcxx/test/std/language.support/support.types/byteops/rshift.assign.compile.fail.cpp
M libcxx/test/std/language.support/support.types/byteops/rshift.assign.pass.cpp
R libcxx/test/std/language.support/support.types/byteops/rshift.compile.fail.cpp
M libcxx/test/std/language.support/support.types/byteops/rshift.pass.cpp
R libcxx/test/std/language.support/support.types/byteops/to_integer.compile.fail.cpp
M libcxx/test/std/language.support/support.types/byteops/to_integer.pass.cpp
M libcxx/test/std/language.support/support.types/byteops/xor.assign.pass.cpp
M libcxx/test/std/language.support/support.types/byteops/xor.pass.cpp
M libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.pass.cpp
M libcxx/test/std/numerics/bit/bit.pow.two/bit_floor.pass.cpp
M libcxx/test/std/numerics/bit/bit.pow.two/bit_width.pass.cpp
M libcxx/test/std/numerics/bit/bit.pow.two/has_single_bit.pass.cpp
M libcxx/test/std/numerics/bit/bitops.count/countl_one.pass.cpp
M libcxx/test/std/numerics/bit/bitops.count/countl_zero.pass.cpp
M libcxx/test/std/numerics/bit/bitops.count/countr_one.pass.cpp
M libcxx/test/std/numerics/bit/bitops.count/countr_zero.pass.cpp
M libcxx/test/std/numerics/bit/bitops.count/popcount.pass.cpp
M libcxx/test/std/numerics/bit/bitops.rot/rotl.pass.cpp
M libcxx/test/std/numerics/bit/bitops.rot/rotr.pass.cpp
M libcxx/test/std/numerics/bit/byteswap.pass.cpp
M libcxx/test/std/numerics/bit/byteswap.verify.cpp
M libcxx/test/std/numerics/numeric.ops/numeric.ops.sat/saturating.bitint.pass.cpp
R libcxx/test/std/utilities/format/format.arguments/format.arg.store/make_format_args.bitint.verify.cpp
M libcxx/test/std/utilities/utility/utility.intcmp/intcmp.bitint.pass.cpp
M libcxx/test/support/test_macros.h
M libcxx/utils/gdb/libcxx/printers.py
M lld/ELF/Arch/AArch64.cpp
M lld/MachO/ICF.cpp
M lld/test/ELF/aarch64-tls-le.s
M lld/test/ELF/aarch64-tlsld-ldst.s
A lld/test/MachO/icf-safe-data-addrsig.s
M lldb/include/lldb/Host/Editline.h
M lldb/source/Host/common/Editline.cpp
M lldb/source/Host/windows/PythonRuntimeLoaderWindows.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/ObjCLanguageRuntime.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/ObjCLanguageRuntime.h
M lldb/source/Plugins/ObjectContainer/Universal-Mach-O/ObjectContainerUniversalMachO.cpp
M lldb/source/Target/Memory.cpp
M lldb/source/Target/Target.cpp
M lldb/test/API/commands/frame/diagnose/inheritance/main.cpp
M lldb/test/API/functionalities/breakpoint/cpp_exception/TestCPPExceptionBreakpoint.py
M lldb/test/API/functionalities/exec/TestExec.py
M lldb/test/API/functionalities/fork/resumes-child/TestForkResumesChild.py
M lldb/test/API/functionalities/inferior-changed/TestInferiorChanged.py
M lldb/test/API/functionalities/inferior-crashing/TestInferiorCrashing.py
M lldb/test/API/functionalities/inferior-crashing/TestInferiorCrashingStep.py
M lldb/test/API/functionalities/inferior-crashing/recursive-inferior/TestRecursiveInferior.py
M lldb/test/API/functionalities/inferior-crashing/recursive-inferior/TestRecursiveInferiorStep.py
M lldb/test/API/functionalities/longjmp/TestLongjmp.py
M lldb/test/API/functionalities/plugins/python_os_plugin/TestPythonOSPlugin.py
M lldb/test/API/functionalities/plugins/python_os_plugin/main.c
M lldb/test/API/functionalities/process_group/TestChangeProcessGroup.py
M lldb/test/API/lang/cpp/exceptions/TestCPPExceptionBreakpoints.py
M lldb/test/API/lang/cpp/extern_c/main.cpp
M lldb/test/API/lang/cpp/floating-types-specialization/TestCppFloatingTypesSpecialization.py
M lldb/test/API/lang/cpp/unique-types/main.cpp
M lldb/test/API/python_api/sbvalue_const_addrof/main.cpp
M lldb/test/API/python_api/sbvalue_unsigned_enum_bitfield_value/main.cpp
M lldb/test/API/python_api/target/main.c
M lldb/test/API/tools/lldb-dap/exception/cpp/TestDAP_exception_cpp.py
M lldb/test/API/tools/lldb-dap/launch/main.c
M lldb/test/API/tools/lldb-dap/restart/main.c
A lldb/test/Shell/Expr/wasm-no-objc-codegen.test
M lldb/unittests/CMakeLists.txt
M lldb/unittests/Editline/EditlineTest.cpp
M lldb/unittests/Host/HostTest.cpp
A lldb/unittests/ObjectContainer/CMakeLists.txt
A lldb/unittests/ObjectContainer/ObjectContainerUniversalMachOTest.cpp
M llvm/docs/AMDGPUAsyncOperations.rst
M llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst
M llvm/docs/AMDGPUExecutionSynchronization.rst
M llvm/docs/ReleaseNotes.md
M llvm/examples/OrcV2Examples/CMakeLists.txt
A llvm/examples/OrcV2Examples/LLJITWithSymbolAliases/CMakeLists.txt
A llvm/examples/OrcV2Examples/LLJITWithSymbolAliases/LLJITWithSymbolAliases.cpp
M llvm/include/llvm/ADT/APFloat.h
M llvm/include/llvm/Analysis/AssumptionCache.h
M llvm/include/llvm/Analysis/ConstantFolding.h
M llvm/include/llvm/Analysis/InstSimplifyFolder.h
M llvm/include/llvm/Analysis/InstructionSimplify.h
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/include/llvm/Analysis/LoopCacheAnalysis.h
M llvm/include/llvm/Analysis/TargetFolder.h
M llvm/include/llvm/BinaryFormat/DXContainer.h
M llvm/include/llvm/CAS/ActionCache.h
M llvm/include/llvm/CAS/MappedFileRegionArena.h
M llvm/include/llvm/CAS/OnDiskDataAllocator.h
M llvm/include/llvm/CAS/OnDiskGraphDB.h
M llvm/include/llvm/CAS/OnDiskKeyValueDB.h
M llvm/include/llvm/CAS/OnDiskTrieRawHashMap.h
M llvm/include/llvm/CAS/UnifiedOnDiskCache.h
M llvm/include/llvm/CGData/StableFunctionMap.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/MIR2Vec.h
M llvm/include/llvm/DebugInfo/DWARF/LowLevel/DWARFDataExtractorSimple.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/IR/BasicBlock.h
M llvm/include/llvm/IR/ConstantFolder.h
M llvm/include/llvm/IR/IRBuilderFolder.h
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/IR/NoFolder.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/MC/MCTargetOptions.h
M llvm/include/llvm/Option/ArgList.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/ProfileData/SampleProfReader.h
M llvm/include/llvm/SandboxIR/Argument.h
M llvm/include/llvm/SandboxIR/BasicBlock.h
M llvm/include/llvm/SandboxIR/Function.h
M llvm/include/llvm/SandboxIR/Instruction.h
M llvm/include/llvm/SandboxIR/Pass.h
M llvm/include/llvm/SandboxIR/Region.h
M llvm/include/llvm/SandboxIR/Tracker.h
M llvm/include/llvm/SandboxIR/Use.h
M llvm/include/llvm/Support/CommandLine.h
M llvm/include/llvm/Support/Compiler.h
M llvm/include/llvm/Support/ConvertUTF.h
M llvm/include/llvm/Support/DataExtractor.h
M llvm/include/llvm/Support/GlobPattern.h
M llvm/include/llvm/Support/KnownBits.h
M llvm/include/llvm/Support/LSP/Logging.h
M llvm/include/llvm/Support/LSP/Protocol.h
M llvm/include/llvm/Support/LSP/Transport.h
M llvm/include/llvm/Support/VirtualOutputConfig.h
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/include/llvm/Transforms/Utils/DebugSSAUpdater.h
A llvm/include/llvm/Transforms/Utils/LowerCommentStringPass.h
M llvm/include/llvm/Transforms/Utils/SSAUpdaterBulk.h
M llvm/lib/Analysis/AssumptionCache.cpp
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/Delinearization.cpp
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
M llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/CAS/OnDiskGraphDB.cpp
M llvm/lib/CAS/OnDiskKeyValueDB.cpp
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/BranchFolding.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalMerge.cpp
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.h
M llvm/lib/DWP/DWP.cpp
M llvm/lib/ExecutionEngine/JITLink/COFF_x86_64.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/IRBuilder.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCAsmInfo.cpp
M llvm/lib/MC/MCAsmInfoXCOFF.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
M llvm/lib/MC/MCWin64EH.cpp
M llvm/lib/ObjCopy/COFF/COFFObjcopy.cpp
M llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp
M llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.h
M llvm/lib/ObjCopy/MachO/MachOObjcopy.cpp
M llvm/lib/ObjCopy/MachO/MachOWriter.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/ProfileData/SampleProfReader.cpp
M llvm/lib/Remarks/RemarkStreamer.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/ConvertUTFWrapper.cpp
M llvm/lib/Support/KnownBits.cpp
M llvm/lib/Support/WithColor.cpp
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/CMakeLists.txt
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
M llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.h
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
A llvm/lib/Target/AArch64/SVEShuffleOpts.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUBarrierLatency.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
M llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
M llvm/lib/Target/AMDGPU/R600ISelLowering.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/SIMachineScheduler.h
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMRegisterInfo.td
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.cpp
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILResourceAccess.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.td
M llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
M llvm/lib/Target/X86/X86InstrFragments.td
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
M llvm/lib/Target/X86/X86WinEHUnwindV3.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/lib/Transforms/IPO/InstrumentorConfigFile.cpp
M llvm/lib/Transforms/IPO/InstrumentorUtils.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/ObjCARC/ObjCARCContract.cpp
M llvm/lib/Transforms/Scalar/DropUnnecessaryAssumes.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Utils/CMakeLists.txt
A llvm/lib/Transforms/Utils/LowerCommentStringPass.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/BasicAA/phi-aa.ll
M llvm/test/Analysis/BasicAA/phi-and-select.ll
M llvm/test/Analysis/BasicAA/recphi.ll
M llvm/test/Analysis/CostModel/AArch64/clmul-fixed.ll
M llvm/test/Analysis/CostModel/AArch64/clmul-scalable.ll
M llvm/test/Analysis/CostModel/AArch64/clmul.ll
M llvm/test/Analysis/CostModel/X86/clmul.ll
A llvm/test/Analysis/Delinearization/inconsistent-types.ll
A llvm/test/Analysis/DependenceAnalysis/find-gcd-overflow.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/LoopnestFixedSize.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost-m32.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/loads-store.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/matmul.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/matvecmul.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/multi-store.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/single-store.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/stencil.ll
M llvm/test/Analysis/LoopCacheAnalysis/compute-cost.ll
M llvm/test/Analysis/LoopCacheAnalysis/interchange-cost-beneficial.ll
M llvm/test/Analysis/LoopCacheAnalysis/interchange-refcost-overflow.ll
M llvm/test/Analysis/LoopCacheAnalysis/partially-perfect-nest.ll
A llvm/test/Analysis/ModuleSummaryAnalysis/implicit-ref-edges.ll
A llvm/test/Analysis/ValueTracking/knownbits-pdep.ll
A llvm/test/Analysis/ValueTracking/knownbits-pext.ll
A llvm/test/Assembler/autoupgrade-lifetime-intrinsics-invalid-decl.ll
A llvm/test/Bitcode/Inputs/invalid-summary-version.bc
A llvm/test/Bitcode/invalid-summary-version.test
A llvm/test/CodeGen/AArch64/GlobalISel/combine-or-and-xor.ll
A llvm/test/CodeGen/AArch64/GlobalISel/combine-or-and-xor.mir
A llvm/test/CodeGen/AArch64/GlobalISel/pr204118.mir
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
R llvm/test/CodeGen/AArch64/aggressive-interleaving.ll
M llvm/test/CodeGen/AArch64/clmul-fixed.ll
M llvm/test/CodeGen/AArch64/clmul-scalable.ll
M llvm/test/CodeGen/AArch64/clmul.ll
A llvm/test/CodeGen/AArch64/extend-bool-vector-load.ll
M llvm/test/CodeGen/AArch64/lower-range-metadata-func-call.ll
A llvm/test/CodeGen/AArch64/pr204118.ll
M llvm/test/CodeGen/AArch64/print-pipeline-passes.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-64b-scaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-64b-unscaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter-64b-scaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter-64b-unscaled.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
A llvm/test/CodeGen/AArch64/sve-tbl-folding-new-pm.ll
A llvm/test/CodeGen/AArch64/sve-tbl-folding-opts.ll
A llvm/test/CodeGen/AArch64/windows-elf-frame-record-pairing.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/and.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_store_local.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-add-sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-and.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-xchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-xor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_minmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/br-constant-invalid-sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-store-pointers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/bug_shuffle_vector_to_scalar.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combiner-crash.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr-new-regbank-select.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value-addrspaces.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.illegal.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/icmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy-scc-vcc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.frexp.mant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.ptr.buffer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.p1.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.live.mask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mul24.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.integer-minmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.softwqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.strictwqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wwm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.atomic.cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant32bit.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-divergent.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-divergent.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mmra.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/or.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.subdword.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
R llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.ll
R llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sbfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shader-epilogs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/smul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-divergent-addr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/store-uniform-addr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ubfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/v_bfe_i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-iu-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/xor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/add-max.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast.gfx6.ll
M llvm/test/CodeGen/AMDGPU/addsub64_carry.ll
M llvm/test/CodeGen/AMDGPU/allow-check.ll
M llvm/test/CodeGen/AMDGPU/amd.endpgm.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-break-large-phis.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
M llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
M llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-max-pregfx12.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_cond.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/barrier-elimination-gfx12.ll
M llvm/test/CodeGen/AMDGPU/barrier-elimination.ll
M llvm/test/CodeGen/AMDGPU/bfi_int.ll
M llvm/test/CodeGen/AMDGPU/bitop3-shared-operand.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/bypass-div.ll
M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-c-function.ll
M llvm/test/CodeGen/AMDGPU/call-constant.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/call-defs-mode-register.ll
M llvm/test/CodeGen/AMDGPU/call-encoding.ll
M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
M llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-return-types.ll
M llvm/test/CodeGen/AMDGPU/call-skip.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callbr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
M llvm/test/CodeGen/AMDGPU/cc-inreg-sgpr0-3-mismatch.ll
M llvm/test/CodeGen/AMDGPU/check-subtarget-features.ll
M llvm/test/CodeGen/AMDGPU/clmul.ll
M llvm/test/CodeGen/AMDGPU/cluster-dims.ll
M llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll
A llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
M llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll
M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ctpop.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cube.ll
M llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll
M llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
A llvm/test/CodeGen/AMDGPU/fence-barrier-latency.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
M llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
M llvm/test/CodeGen/AMDGPU/fmed3.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll
M llvm/test/CodeGen/AMDGPU/fminnum.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs-v2f32.ll
M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-image-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-flat-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-global-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpenv.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
M llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll
M llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/global-address.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/gws_agpr.ll
A llvm/test/CodeGen/AMDGPU/i128-add-carry-chain.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/intrinsic-amdgcn-s-alloc-vgpr.ll
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/invariant-image-load.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/lds-barrier-memoperand.ll
M llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll
M llvm/test/CodeGen/AMDGPU/lds-size.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.addrspacecast.nonnull.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitreplicate.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load-last-use.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.lds.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.flat.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-agent.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-basic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-singlethread.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-system.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-wavefront.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-workgroup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f32.fp8.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.e5m3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.off.f32.i4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.add.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.append.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.async.barrier.arrive.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.fi.b32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.consume.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-bundle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add-errors.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx11.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.sub.gs.reg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f16.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.err.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.tr-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.flt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.direct.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.param.load.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.async.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.i24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.u24.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.pk.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.bcast.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.down.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.idx.gen.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.up.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.prng.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.m0.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.get.waveid.in.workgroup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.monitor.sleep.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.nop.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.inc.wg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.ttracedata.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
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M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1251.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id-unsupported-calling-convention.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.modf.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/load-range-metadata-sign-bits.ll
M llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-nontemporal-metadata.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-opt.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/lrint.ll
M llvm/test/CodeGen/AMDGPU/lround.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/make-buffer-rsrc-lds-fails.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/med3-knownbits.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll
M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
M llvm/test/CodeGen/AMDGPU/memset-pattern.ll
M llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx942.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/minmax.ll
A llvm/test/CodeGen/AMDGPU/mir-dynamic-vgpr-block-size-roundtrip.mir
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
M llvm/test/CodeGen/AMDGPU/nor-divergent-lanemask.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/overlapping-tuple-copy-implicit-op-failure.ll
M llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll
M llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/ptr-buffer-alias-scheduling.ll
M llvm/test/CodeGen/AMDGPU/read-register-invalid-register.ll
M llvm/test/CodeGen/AMDGPU/read_register.ll
M llvm/test/CodeGen/AMDGPU/readcyclecounter.ll
M llvm/test/CodeGen/AMDGPU/readsteadycounter.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
M llvm/test/CodeGen/AMDGPU/ret.ll
M llvm/test/CodeGen/AMDGPU/returnaddress.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/s-barrier.ll
M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-global.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-scratch.ll
M llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll
M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
M llvm/test/CodeGen/AMDGPU/scratch-pointer-sink.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/sgpr-count-graphics.ll
M llvm/test/CodeGen/AMDGPU/shlN_add.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-block.ll
M llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll
A llvm/test/CodeGen/AMDGPU/spillv16Kernel.mir
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/stackguard.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.invalid.ll
M llvm/test/CodeGen/AMDGPU/store-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/store-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/store-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll
M llvm/test/CodeGen/AMDGPU/swizzle.bit.extract.ll
M llvm/test/CodeGen/AMDGPU/tail-call-amdgpu-gfx.ll
A llvm/test/CodeGen/AMDGPU/target-id-xnack-always-on.ll
M llvm/test/CodeGen/AMDGPU/target-mem-intrinsic-metadata.ll
M llvm/test/CodeGen/AMDGPU/trans-coexecution-hazard.mir
M llvm/test/CodeGen/AMDGPU/trap.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/unaligned-buffer.ll
M llvm/test/CodeGen/AMDGPU/unsupported-cs-chain.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/wmma-coexecution-valu-hazards.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll
M llvm/test/CodeGen/AMDGPU/write-register-invalid-register.ll
M llvm/test/CodeGen/AMDGPU/write_register.ll
M llvm/test/CodeGen/ARM/atomic-load-store.ll
A llvm/test/CodeGen/ARM/machine-outliner-thunk-tcgpr.mir
A llvm/test/CodeGen/BPF/jump_table_func_ptr_array.ll
A llvm/test/CodeGen/DirectX/ResourceAccess/load-constant-buffer-t.ll
M llvm/test/CodeGen/Hexagon/print-pipeline-passes.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
M llvm/test/CodeGen/PowerPC/clmul-vector.ll
M llvm/test/CodeGen/PowerPC/ucmp.ll
M llvm/test/CodeGen/RISCV/clmul.ll
M llvm/test/CodeGen/RISCV/clmulh.ll
M llvm/test/CodeGen/RISCV/clmulr.ll
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
M llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmul.ll
M llvm/test/CodeGen/RISCV/xcvbitmanip.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-void-call-aggregate-arg.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-large-vector-shader.ll
A llvm/test/CodeGen/SPIRV/instructions/phi-large-vector.ll
A llvm/test/CodeGen/SPIRV/instructions/undef-composite.ll
M llvm/test/CodeGen/Thumb2/cmpxchg.mir
M llvm/test/CodeGen/Thumb2/mve-clmul.ll
M llvm/test/CodeGen/VE/Scalar/atomic.ll
M llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll
M llvm/test/CodeGen/X86/atomic-load-store.ll
M llvm/test/CodeGen/X86/bmi.ll
M llvm/test/CodeGen/X86/bmi2.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/clmul.ll
M llvm/test/CodeGen/X86/legalize-vec-assertzext.ll
A llvm/test/CodeGen/X86/win64-eh-unwindv3-split-large.ll
A llvm/test/ExecutionEngine/JITLink/x86-64/COFF_dllimport_iat.s
M llvm/test/Instrumentation/MemorySanitizer/bmi.ll
M llvm/test/Instrumentation/MemorySanitizer/pdep.ll
M llvm/test/Instrumentation/MemorySanitizer/pext.ll
A llvm/test/MC/AArch64/compact-unwind-force-dwarf.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx13_asm_vop3_dpp16.s
M llvm/test/MC/COFF/seh-unwindv3-inheritance.s
M llvm/test/MC/COFF/seh-unwindv3-large.s
M llvm/test/MC/COFF/seh-unwindv3-nonmirror.s
A llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16-fake.txt
R llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
M llvm/test/MC/MachO/ARM/compact-unwind-armv7k.s
M llvm/test/MC/Mips/mips64r6/invalid.s
A llvm/test/MC/X86/compact-unwind-force-dwarf.s
M llvm/test/Other/new-pm-O0-defaults.ll
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
M llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
M llvm/test/Transforms/IRCE/correct-loop-info.ll
M llvm/test/Transforms/IndVarSimplify/lcssa-preservation.ll
M llvm/test/Transforms/InstCombine/add.ll
M llvm/test/Transforms/InstCombine/alloca-big.ll
M llvm/test/Transforms/InstCombine/and-or-icmps.ll
M llvm/test/Transforms/InstCombine/assume.ll
M llvm/test/Transforms/InstCombine/or.ll
M llvm/test/Transforms/InstCombine/pdep.ll
M llvm/test/Transforms/InstCombine/pext.ll
M llvm/test/Transforms/InstCombine/scmp.ll
M llvm/test/Transforms/InstCombine/select-to-cmp.ll
M llvm/test/Transforms/InstCombine/set.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fma.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maxnum.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minnum.ll
M llvm/test/Transforms/InstCombine/ucmp.ll
M llvm/test/Transforms/InstCombine/zext.ll
M llvm/test/Transforms/LoopUnroll/runtime-loop-multiexit-dom-verify.ll
A llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-constant-ops.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-with-wide-ops-and-casts.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-with-wide-ops-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-with-wide-ops.ll
A llvm/test/Transforms/LoopVectorize/AArch64/vplan-native-outer-loop-wide-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
A llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-memory-op-decisions.ll
M llvm/test/Transforms/LoopVectorize/VPlan/interleave-and-scalarize-only.ll
A llvm/test/Transforms/LoopVectorize/VPlan/scalarize-irregular-type-memops.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-before-after-all.ll
A llvm/test/Transforms/LoopVectorize/VPlan/widen_mem_idioms.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/X86/pr36524.ll
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-scalable-vf1.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-with-uniform-ops.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads.ll
M llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization-2.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/metadata.ll
M llvm/test/Transforms/LoopVectorize/narrow-interleave-groups-scalable-vf.ll
M llvm/test/Transforms/LoopVectorize/narrow-to-single-scalar-widen-gep-scalable.ll
M llvm/test/Transforms/LoopVectorize/pr128062-interleaved-accesses-narrow-group.ll
M llvm/test/Transforms/LoopVectorize/pr47343-expander-lcssa-after-cfg-update.ll
M llvm/test/Transforms/LoopVectorize/pr59319-loop-access-info-invalidation.ll
M llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
M llvm/test/Transforms/LoopVectorize/scalable-assume.ll
M llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/scalable-iv-outside-user.ll
M llvm/test/Transforms/LoopVectorize/scalable-lifetime.ll
M llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll
M llvm/test/Transforms/LoopVectorize/scalable-noalias-scope-decl.ll
M llvm/test/Transforms/LoopVectorize/scalable-reduction-inloop.ll
A llvm/test/Transforms/LoopVectorize/shl-shift-amount-out-of-range-scev.ll
M llvm/test/Transforms/LoopVectorize/single-scalar-cast-minbw.ll
M llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll
M llvm/test/Transforms/LoopVectorize/trip-count-expansion-may-introduce-ub.ll
M llvm/test/Transforms/LoopVectorize/vector-freeze.ll
A llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/version-mem-access.ll
M llvm/test/Transforms/LoopVectorize/vscale-cost.ll
A llvm/test/Transforms/LoopVectorize/widen-call-op-scalar-vector.ll
A llvm/test/Transforms/LowerCommentString/lower-comment-string.ll
M llvm/test/Transforms/PhaseOrdering/X86/madd.ll
M llvm/test/Transforms/PhaseOrdering/X86/sad.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
A llvm/test/Transforms/Reassociate/reassociate-distribute.ll
A llvm/test/Transforms/RelLookupTableConverter/AArch64/no_relative_lookup_table.ll
M llvm/test/Transforms/RelLookupTableConverter/unnamed_addr.ll
A llvm/test/Transforms/SCCP/implicit-ref-propagation.ll
A llvm/test/Transforms/SLPVectorizer/X86/insertvalue-reordered-operands.ll
A llvm/test/Transforms/SLPVectorizer/X86/reduced-value-replace-extractelement-cost.ll
A llvm/test/Transforms/SLPVectorizer/X86/revec-ordered-reductions.ll
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
M llvm/test/Transforms/SLPVectorizer/revec.ll
A llvm/test/Transforms/SimplifyCFG/AArch64/two-entry-phi-fold-unpredictable.ll
M llvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
M llvm/test/Transforms/VectorCombine/AArch64/partial-reduce-crash.ll
M llvm/test/Transforms/VectorCombine/AArch64/shuffle-of-intrinsics.ll
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
M llvm/test/Transforms/VectorCombine/RISCV/shuffle-of-intrinsics.ll
M llvm/test/Transforms/VectorCombine/X86/extract-binop-inseltpoison.ll
M llvm/test/Transforms/VectorCombine/X86/extract-binop.ll
A llvm/test/Transforms/VectorCombine/X86/shuffle-chain-reduction-subvector.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-chain-reduction-umin.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-intrinsics.ll
M llvm/test/Transforms/VectorCombine/fold-shuffle-chains-to-reduce.ll
M llvm/test/Verifier/nofpclass-metadata.ll
A llvm/test/Verifier/nonnull-metadata.ll
R llvm/test/Verifier/nonnull_metadata.ll
A llvm/test/Verifier/noundef-metadata.ll
R llvm/test/Verifier/range-1.ll
A llvm/test/Verifier/range-metadata.ll
A llvm/test/tools/dsymutil/X86/fat-multiarch-parallel-link.test
M llvm/test/tools/llubi/assume_invalid_align.ll
M llvm/test/tools/llubi/controlflow.ll
M llvm/test/tools/llubi/intr_vector_manip.ll
M llvm/test/tools/llubi/invoke_poison.ll
M llvm/test/tools/llubi/metadata.ll
A llvm/test/tools/llubi/verify.ll
M llvm/test/tools/llvm-cov/coverage-prefix-map.test
M llvm/test/tools/llvm-cov/directory_coverage.test
M llvm/test/tools/llvm-cov/multithreaded-report.test
M llvm/test/tools/llvm-cov/sources-specified.test
A llvm/test/tools/llvm-mca/AArch64/Cortex/A55-in-order-bottleneck-analysis.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/A57-direct-branch.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/A57-forwarding.s
A llvm/test/tools/llvm-mca/AArch64/Cortex/A57-shifted-register.s
R llvm/test/tools/llvm-mca/AArch64/Cortex/direct-branch.s
R llvm/test/tools/llvm-mca/AArch64/Cortex/forwarding-A57.s
R llvm/test/tools/llvm-mca/AArch64/Cortex/in-order-bottleneck-analysis.s
R llvm/test/tools/llvm-mca/AArch64/Cortex/shifted-register.s
R llvm/test/tools/llvm-objcopy/ELF/compress-debug-sections-zstd-err.test
M llvm/test/tools/llvm-objcopy/ELF/compress-sections-within-segment.s
A llvm/test/tools/llvm-objcopy/ELF/compress-sections-zlib-unsupported.test
A llvm/test/tools/llvm-objcopy/ELF/compress-sections-zstd-unsupported.test
R llvm/test/tools/llvm-objcopy/ELF/decompress-debug-sections-unsupported-zlib.test
A llvm/test/tools/llvm-objcopy/ELF/decompress-sections-unsupported-zlib.test
A llvm/test/tools/llvm-objcopy/ELF/decompress-sections-unsupported-zstd.test
A llvm/test/tools/llvm-objcopy/MachO/linkedit-alignment.test
M llvm/test/tools/llvm-objcopy/MachO/linkedit-order-1.test
M llvm/test/tools/llvm-objcopy/MachO/linkedit-order-2.test
M llvm/test/tools/llvm-objcopy/MachO/symbol-table.test
M llvm/tools/llubi/lib/Interpreter.cpp
M llvm/tools/llubi/llubi.cpp
M llvm/tools/llvm-cov/CodeCoverage.cpp
M llvm/tools/llvm-debuginfod/llvm-debuginfod.cpp
M llvm/tools/llvm-dwarfdump/Statistics.cpp
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
M llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
M llvm/tools/llvm-objdump/SourcePrinter.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp
M llvm/tools/llvm-readobj/DwarfCFIEHPrinter.h
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/tools/llvm-readobj/ObjDumper.h
M llvm/tools/llvm-readobj/llvm-readobj.cpp
M llvm/tools/obj2yaml/elf2yaml.cpp
M llvm/unittests/ADT/APFloatTest.cpp
M llvm/unittests/CMakeLists.txt
M llvm/unittests/DebugInfo/DWARF/DWARFExpressionCompactPrinterTest.cpp
M llvm/unittests/Support/CommandLineTest.cpp
M llvm/unittests/Support/DataExtractorTest.cpp
M llvm/unittests/Support/KnownBitsTest.cpp
M llvm/utils/UpdateTestChecks/common.py
M llvm/utils/docker/build_docker_image.sh
M llvm/utils/gn/build/write_cmake_config.gni
M llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Transforms/IPO/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
M llvm/utils/lit/lit/TestRunner.py
M llvm/utils/lit/lit/main.py
M llvm/utils/lit/lit/run.py
M llvm/utils/lit/tests/filter-failed-delete.py
M llvm/utils/lit/tests/filter-failed-rerun.py
M llvm/utils/lit/tests/filter-failed.py
M llvm/utils/vscode/llvm/README.md
M llvm/utils/yaml-bench/YAMLBench.cpp
M mlir/include/mlir/Dialect/Affine/Analysis/LoopAnalysis.h
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/Bufferization/IR/UnstructuredControlFlow.h
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCompositeOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLOps.td
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/lib/Conversion/PtrToLLVM/PtrToLLVM.cpp
M mlir/lib/Dialect/Affine/Analysis/LoopAnalysis.cpp
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineLoopInvariantCodeMotion.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopTiling.cpp
M mlir/lib/Dialect/Affine/Transforms/LoopUnroll.cpp
M mlir/lib/Dialect/Affine/Transforms/PipelineDataTransfer.cpp
M mlir/lib/Dialect/Affine/Utils/LoopFusionUtils.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/X86/Transforms/VectorContractToAMXDotProduct.cpp
M mlir/lib/ExecutionEngine/CMakeLists.txt
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Analysis/DataFlow/test-staged-analyses.mlir
A mlir/test/Conversion/MemRefToEmitC/memref-with-custom-types.mlir
M mlir/test/Conversion/PtrToLLVM/ptr-to-llvm.mlir
A mlir/test/Dialect/Affine/trip-count.mlir
M mlir/test/Dialect/Arith/one-shot-bufferize-memory-space-invalid.mlir
M mlir/test/Dialect/Bufferization/Transforms/test-one-shot-module-bufferize.mlir
M mlir/test/Dialect/ControlFlow/one-shot-bufferize-invalid.mlir
M mlir/test/Dialect/SCF/one-shot-bufferize-invalid.mlir
M mlir/test/Dialect/SPIRV/IR/composite-ops.mlir
M mlir/test/Dialect/SPIRV/IR/gl-ops.mlir
M mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
M mlir/test/Dialect/X86/AMX/vector-contract-to-tiled-dp.mlir
A mlir/test/Target/LLVMIR/openmp-task-in-reduction.mlir
A mlir/test/Target/LLVMIR/openmp-taskloop-reduction.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
M mlir/test/Target/SPIRV/gl-ops.mlir
M mlir/test/Target/SPIRV/ocl-ops.mlir
M mlir/test/lib/Analysis/TestDataFlowFramework.cpp
M mlir/test/lib/Dialect/Bufferization/TestOneShotModuleBufferize.cpp
M mlir/test/lib/Dialect/Test/CMakeLists.txt
M mlir/test/lib/Dialect/Test/TestDialectInterfaces.cpp
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
M offload/ci/openmp-offload-amdgpu-libc-runtime.py
M offload/libomptarget/device.cpp
M offload/libomptarget/omptarget.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/include/RecordReplay.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/common/src/RPC.cpp
M offload/plugins-nextgen/common/src/RecordReplay.cpp
M offload/plugins-nextgen/level_zero/include/L0CmdListManager.h
M offload/plugins-nextgen/level_zero/include/L0Context.h
M offload/plugins-nextgen/level_zero/include/L0Device.h
M offload/plugins-nextgen/level_zero/include/L0Queue.h
M offload/plugins-nextgen/level_zero/src/L0Context.cpp
M offload/plugins-nextgen/level_zero/src/L0Device.cpp
M offload/plugins-nextgen/level_zero/src/L0Queue.cpp
M offload/test/tools/omp-kernel-replay/record-replay-diff-teams-threads.cpp
M offload/test/tools/omp-kernel-replay/record-replay-diff-threads.cpp
A offload/test/tools/omp-kernel-replay/record-replay-empty-memory.cpp
M offload/tools/kernelreplay/llvm-omp-kernel-replay.cpp
M offload/unittests/OffloadAPI/memory/olMemFill.cpp
M offload/unittests/OffloadAPI/queue/olLaunchHostFunction.cpp
M openmp/docs/design/Runtimes.rst
M openmp/runtime/CMakeLists.txt
M openmp/runtime/cmake/config-ix.cmake
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_config.h.cmake
M openmp/runtime/src/ompd-specific.cpp
M openmp/runtime/src/z_Linux_util.cpp
M orc-rt/include/CMakeLists.txt
A orc-rt/include/orc-rt/InProcessControllerAccess.h
A orc-rt/include/orc-rt/QueueingRunner.h
R orc-rt/include/orc-rt/QueueingTaskDispatcher.h
R orc-rt/include/orc-rt/ScopeExit.h
M orc-rt/include/orc-rt/Session.h
M orc-rt/include/orc-rt/SimplePackedSerialization.h
R orc-rt/include/orc-rt/TaskDispatcher.h
A orc-rt/include/orc-rt/ThreadPoolRunner.h
R orc-rt/include/orc-rt/ThreadPoolTaskDispatcher.h
A orc-rt/include/orc-rt/scope_exit.h
M orc-rt/lib/executor/AllocAction.cpp
M orc-rt/lib/executor/CMakeLists.txt
A orc-rt/lib/executor/InProcessControllerAccess.cpp
R orc-rt/lib/executor/QueueingTaskDispatcher.cpp
M orc-rt/lib/executor/Session.cpp
R orc-rt/lib/executor/TaskDispatcher.cpp
A orc-rt/lib/executor/ThreadPoolRunner.cpp
R orc-rt/lib/executor/ThreadPoolTaskDispatcher.cpp
M orc-rt/unittests/BootstrapInfoTest.cpp
M orc-rt/unittests/CMakeLists.txt
M orc-rt/unittests/CommonTestUtils.h
A orc-rt/unittests/InProcessControllerAccessTest.cpp
M orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
M orc-rt/unittests/NativeDylibManagerTest.cpp
A orc-rt/unittests/QueueingRunnerTest.cpp
R orc-rt/unittests/QueueingTaskDispatcherTest.cpp
R orc-rt/unittests/ScopeExitTest.cpp
M orc-rt/unittests/SessionTest.cpp
M orc-rt/unittests/SimpleNativeMemoryMapSPSCITest.cpp
M orc-rt/unittests/SimpleNativeMemoryMapTest.cpp
M orc-rt/unittests/SimplePackedSerializationTest.cpp
A orc-rt/unittests/ThreadPoolRunnerTest.cpp
R orc-rt/unittests/ThreadPoolTaskDispatcherTest.cpp
A orc-rt/unittests/scope_exit-test.cpp
M polly/test/CodeGen/scop_expander_insert_point.ll
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
M utils/bazel/llvm-project-overlay/openmp/runtime/src/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/kparzysz/m02-locator-frontend
Compare: https://github.com/llvm/llvm-project/compare/6f22cd8aa0af...fd1c4828f509
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