[all-commits] [llvm/llvm-project] 0edada: [RISCV][XCV] Fix incorrect llvm.ctlz lowering to c...

[vitbur via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0edadae062e0e9a2d2f87c2f9f61cfdac7bedb28
      https://github.com/llvm/llvm-project/commit/0edadae062e0e9a2d2f87c2f9f61cfdac7bedb28
  Author: vitbur <vittorioburani at gmail.com>
  Date:   2026-06-18 (Thu, 18 Jun 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/test/CodeGen/RISCV/xcvbitmanip.ll

  Log Message:
  -----------
  [RISCV][XCV] Fix incorrect llvm.ctlz lowering to cv.fl1 (#197288)

Fixes #197006.

The XCVbitmanip pattern `def : PatGpr<ctlz, CV_FL1, i32>;` is
semantically incorrect: `cv.fl1` returns a bit position while
`llvm.ctlz` returns a leading-zero count. They differ by up to 31 on
every non-zero input, miscompiling every use of `__builtin_clz`,
including compiler-rt's `__udivdi3`.

This PR:
- Replaces the pattern with one matching `llvm.ctlz` with
  `is_zero_poison=true`, lowered to `xori (cv.fl1 rs1), 31`.
- Adds explicit `setOperationAction` calls in `RISCVISelLowering.cpp`
  to route `ISD::CTLZ` to generic expansion and keep
  `ISD::CTLZ_ZERO_*` matched by the `.td` pattern.

The companion `def : PatGpr<cttz, CV_FF1, i32>;` is correct as-is
(both return 32 on zero, coincide on non-zero), and is left
untouched.

See the linked issue for the full analysis including a CV32E40P sim
trace showing miscompilation of `__udivdi3` in compiler-rt.



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