[all-commits] [llvm/llvm-project] 19d343: [X86][APX] Remove prefer-ndd-imm tuning (#203758)
Phoebe Wang via All-commits
all-commits at lists.llvm.org
Sun Jun 14 18:09:15 PDT 2026
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 19d343debcbc47b1d9b2e2117a599130c33c547c
https://github.com/llvm/llvm-project/commit/19d343debcbc47b1d9b2e2117a599130c33c547c
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2026-06-15 (Mon, 15 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/test/CodeGen/X86/apx/adc.ll
M llvm/test/CodeGen/X86/apx/add.ll
M llvm/test/CodeGen/X86/apx/and.ll
M llvm/test/CodeGen/X86/apx/cmov.ll
M llvm/test/CodeGen/X86/apx/dec.ll
M llvm/test/CodeGen/X86/apx/imul.ll
M llvm/test/CodeGen/X86/apx/inc.ll
M llvm/test/CodeGen/X86/apx/memfold-no-physreg.ll
M llvm/test/CodeGen/X86/apx/mul-i1024.ll
M llvm/test/CodeGen/X86/apx/neg.ll
M llvm/test/CodeGen/X86/apx/not.ll
M llvm/test/CodeGen/X86/apx/or.ll
M llvm/test/CodeGen/X86/apx/rol.ll
M llvm/test/CodeGen/X86/apx/ror.ll
M llvm/test/CodeGen/X86/apx/sar.ll
M llvm/test/CodeGen/X86/apx/sbb.ll
M llvm/test/CodeGen/X86/apx/shl.ll
M llvm/test/CodeGen/X86/apx/shld.ll
M llvm/test/CodeGen/X86/apx/shr.ll
M llvm/test/CodeGen/X86/apx/shrd.ll
M llvm/test/CodeGen/X86/apx/sub.ll
M llvm/test/CodeGen/X86/apx/xor.ll
M llvm/test/CodeGen/X86/cmp.ll
Log Message:
-----------
[X86][APX] Remove prefer-ndd-imm tuning (#203758)
It turns out NDD's immediate variants perform as good as non-NDD's on
real hardware. Verified both on CPU2017 and CPU2026, the geomean is
around 0 w/ and w/o this change. A few items get up and down due to the
side effect of register live range change caused by the NDD form. No
evidence shows this tuning has improvements or degradations even on
single items.
Assisted-by: Claude Sonnet 4.6
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