[all-commits] [llvm/llvm-project] e5cfc1: [Xtensa] Implement support of the ESP32S2 target. ...

[Andrei Safronov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e5cfc1ec130e9ef61fd64369353253f9da894887
      https://github.com/llvm/llvm-project/commit/e5cfc1ec130e9ef61fd64369353253f9da894887
  Author: Andrei Safronov <andrei.safronov at espressif.com>
  Date:   2026-06-13 (Sat, 13 Jun 2026)

  Changed paths:
    M llvm/include/llvm/TargetParser/XtensaTargetParser.def
    M llvm/include/llvm/TargetParser/XtensaTargetParser.h
    M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
    M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
    M llvm/lib/Target/Xtensa/XtensaFeatures.td
    M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
    M llvm/lib/Target/Xtensa/XtensaOperands.td
    M llvm/lib/Target/Xtensa/XtensaProcessors.td
    M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
    M llvm/lib/Target/Xtensa/XtensaSubtarget.h
    M llvm/test/CodeGen/Xtensa/cpus.ll
    A llvm/test/MC/Xtensa/xtensa-esp32s2-valid.s

  Log Message:
  -----------
  [Xtensa] Implement support of the ESP32S2 target. (#200130)



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