[all-commits] [llvm/llvm-project] 8b0466: [AMDGPU] Enabled GCN trackers (amdgpu-use-amdgpu-t...

Dhruva Chakrabarti via All-commits all-commits at lists.llvm.org
Fri Jun 12 22:26:08 PDT 2026 

  Branch: refs/heads/users/dhruvachak/enable_gcn_trackers
  Home:   https://github.com/llvm/llvm-project
  Commit: 8b0466c1e36a9efd5be5b543cda75304d1885061
      https://github.com/llvm/llvm-project/commit/8b0466c1e36a9efd5be5b543cda75304d1885061
  Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
  Date:   2026-06-13 (Sat, 13 Jun 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/add.vni16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
    M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/abs_i16.ll
    M llvm/test/CodeGen/AMDGPU/add.ll
    M llvm/test/CodeGen/AMDGPU/addrspacecast.ll
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
    M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
    M llvm/test/CodeGen/AMDGPU/div_i128.ll
    M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
    M llvm/test/CodeGen/AMDGPU/extract-subvector.ll
    M llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
    M llvm/test/CodeGen/AMDGPU/fceil64.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmaximum.ll
    M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
    M llvm/test/CodeGen/AMDGPU/fminimum.ll
    M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
    M llvm/test/CodeGen/AMDGPU/freeze.ll
    M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
    M llvm/test/CodeGen/AMDGPU/function-args.ll
    M llvm/test/CodeGen/AMDGPU/function-returns.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
    M llvm/test/CodeGen/AMDGPU/half.ll
    M llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
    M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
    M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2c.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
    M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
    M llvm/test/CodeGen/AMDGPU/machine-scheduler-rematerialization-scoring.mir
    M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
    M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
    M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
    M llvm/test/CodeGen/AMDGPU/maximumnum.ll
    M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
    M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
    M llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll
    M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
    M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
    M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
    M llvm/test/CodeGen/AMDGPU/minimumnum.ll
    M llvm/test/CodeGen/AMDGPU/mul.ll
    M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
    M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
    M llvm/test/CodeGen/AMDGPU/pr51516.mir
    M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
    M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
    M llvm/test/CodeGen/AMDGPU/rem_i128.ll
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
    M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
    M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
    M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
    M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
    M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir
    M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_diff_types.mir
    M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
    M llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit.ll
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll
    M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
    M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
    M llvm/test/CodeGen/AMDGPU/sdiv.ll
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/sema-v-unsched-bundle.ll
    M llvm/test/CodeGen/AMDGPU/shl.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4i64.v4i64.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v4p0.v4p0.ll
    M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
    M llvm/test/CodeGen/AMDGPU/sra.ll
    M llvm/test/CodeGen/AMDGPU/srem.ll
    M llvm/test/CodeGen/AMDGPU/srl.ll
    M llvm/test/CodeGen/AMDGPU/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/stack-realign.ll
    M llvm/test/CodeGen/AMDGPU/uaddsat.ll
    M llvm/test/CodeGen/AMDGPU/udiv.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll
    M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll

  Log Message:
  -----------
  [AMDGPU] Enabled GCN trackers (amdgpu-use-amdgpu-trackers) by default.

The LIT tests have been generally updated in one of the following ways:
(1) If the above option was not present and the test was auto-generated,
the test has now been auto-generated.
(2) If the above option was not present and the test was not
auto-generated, added the option -amdgpu-use-amdgpu-trackers=0 so as to
preserve any specific attributes the test was already checking.
(3) If the above option was present in a test, then its value has been
updated to reflect the change in the default.

Currently, there are 4 tests in category (2). They are:
CodeGen/AMDGPU/
  addrspacecast.ll
  schedule-regpressure-limit.ll
  schedule-regpressure-limit2.ll
  sema-v-unsched-bundle.ll

There are 8 tests in category (3). They are:
CodeGen/AMDGPU/
  schedule-amdgpu-tracker-physreg.ll
  schedule-amdgpu-trackers.ll
  materialize-frame-index-sgpr.ll
  schedule-relaxed-occupancy.ll
  schedule-regpressure-ilp-metric-spills.mir
  pr51516.mir
  high-RP-reschedule.mir
  machine-scheduler-sink-trivial-remats.mir

The rest are in category (1).

This PR is stacked on top of https://github.com/llvm/llvm-project/pull/184275.

Assisted-by: Cursor


  Commit: 16b4a6a50a24be85438e624c30a9aa7aa7dba1ab
      https://github.com/llvm/llvm-project/commit/16b4a6a50a24be85438e624c30a9aa7aa7dba1ab
  Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
  Date:   2026-06-13 (Sat, 13 Jun 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
    M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir

  Log Message:
  -----------
  [AMDGPU] Regenerated tests after rebasing on top of
users/dhruvachak/add_physical_to_gcn_trackers_after_rename.


  Commit: 114363976d4960aef4c93d5b4dbb0610c8da1be3
      https://github.com/llvm/llvm-project/commit/114363976d4960aef4c93d5b4dbb0610c8da1be3
  Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
  Date:   2026-06-13 (Sat, 13 Jun 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll

  Log Message:
  -----------
  [AMDGPU] Adjusted GCN tracker option after rebasing on top of
users/dhruvachak/add_physical_to_gcn_trackers_after_rename.


  Commit: 6949ca2b2d731970f285a8e598e537da7f21d288
      https://github.com/llvm/llvm-project/commit/6949ca2b2d731970f285a8e598e537da7f21d288
  Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
  Date:   2026-06-13 (Sat, 13 Jun 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
    M llvm/test/CodeGen/AMDGPU/abs_i16.ll
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmaximum.ll
    M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
    M llvm/test/CodeGen/AMDGPU/fminimum.ll
    M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
    M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
    M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
    M llvm/test/CodeGen/AMDGPU/maximumnum.ll
    M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
    M llvm/test/CodeGen/AMDGPU/minimumnum.ll
    M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
    M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/shift-i128.ll
    M llvm/test/CodeGen/AMDGPU/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/stack-realign.ll
    M llvm/test/CodeGen/AMDGPU/uaddsat.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-and.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-xor.ll

  Log Message:
  -----------
  [AMDGPU] Regenerated tests after rebasing.


  Commit: e8b43f2a47e5a326bb9085fab665edd05dc5702a
      https://github.com/llvm/llvm-project/commit/e8b43f2a47e5a326bb9085fab665edd05dc5702a
  Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
  Date:   2026-06-13 (Sat, 13 Jun 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
    M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir

  Log Message:
  -----------
  Regenerated tests after rebasing.


  Commit: af4839a9b628051f0fa48d140975d2b72dfb07a5
      https://github.com/llvm/llvm-project/commit/af4839a9b628051f0fa48d140975d2b72dfb07a5
  Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
  Date:   2026-06-13 (Sat, 13 Jun 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
    M llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
    M llvm/test/CodeGen/AMDGPU/indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/live-interval-bug-in-rename-independent-subregs.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir
    M llvm/test/CodeGen/AMDGPU/memory_clause.mir
    M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
    M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
    M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
    M llvm/test/CodeGen/AMDGPU/sibling-call.ll
    M llvm/test/CodeGen/AMDGPU/soft-clause-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
    M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll

  Log Message:
  -----------
  Updated tests because of liveins/liveouts seeding.


Compare: https://github.com/llvm/llvm-project/compare/7327c7426ba1...af4839a9b628

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