[all-commits] [llvm/llvm-project] 2363ec: [AMDGPU] Physical register tracking in GCN trackers.
Dhruva Chakrabarti via All-commits
all-commits at lists.llvm.org
Fri Jun 12 21:19:01 PDT 2026
Branch: refs/heads/users/dhruvachak/add_physical_to_gcn_trackers_after_rename
Home: https://github.com/llvm/llvm-project
Commit: 2363eca9f99ed1e1bb0c32b915ac8d48c144bbe9
https://github.com/llvm/llvm-project/commit/2363eca9f99ed1e1bb0c32b915ac8d48c144bbe9
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/RegisterPressure.h
M llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg-crash.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
A llvm/test/CodeGen/AMDGPU/schedule-gcn-physreg-pressure.ll
Log Message:
-----------
[AMDGPU] Physical register tracking in GCN trackers.
Previously, the GCN tracker only monitored virtual registers, leading to
inaccurate register pressure estimates and sub-optimal scheduling decisions
when physical registers were present. This patch adds support for tracking
physical registers in GCN trackers. Virtual and physical register tracking
are maintained separately. Similar to virtual LiveRegs, physical LiveRegs
are now maintained. The tracking flow closely follows that of the GCN
trackers in the recede, advance, and pressure-increment methods.
Tracking physical registers leads to better register allocation, no more
allocation failures, and more accurate pressure estimates. Existing tests
have been updated to reflect the above. A new test schedule-gcn-physreg-pressure
has been added that validates physical register tracking across multiple
scenarios.
Assisted-by: Cursor
Commit: 5788d0d279739dec459cd445c2ec5a83a3243048
https://github.com/llvm/llvm-project/commit/5788d0d279739dec459cd445c2ec5a83a3243048
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/RegisterPressure.h
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
M llvm/test/CodeGen/AMDGPU/schedule-gcn-physreg-pressure.ll
Log Message:
-----------
[AMDGPU] Used LiveRegUnits for physical register pressure tracking.
Addressed review comments as well.
Commit: 75a60fb82f9751a14f36bb8a2bbacb5c76917a26
https://github.com/llvm/llvm-project/commit/75a60fb82f9751a14f36bb8a2bbacb5c76917a26
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
M llvm/test/CodeGen/AMDGPU/schedule-gcn-physreg-pressure.ll
Log Message:
-----------
[AMDGPU] Addressed reviewer comments.
Make some pressure inc() logic unconditional to match existing code.
Un-invert some logic and naming for regunit management.
Use auto-gen script for new test while maintaining debug messages.
Commit: 061011cf01476ad5da108b82268cb803d0931af3
https://github.com/llvm/llvm-project/commit/061011cf01476ad5da108b82268cb803d0931af3
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/schedule-gcn-physreg-pressure.ll
Log Message:
-----------
Added test for early clobber with a tuple register.
Commit: c897e7702cc3a7b0c33e3658fa4e4be40e43c219
https://github.com/llvm/llvm-project/commit/c897e7702cc3a7b0c33e3658fa4e4be40e43c219
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-tracker-physreg.ll
Log Message:
-----------
Folded multiple RUN lines into one while maintaining debug msgs.
Commit: 670ea40fbdd6b4e2d58453fd2692e19202231b47
https://github.com/llvm/llvm-project/commit/670ea40fbdd6b4e2d58453fd2692e19202231b47
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
Log Message:
-----------
Added early clobber support to physical register tracking.
Commit: 7ad2c298809010c55776acfb94a18a191ea7a7ce
https://github.com/llvm/llvm-project/commit/7ad2c298809010c55776acfb94a18a191ea7a7ce
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
A llvm/test/CodeGen/AMDGPU/regpressure-physreg-early-clobber.mir
Log Message:
-----------
Added a new test for physical register early clobber.
Commit: 502fb6866c23dc3ae09a4e8d0f499e7a6ae11eff
https://github.com/llvm/llvm-project/commit/502fb6866c23dc3ae09a4e8d0f499e7a6ae11eff
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
Log Message:
-----------
Added an SIRegisterInfo member to GCNRPTracker and its uses.
Commit: 357ace7dc88476ced9d46eb37b7f6a0eea36d5e9
https://github.com/llvm/llvm-project/commit/357ace7dc88476ced9d46eb37b7f6a0eea36d5e9
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
Log Message:
-----------
Removed invert.
Commit: 1e6b5b70df98ee929a19c74f2bdc50fc96431791
https://github.com/llvm/llvm-project/commit/1e6b5b70df98ee929a19c74f2bdc50fc96431791
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/schedule-gcn-physreg-pressure.ll
Log Message:
-----------
Unified GCNRegPressure objects for virtual and physical.
Augmented physical live register representation.
Commit: 9d1e1259f154f289e1252b31b2e63a8314f9b591
https://github.com/llvm/llvm-project/commit/9d1e1259f154f289e1252b31b2e63a8314f9b591
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
Log Message:
-----------
Always clear PhysLiveRegs even when TrackPhysRegs is false.
Added debug output if assert fails.
Commit: ff3a00298aa18649eb303a0a0cfa34ce6408a7cd
https://github.com/llvm/llvm-project/commit/ff3a00298aa18649eb303a0a0cfa34ce6408a7cd
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
Log Message:
-----------
clang-format fix.
Commit: d8b6fc0e5e84ce15bf9a7a396d36b5f8a9ddaf77
https://github.com/llvm/llvm-project/commit/d8b6fc0e5e84ce15bf9a7a396d36b5f8a9ddaf77
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
Log Message:
-----------
Updated remove() method to ensure registers and units are in sync.
If there is aliasing between 2 entries in physical register tracker,
the remove method for one of those registers may remove regunits
that correspond to the other entry that is still in the tracker. This
produces an inconsistency. This patch fixes this problem by first
removing the register/units but then reconstructing the units from
the remaining registers that are present in the tracker.
Commit: b4f8fcd4f7756d6b00edaa8e3a1a898457556c05
https://github.com/llvm/llvm-project/commit/b4f8fcd4f7756d6b00edaa8e3a1a898457556c05
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
Log Message:
-----------
Added comments on limitations of physical register tracking.
Commit: 14962991178ae273bbaf3ba7a7deb16ad1c3a1f3
https://github.com/llvm/llvm-project/commit/14962991178ae273bbaf3ba7a7deb16ad1c3a1f3
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
Log Message:
-----------
Use inc/dec.
Commit: 323b0a1101fbf6a926c774da57888d539154dcc4
https://github.com/llvm/llvm-project/commit/323b0a1101fbf6a926c774da57888d539154dcc4
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
Log Message:
-----------
Added helper shouldTrackPhysReg.
Commit: 037b27f9b76a9eb8420ff023e10e6722f4e8d426
https://github.com/llvm/llvm-project/commit/037b27f9b76a9eb8420ff023e10e6722f4e8d426
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
A llvm/test/CodeGen/AMDGPU/regpressure-physreg-limits.mir
Log Message:
-----------
Added new test for physical register isAllocatable and aliasing.
Commit: 2fe69874c02f980520c97f2b84563039a7e16044
https://github.com/llvm/llvm-project/commit/2fe69874c02f980520c97f2b84563039a7e16044
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
Log Message:
-----------
Addressed review comments.
- Reverted unintended comment removal.
- Fixed compiler warnings in NDEBUG mode.
- Removed unused method getVirtLiveRegs, kept pre-existing getLiveRegs.
Commit: 1f43a8d6fba0ffd1e819f2ec9843099be4f56457
https://github.com/llvm/llvm-project/commit/1f43a8d6fba0ffd1e819f2ec9843099be4f56457
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
Log Message:
-----------
Added PhysicalRegLiveness ctor, removed conditional init.
Commit: 29f397ff369a2d581f5382b6ce6f8f2771c5f22e
https://github.com/llvm/llvm-project/commit/29f397ff369a2d581f5382b6ce6f8f2771c5f22e
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
Log Message:
-----------
Addressed review comments.
- Removed copy ctor.
- Removed isReg() query for all_uses().
- Simplify code by using isAnyRegUnitNotLive.
Commit: a26bdd263b8a335b84260aeba44f1448d4bd5a20
https://github.com/llvm/llvm-project/commit/a26bdd263b8a335b84260aeba44f1448d4bd5a20
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
M llvm/test/CodeGen/AMDGPU/regpressure-physreg-limits.mir
M llvm/test/CodeGen/AMDGPU/schedule-gcn-physreg-pressure.ll
Log Message:
-----------
Remove tracking of registers from physical GCN tracker.
The tracker is now just a bitvector.
All tracking is now at the regunit level, handling aliasing accurately.
Tuple and raw pressure are adjusted by the same delta.
Updated tests accordingly.
Commit: 878f803d14af233b6e154c8ed32365019abd9542
https://github.com/llvm/llvm-project/commit/878f803d14af233b6e154c8ed32365019abd9542
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/regpressure-physreg-limits.mir
A llvm/test/CodeGen/AMDGPU/sched-physreg-liveins.mir
Log Message:
-----------
Adds support for physical register liveins/liveouts in GCN trackers.
Commit: 40b3190112ca2cfd2c7c8da6681220e4d19c5273
https://github.com/llvm/llvm-project/commit/40b3190112ca2cfd2c7c8da6681220e4d19c5273
Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
Log Message:
-----------
Fixed rebase.
Compare: https://github.com/llvm/llvm-project/compare/d701e398acdf...40b3190112ca
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