[all-commits] [llvm/llvm-project] f3105e: [arm64e][cfi] .cfi_negate_ra_state is irrelevant f...
Alexander Richardson via All-commits
all-commits at lists.llvm.org
Fri Jun 12 17:38:31 PDT 2026
Branch: refs/heads/users/arichardson/spr/tablegen-support-hwmode-registers-in-compressinstemitter
Home: https://github.com/llvm/llvm-project
Commit: f3105e22dc292dc1b2d91c80edbc169d77f91bdd
https://github.com/llvm/llvm-project/commit/f3105e22dc292dc1b2d91c80edbc169d77f91bdd
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/test/CodeGen/AArch64/arm64e-tail-call-autib.ll
Log Message:
-----------
[arm64e][cfi] .cfi_negate_ra_state is irrelevant for Mach-O platforms (#203076)
The arm64e unwinder on Mach-O platforms always assumes saved LR's have
been signed with a pacibsp, and does not support mixed signed and
un-signed frames. Since the unwinder behaves the same whether the
directive is present, it is better to avoid emitting it in the first
place. This aligns with the behavior of AppleClang.
rdar://178084701
Commit: 9bece3b7dc3bb184ae3e6f1bdc4a864a096a6d68
https://github.com/llvm/llvm-project/commit/9bece3b7dc3bb184ae3e6f1bdc4a864a096a6d68
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLOps.td
M mlir/test/Dialect/SPIRV/IR/gl-ops.mlir
M mlir/test/Target/SPIRV/gl-ops.mlir
Log Message:
-----------
[mlir][SPIR-V] Add GL atan2 op (#201927)
Commit: 9ce63d09cff0bf07da9623b753010112db87b1d7
https://github.com/llvm/llvm-project/commit/9ce63d09cff0bf07da9623b753010112db87b1d7
Author: carlobertolli <carlo.bertolli at amd.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Analysis/ScalarEvolution/shift-op.ll
Log Message:
-----------
[AMDGPU][SCEV] Tighten max backedge-taken count for shift recurrence loops. (#197292)
Application code on AMDGPUs often uses the following pattern:
for (int i = blockDim.x / 2; i >= 1; i >>= 1)
if (threadIdx.x < i) {
<STMT based on threadIdx.x>
}
__syncthreads();
}
but this is currently not unrolled by LLVM for two reasons:
1. We overestimate the loop count with the number of bits in the
iteration variable (32).
2. Runtime unrolling is not applicable because of convergent
instructions.
For the specific pattern above, we can compute a tighter bound by using
range information, which for blockDim.x is (0,1025) and already emitted
by clang, resulting in 10 as upper bound as opposed to 32.
The next step in unrolling the loop is to adjust the threshold used to
control full loop unrolling with convergent instructions.
Assisted-by: Cursor
Commit: dfa5d20f7a0c7eefaf3c0a267b0971d1ea692394
https://github.com/llvm/llvm-project/commit/dfa5d20f7a0c7eefaf3c0a267b0971d1ea692394
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/wmma-coexecution-valu-hazards.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
A llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1251-w32.mir
Log Message:
-----------
[AMDGPU] Handle gfx1251 wmma hazard (#203145)
Generic target affected too in a pessimistic way.
Commit: d109c2ed9d5b456c3cfca8f74a6d26e2a2ec36c4
https://github.com/llvm/llvm-project/commit/d109c2ed9d5b456c3cfca8f74a6d26e2a2ec36c4
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
Log Message:
-----------
[VPlan] Remove type verification from VPlanVerifier (NFC) (#201209)
With https://github.com/llvm/llvm-project/pull/200692
and https://github.com/llvm/llvm-project/pull/200686, types are no
checked at construction, and each operation that changes operands
(setOperand, addOperand etc) verifies that the replacement happens with
suitable types.
This should remove the need for running type checking as part of the
verifier.
PR: https://github.com/llvm/llvm-project/pull/201209
Commit: 229383a74eed0bc4f610713b9bd6ac7b6a152ef5
https://github.com/llvm/llvm-project/commit/229383a74eed0bc4f610713b9bd6ac7b6a152ef5
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
R clang/include/clang/Basic/AtomicLineLogger.h
R clang/lib/Basic/AtomicLineLogger.cpp
M clang/lib/Basic/CMakeLists.txt
R clang/unittests/Basic/AtomicLineLoggerTest.cpp
M clang/unittests/Basic/CMakeLists.txt
Log Message:
-----------
Revert "[clang] Reland Adding an Atomic Line Logger (#195885)" (#203366)
Reverts llvm/llvm-project#202428 as it is causing sanitizer failures.
Details at
https://github.com/llvm/llvm-project/pull/202428#issuecomment-4683845844.
Commit: 7a1f3d768041742b1d7988ca7df65fade9bff713
https://github.com/llvm/llvm-project/commit/7a1f3d768041742b1d7988ca7df65fade9bff713
Author: Fabrice de Gans <Steelskin at users.noreply.github.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M .github/workflows/ids-check.yml
Log Message:
-----------
[ids-check] Re-enable the workflow (#203325)
Following earlier changes, the workflow should now only affect modified
headers.
The effort to build LLVM as a shared library is tracked in #109483.
Commit: 5f4e81c81be73304ae2dd87da366aac11debd9df
https://github.com/llvm/llvm-project/commit/5f4e81c81be73304ae2dd87da366aac11debd9df
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M libc/src/time/CMakeLists.txt
M libc/src/time/asctime.cpp
M libc/src/time/asctime_r.cpp
M libc/src/time/ctime.cpp
M libc/src/time/ctime_r.cpp
M libc/src/time/gmtime.cpp
M libc/src/time/gmtime_r.cpp
M libc/src/time/localtime.cpp
M libc/src/time/localtime_r.cpp
M libc/src/time/mktime.cpp
M libc/src/time/strftime.cpp
M libc/src/time/strftime_core/CMakeLists.txt
M libc/src/time/strftime_core/composite_converter.h
M libc/src/time/strftime_core/converter.h
M libc/src/time/strftime_core/num_converter.h
M libc/src/time/strftime_core/str_converter.h
M libc/src/time/strftime_l.cpp
M libc/src/time/time_utils.cpp
M libc/src/time/time_utils.h
M libc/test/src/time/asctime_r_test.cpp
M libc/test/src/time/asctime_test.cpp
M libc/test/src/time/ctime_r_test.cpp
M libc/test/src/time/ctime_test.cpp
M libc/test/src/time/gmtime_r_test.cpp
M libc/test/src/time/gmtime_test.cpp
M libc/test/src/time/localtime_r_test.cpp
M libc/test/src/time/localtime_test.cpp
M libc/test/src/time/mktime_test.cpp
Log Message:
-----------
[libc] Complete hardening of time functions and remove Y2038 limit (#203298)
Completed safety and hardening refactoring for time functions, and
removed Y2038 limitation:
* Hardening: Refactored update_from_seconds to return ErrorOr<int>
(instead of int64_t status, as it only returns status 0 or error)
and propagated it to entrypoints. Added LIBC_CRASH_ON_NULLPTR to public
boundaries and converted tests to death tests using SIGILL.
* Y2038: Removed the artificial int32_t max check from ctime and
ctime_r, allowing them to support timestamps beyond 2038 (up to Year
9999).
* Tests: Updated ctime/ctime_r tests to include Year 2039 test cases and
updated overflow test cases to Year 10000.
* Style: Fixed header blocks and added Doxygen comments in converter.h,
str_converter.h, and time_utils.h.
* Conventions: Fixed relative includes in converter.h and time_utils.h.
Assisted-by: Automated tooling, human reviewed.
Commit: 53c483660a7a85884b4d161efa3a86a337d2e3a2
https://github.com/llvm/llvm-project/commit/53c483660a7a85884b4d161efa3a86a337d2e3a2
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 123078c (#203205)
This fixes 123078c21cfbe4c6abe1052e53739f9e933e8c1d.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: b0c7a44b9b8dbfa1c2cb30c6f9c94fcc90a4f090
https://github.com/llvm/llvm-project/commit/b0c7a44b9b8dbfa1c2cb30c6f9c94fcc90a4f090
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M bolt/docs/profiles.md
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/X86/pre-aggregated-records.s
M bolt/unittests/Profile/DataAggregator.cpp
Log Message:
-----------
[BOLT] Make mispreds optional for preagg B/T/R records (#202856)
Extend pre-aggregated format with an optional mispredictions field.
Update parsing and pre-aggregated profile writer.
Test Plan:
added PreAggregatedX86TestHelper.OptionalMispredField
updated pre-aggregated-records.s
Commit: 3b267d20846c8dc861fc302c1ac9a6d45d67aa02
https://github.com/llvm/llvm-project/commit/3b267d20846c8dc861fc302c1ac9a6d45d67aa02
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
Log Message:
-----------
[flang][OpenMP] Simplify code by using common functions, NFC (#203373)
Commit: c6a51bab81e5637201d54d680654562a6936a618
https://github.com/llvm/llvm-project/commit/c6a51bab81e5637201d54d680654562a6936a618
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/induction-cost.ll
Log Message:
-----------
[LV] Add cost tests for induction recipes (NFC). (#203376)
Commit: e08481e61f4bff102079aead3f442a572ceb1034
https://github.com/llvm/llvm-project/commit/e08481e61f4bff102079aead3f442a572ceb1034
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
Log Message:
-----------
[AMDGPU] Add FeatureFullRate64Ops to gfx1251 (#203368)
Commit: 08f2c2808b8115a29cf57d59d3673c1430a7dbf4
https://github.com/llvm/llvm-project/commit/08f2c2808b8115a29cf57d59d3673c1430a7dbf4
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/perf2bolt/perf_brstack.test
Log Message:
-----------
[BOLT] Parse branch type from perf script
Parse branch type and set `IsReturn` when using perf data input.
This makes profile attaching more accurate for external returns.
Test Plan: updated perf_brstack.test
Reviewers: maksfb, rafaelauler, yozhu, ayermolo, yavtuk, paschalis-mpeis
Reviewed By: yozhu
Pull Request: https://github.com/llvm/llvm-project/pull/202813
Commit: b0f7e00e723d2ebea7c80b246391599d55271aea
https://github.com/llvm/llvm-project/commit/b0f7e00e723d2ebea7c80b246391599d55271aea
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/test/Transforms/InstSimplify/fold-intrinsics.ll
Log Message:
-----------
[InstSimplify] Const-fold clmul (#203346)
Commit: cdf2804105b223b5729bc8a3dea5e6d06c5cc5c9
https://github.com/llvm/llvm-project/commit/cdf2804105b223b5729bc8a3dea5e6d06c5cc5c9
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
Log Message:
-----------
[VPlan] Clean up code around getFMFOrNone (NFC) (#202954)
Commit: 790938d0204af8307d7d37b3e10caef27b3d527f
https://github.com/llvm/llvm-project/commit/790938d0204af8307d7d37b3e10caef27b3d527f
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/test/CodeGenHLSL/ArrayAssignable.hlsl
M clang/test/CodeGenHLSL/ArrayAssignable.logicalptr.hlsl
M clang/test/CodeGenHLSL/cbuffer-matrix-layout-keyword.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer-empty-struct-array.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_and_namespaces.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_with_packoffset.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_with_static_global_and_function.hlsl
M clang/test/CodeGenHLSL/resources/default_cbuffer.hlsl
M clang/test/CodeGenHLSL/resources/default_cbuffer_with_layout.hlsl
M llvm/include/llvm/Frontend/HLSL/CBuffer.h
M llvm/lib/Frontend/HLSL/CBuffer.cpp
M llvm/lib/Target/DirectX/DXILCBufferAccess.cpp
M llvm/lib/Target/SPIRV/SPIRVCBufferAccess.cpp
A llvm/test/CodeGen/DirectX/cbuffer_global_elim.ll
A llvm/test/CodeGen/SPIRV/cbuffer_global_elim.ll
Log Message:
-----------
[HLSL] Set visibility of cbuffer global variables to internal (2nd attempt) (#202745)
Global variables for all resources except `cbuffer` are already emitted
with internal linkage (since #166844).
This change adds internal linkage to the `cbuffer` handle globals as
well.
One problem is that the `cbuffer` handle globals appears unused between
Clang CodeGen and `{DXIL|SPIRV}CBufferAccess` pass, which replaces
individual `cbuffer` constant globals with accesses through the
`cbuffer` handle globals. Before this pass runs, the unused globals
could get optimized away in `GlobalOptPass` with `-O3`.
To solve this, the `cbuffer` handle globals are added to the
`@llvm.compiler.used` list to make sure they stay in the module until
the `{DXIL|SPRIV}CBufferAccess` pass, which then removes them from the
list.
This is a second attempt to land this change. The [first
one](https://github.com/llvm/llvm-project/pull/200312) had to be
reverted because the use of `llvm::removeFromUsedList` introduced a
cyclic dependency between `LLVMTransformUtils` and `LLVMFrontendHLSL`.
This change fixes this by calling `llvm::removeFromUsedList` directly
from the passes.
Commit: 27dc2ec9b323edbb76e56388dbc8064a5109f430
https://github.com/llvm/llvm-project/commit/27dc2ec9b323edbb76e56388dbc8064a5109f430
Author: Shubh Pachchigar <33875085+shubhe25p at users.noreply.github.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M libc/src/__support/str_to_integer.h
M libc/test/src/__support/str_to_integer_test.cpp
M libc/test/src/stdlib/StrtolTest.h
M libc/test/src/wchar/WcstolTest.h
Log Message:
-----------
[libc] Add C23 binary prefix support to strtointeger (#202243)
The C23 standard (N3220 §7.24.1.7) requires strtol and related functions
to recognize the 0b/0B prefix when base is 2 or 0. This change
implements that support and adds relevant tests.
Assisted by: Claude Sonnet 4.6 for generating and understanding Tests.
Co-authored-by: shubhe25p <shubhp at Mac.lan>
Commit: 84e6eb8ae98ddd3fdabbad5ab2ae0bc1cdcba706
https://github.com/llvm/llvm-project/commit/84e6eb8ae98ddd3fdabbad5ab2ae0bc1cdcba706
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/AttrDocs.td
M llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/modular-format.ll
M llvm/test/Verifier/modular-format.ll
Log Message:
-----------
[LLVM][InstCombine] Add fixed-point aspect to modular printf attribute (#202425)
This commit adds support for the "fixed" aspect inside LLVM's modular
printf optimizer pass (InstCombineCalls.cpp). It implements a targeted
format string parser that scans constant format strings for "%r, %R, %k,
%K" specifiers to resolve if the "fixed" aspect is needed, falling back
to conservatively assumed needed if the format string is dynamic.
This commit also adds missing Verifier checks for modular-format,
including those that guard the parts of its syntax that are newly used
by this change.
Generated by Gemini; reviewed and edited manually.
Commit: b57c32db810bb8619220591224b4a71bc2d4b40d
https://github.com/llvm/llvm-project/commit/b57c32db810bb8619220591224b4a71bc2d4b40d
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/CMakeLists.txt
A lldb/source/Plugins/Process/Windows/Common/ExceptionRecord.cpp
M lldb/source/Plugins/Process/Windows/Common/ExceptionRecord.h
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
Log Message:
-----------
[lldb][Windows] Append access-violation detail to lldb-server stop description (#203301)
`lldb-server.exe` reports access violations with only the bare exception
code (e.g. `Exception 0xc0000005 encountered at address 0x...`), while
the in-process Windows debugger produces the much more useful `Access
violation
reading location 0x...` / `writing` / `DEP at` form.
This patch lifts the in process helper into a method of the
`ExceptionRecord` class to allow both Windows plugins to use it.
This fixes `exception_access_violation.cpp` with
`LLDB_USE_LLDB_SERVER=1`.
rdar://179366768
Commit: 8c64020b2397fc5dddd577276020cbb30cdbc6cc
https://github.com/llvm/llvm-project/commit/8c64020b2397fc5dddd577276020cbb30cdbc6cc
Author: Zhaoxuan Jiang <jiangzhaoxuan94 at gmail.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M lld/MachO/BPSectionOrderer.cpp
M lld/MachO/Driver.cpp
M lld/MachO/ICF.cpp
M lld/MachO/InputFiles.cpp
M lld/MachO/InputSection.h
M lld/MachO/SectionPriorities.cpp
M lld/MachO/SymbolTable.cpp
M lld/MachO/SymbolTable.h
M lld/MachO/Symbols.cpp
M lld/MachO/Symbols.h
M lld/MachO/SyntheticSections.cpp
M lld/MachO/Writer.cpp
A lld/test/MachO/bp-section-orderer-cold.s
A lld/test/MachO/cold-func-weak-merge.s
A lld/test/MachO/cold-func.s
Log Message:
-----------
[lld][MachO] Add N_COLD_FUNC support (#183909)
Parse `N_COLD_FUNC` from input object files and use it to move cold
functions to the end of __text, after all non-cold and ordered symbols.
Key behaviors:
- Cold functions are placed after all non-cold unordered symbols.
- Order file entries take precedence over the cold attribute: a cold
function listed in the order file retains its specified position.
- BP interaction: utilize the subgrouping introduced in #185661 to split
`N_COLD_FUNC` sections into a distinct subgroup.
- ICF interaction: when a non-cold section is folded into a cold master,
the master's coldness is unset. With safe_thunks, cold
address-significant functions get cold thunks placed in the cold region.
- The `N_COLD_FUNC` flag is stripped from the output symbol table.
Commit: 1d8dc059d8e183e95ab71e162f1b47aca659971b
https://github.com/llvm/llvm-project/commit/1d8dc059d8e183e95ab71e162f1b47aca659971b
Author: Aayush Shrivastava <iamaayushrivastava at gmail.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Fix crash on assert !Scopes.empty() in parseBrace() (#199100)
Fixes #199017
When angle-bracket parsing fails and resets the token stream, a closing
brace can be consumed twice through `parseConditional()`, each time
popping one entry from Scopes. This leaves Scopes empty when
`parseBrace()` encounters the legitimate closing brace, triggering the
assertion.
Replace the assert with a graceful return false, consistent with the
existing unbalanced-brace handling in `consumeToken()`.
Commit: 99ecce0d4adacbe71cce8e27e427011c76ead17f
https://github.com/llvm/llvm-project/commit/99ecce0d4adacbe71cce8e27e427011c76ead17f
Author: Christopher Di Bella <cjdb at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/invalid-vector/TestDataFormatterLibcxxInvalidVectorSimulator.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/invalid-vector/main.cpp
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/vector/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/vector/TestDataFormatterLibcxxVectorSimulator.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/vector/main.cpp
Log Message:
-----------
Teach LLDB's pretty-printer about libc++'s various `std::vector` layouts (#202438)
PR #155330 changes `std::vector` from unconditionally using three
pointers to represent its layout to potentially using three pointers or
a begin pointer and two integers. This commit changes LLDB so that it
can robustly work with the legacy vector layout, the new pointer layout,
and the new size-based layout.
Commit: 57d06749766b6e99ee52fdfd874ead83595ad505
https://github.com/llvm/llvm-project/commit/57d06749766b6e99ee52fdfd874ead83595ad505
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M clang/test/CIR/CodeGen/bind-temporary-lvalue.cpp
Log Message:
-----------
[CIR] Fix bind-temporary-lvalue test (#203391)
This test was merged with checks for the old alloca format
Commit: fafc55b27f8b68279f9b32968ef903ddfccd3a62
https://github.com/llvm/llvm-project/commit/fafc55b27f8b68279f9b32968ef903ddfccd3a62
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
A llvm/test/CodeGen/AMDGPU/packed-fp64.ll
A llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1251_err.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
Log Message:
-----------
[AMDGPU] Add gfx1251 V_PK_ADD_F64 (#203382)
Commit: 8449a84b770b0ae15eb6b7595ea93c93323e6ac2
https://github.com/llvm/llvm-project/commit/8449a84b770b0ae15eb6b7595ea93c93323e6ac2
Author: Alexey Bader <alexey.bader at intel.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M clang/docs/ClangSYCLLinker.rst
A clang/test/OffloadTools/clang-sycl-linker/archive-extras.ll
M clang/test/OffloadTools/clang-sycl-linker/basic.ll
M clang/test/OffloadTools/clang-sycl-linker/link.ll
M clang/test/OffloadTools/clang-sycl-linker/split-mode.ll
M clang/test/OffloadTools/clang-sycl-linker/triple.ll
A clang/test/OffloadTools/clang-sycl-linker/weak-symbols.ll
M clang/tools/clang-sycl-linker/CMakeLists.txt
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
M clang/tools/clang-sycl-linker/SYCLLinkOpts.td
Log Message:
-----------
[clang-sycl-linker] Add static archive (.a) support (#202829)
Add support for static archives of LLVM bitcode files to
clang-sycl-linker. The archive member-selection engine (a symbol-driven
fixed-point lazy extraction loop) is simplified to bitcode-only
handling.
clang-sycl-linker gains -l/--library,
--whole-archive/--no-whole-archive, and -u/--undefined options. The
previous --bc-library option is removed in favor of the standard -l
mechanism. Inputs (positional files and -l libraries) are now resolved
to in-memory buffers; archive members are pulled in lazily only when
they resolve undefined symbols, and bitcode is loaded with
parseBitcodeFile.
Co-Authored-By: Claude
---------
Co-authored-by: Yury Plyakhin <yury.plyakhin at intel.com>
Commit: 0d490215a541cf91b8e24e697570bb1cc938078d
https://github.com/llvm/llvm-project/commit/0d490215a541cf91b8e24e697570bb1cc938078d
Author: adams381 <adams at nvidia.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M clang/lib/CIR/Lowering/LoweringHelpers.cpp
A clang/test/CIR/CodeGen/string-literal-high-bytes.c
Log Message:
-----------
[CIR] Lower string literals with high-bit bytes (#203384)
A string literal containing a byte >= 0x80 crashes CIR-to-LLVM lowering.
`convertStringAttrToDenseElementsAttr` builds each element's `APInt`
from a signed `char`, so a high-bit byte sign-extends to a 64-bit value
that no longer fits the 8-bit element width and trips the `APInt`
constructor assertion (`isUIntN(BitWidth, val) && "Value is not an N-bit
unsigned value"`).
Interpreting each string byte as `unsigned char` fixes it, mirroring
what #197269 did for scalar character literals. The string-literal array
path was the remaining site with the same defect, and the lowered LLVM
is byte-identical to classic CodeGen.
Repro: `char s[] = "\x80";` compiled with `-fclangir -emit-llvm`. This
also clears a cluster of SingleSource gcc-torture globals that embed
high-byte string data.
These globals compiled until #198427 removed the trailing-zeros
fast-path in the same lowering. String literals always carry a null
terminator (trailing zeros), so they previously took the insertvalue
path and never reached `convertStringAttrToDenseElementsAttr`; #198427
routes them through it and exposed this latent sign-extension bug.
Commit: 240539f1c1ba5f72ce5879807ed1a6dd5b694ef5
https://github.com/llvm/llvm-project/commit/240539f1c1ba5f72ce5879807ed1a6dd5b694ef5
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
Log Message:
-----------
[VPlan] Account for canonical IV being simplified in verifier. (#203403)
In plain CFG plans, VPCurrentIterationPHIRecipe may be the first recipe,
if the canonical IV phi has been removed because it became unused (e.g.
the vector loop is known to only execute a single iteration).
Fixes https://lab.llvm.org/buildbot/#/builders/187/builds/20801.
Commit: 44c543639726d6c40017a20d73b572d26fceb698
https://github.com/llvm/llvm-project/commit/44c543639726d6c40017a20d73b572d26fceb698
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
M libc/include/llvm-libc-types/struct_tm.h
A libc/include/llvm-libc-types/tm_gmtoff_t.h
M libc/include/time.yaml
M libc/src/time/strftime_core/converter.h
M libc/src/time/time_utils.h
M libc/test/src/time/strftime_test.cpp
Log Message:
-----------
[libc] Add timezone extensions to struct tm and time.h (#203381)
Added timezone extensions to struct tm and time.h:
* struct tm: Added tm_gmtoff and tm_zone, with __tm_gmtoff and __tm_zone
aliases defined as macros.
* time.h: Added tm_gmtoff_t type.
Updated gmtime and localtime to initialize these fields, and enabled %z
and %Z support in strftime.
These changes are implemented unconditionally. While the timezone
database loading is not yet implemented (so local time offsets default
to UTC/0), the timezone formatting and struct field support is fully
complete. Implementing this conditionally would require complex
build-time configuration and conditional inclusion of code, which is
avoided as this implementation is already a complete improvement over
the previous state.
Assisted-by: Automated tooling, human reviewed.
Commit: 112fb2f79d7983be203957cad6b148865182ed47
https://github.com/llvm/llvm-project/commit/112fb2f79d7983be203957cad6b148865182ed47
Author: mleair <leairmark at gmail.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M flang/lib/Parser/Fortran-parsers.cpp
A flang/test/Parser/recovery09.f90
Log Message:
-----------
[flang] Improve error for data component definition after CONTAINS in derived type (#203379)
When a data component declaration appears after CONTAINS in a derived
type definition, flang previously emitted confusing "expected 'FINAL'",
"expected 'GENERIC'", and "expected 'PROCEDURE'" errors for each
misplaced component.
This patch adds a misplaced-component detector following the same
pattern as `misplacedSpecificationStmt` in program-parsers.cpp.
DataComponentDefStmt is tried as a last alternative in
TypeBoundProcBinding's first(). When it matches, fail<>() fires
with the message:
error: component definition must precede CONTAINS in a derived type
CombineFailedParses then replaces the three keyword-mismatch messages
with this single targeted one, since the component parse advances
further than the PROCEDURE/GENERIC/FINAL failures.
Assisted-By: AI
Commit: 421d296893ed173846c0aceaee67cdafa67da07b
https://github.com/llvm/llvm-project/commit/421d296893ed173846c0aceaee67cdafa67da07b
Author: adams381 <adams at nvidia.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.h
A clang/test/CIR/Transforms/abi-lowering/indirect-return-sret.cir
Log Message:
-----------
[CIR] Lower sret returns in CallConvLowering (#201716)
Functions that return an aggregate by value classify their return as
ArgKind::Indirect, but CallConvLowering reached an errorNYI for that
case, so the whole CallConv pass refused to lower any struct-returning
function.
rewriteFunctionDefinition now recognizes an Indirect return: the wire
return type becomes void, a hidden sret pointer is prepended as block
argument 0, and every cir.return is routed through that pointer. Rather
than storing the loaded return value through the sret pointer (a
byte-copy that breaks non-trivially-copyable types -- libstdc++'s SSO
std::string keeps a _M_p pointer into its own _M_local_buf, so a
byte-copy leaves the destination aliasing the source's dying stack
storage), insertSRetStores rewires the __retval alloca to the sret
pointer so construction flows directly into the caller's slot, matching
classic CodeGen's "construct into %agg.result" pattern. CIRGen emits one
cir.load __retval / cir.return pair per return statement, all reading
the
single __retval alloca, so the alloca is rewired once and every return
is
collapsed to a bare return. That cir.return (cir.load <alloca>) shape is
treated as an invariant and asserted with cast<> rather than guarded by
a
fallback. The sret parameter carries sret(T) align A writable
dead_on_unwind, plus noalias on definitions.
rewriteCallSite prepends the return slot, makes the call return void,
and reads the result back. When the result has a single store-into-dest
use whose destination dominates the call, it reuses that destination as
the sret slot and drops the redundant store, so the callee writes
straight into the local with no copy; otherwise it allocates a fresh
slot
and loads the value out. The slot's
per-argument attributes go through the same updateArgAttrs path as the
non-sret case, so sret composes with Extend (signext/zeroext) and Ignore
arguments.
byval indirect arguments and Expand are still errorNYI.
Co-authored-by: Cursor <cursoragent at cursor.com>
---------
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: 3397635cb50abdc9413246a3810f7d1701211f0b
https://github.com/llvm/llvm-project/commit/3397635cb50abdc9413246a3810f7d1701211f0b
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1251_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
Log Message:
-----------
[AMDGPU] Add gfx1251 V_PK_MUL_F64 (#203410)
Commit: 673ec226f6fae99ab58cb1cff90a795b03a17f80
https://github.com/llvm/llvm-project/commit/673ec226f6fae99ab58cb1cff90a795b03a17f80
Author: Jason Molenda <jmolenda at apple.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M lldb/test/API/macosx/simulator/TestSimulatorPlatform.py
Log Message:
-----------
[lldb][macosx] Pare down the SimulatPlatform tests, don't run on intel (#203417)
TestSimulatorPlatform.py is flakey on the Intel Mac CI, doing a
'platform process list' and not getting a reply back. The issue is only
happening on the old Intel mac CI and not the newer arm64 CI's; it is
not important. I am skipping this test on the Intel mac CI.
I'm also removing test runs that try to build 32-bit binaries (i386,
armv7k) and the tests that would explicitly test for a legacy build load
command (e.g. `LC_VERSION_MIN_IPHONEOS`); we don't support building back
to when OSes were using those, any more.
Commit: bd1de35f75bf1b08c02939fc9c4b67c45630d902
https://github.com/llvm/llvm-project/commit/bd1de35f75bf1b08c02939fc9c4b67c45630d902
Author: Xyloflake <xyloflake at gmail.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/TargetParser/Host.cpp
Log Message:
-----------
Add Apple M5 host detection (#200616)
The values have been taken from `mach/machine.h` in the Xcode 26.5 SDK.
Commit: bfca0db5bd17ab116cd70464d7e1099b07a5872b
https://github.com/llvm/llvm-project/commit/bfca0db5bd17ab116cd70464d7e1099b07a5872b
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/include/llvm/Frontend/HLSL/CBuffer.h
M llvm/lib/Frontend/HLSL/CBuffer.cpp
M llvm/lib/Target/DirectX/DXILCBufferAccess.cpp
M llvm/lib/Target/SPIRV/SPIRVCBufferAccess.cpp
Log Message:
-----------
[NFC][DirectX][SPIRV] Remove helper from HLSLFrontend (#203401)
Remove helper function `removeCBufferGlobalsFromUseList` which basically
implements existing `llvm::removeFromUsedLists`. Modify the passes that
use it to call `llvm::removeFromUsedLists`.
Follow-up on
https://github.com/llvm/llvm-project/pull/202745#discussion_r3398119720
Commit: 10836c2234c480ac943850fec9359c83dba2d45d
https://github.com/llvm/llvm-project/commit/10836c2234c480ac943850fec9359c83dba2d45d
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1251_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
Log Message:
-----------
[AMDGPU] Add gfx1251 V_PK_FMA_F64 (#203418)
Commit: 2e708e7c90e611a57f7e748347acc4dbd540e43a
https://github.com/llvm/llvm-project/commit/2e708e7c90e611a57f7e748347acc4dbd540e43a
Author: William Tran-Viet <wtranviet at proton.me>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M libcxx/include/optional
M libcxx/test/std/utilities/optional/optional.syn/optional_in_place_t.verify.cpp
M libcxx/test/std/utilities/optional/optional.syn/optional_nullopt_t.verify.cpp
Log Message:
-----------
[libc++] Reimplement `optional<T&>` as a partial specialization (#201983)
- Break out the `optional<T&>` implementation that was interwoven with
the regular interface
- This should simplify the implementation
- And fix a missed added constraint for the `std::swap` specialization.
Commit: 9f1e08fa8ed7bcf4b7cfaf9eaaa7c23a2d3ed347
https://github.com/llvm/llvm-project/commit/9f1e08fa8ed7bcf4b7cfaf9eaaa7c23a2d3ed347
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowExtractor.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.h
M clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
Log Message:
-----------
[SSAF][Extractor] Make hard errors in PointerFlow and UnsafeBufferUsage Extractors quiet (#201953)
Hard errors were used in extractors during development to quickly
identify unsupported language constructs. This commit converts them to
DEBUG_WITH_TYPE so that these errors are silenced in release builds.
In addition, translating unsupported language constructs now silently
results in an empty EntityPointerLevelSet. The PointerFlowExtractor will
skip empty sets for either the source or the destination when building
edges to avoid an ill-formed edge set data structure.
rdar://178747892
---------
Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
Commit: 48813264376be9868bec78fa1653bc9003db512f
https://github.com/llvm/llvm-project/commit/48813264376be9868bec78fa1653bc9003db512f
Author: SeongJaePark <111725324+SeongjaeP at users.noreply.github.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/LowerVectorContract.cpp
M mlir/test/Dialect/Vector/vector-contract-to-parallel-arith-transforms.mlir
Log Message:
-----------
[mlir][vector][NFC] Document and simplify vector contract reshape helpers (#200544)
Replace the bare `// TODO` placeholders above `reshapeLoad` and
`reshapeStore`
in `LowerVectorContract.cpp` with doc comments describing each helper's
semantics (the `index == -1` / `index == 0` / `index > 0` cases) and
short
before/after IR examples.
Also drop the redundant `VectorType` parameter from both helpers; the
type is
now inferred from the value operand (`val` for `reshapeLoad`, `result`
for
`reshapeStore`).
Add a LIT test that exercises the recursive `reshapeLoad` unroll path by
mapping a parallel iterator to a non-leading dimension, which falls
through
to the generic `lowerParallel` / `reshapeLoad` path.
No functional change.
---------
Co-authored-by: sjae.park <dev at opt-ai.kr>
Commit: 7597c0c938b364306cbee21dd03835ff5b699c74
https://github.com/llvm/llvm-project/commit/7597c0c938b364306cbee21dd03835ff5b699c74
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.fmt-error.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_wmma_w32.s
M llvm/test/MC/AMDGPU/gfx1250_asm_wmma_w32_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_wmma_w32.txt
Log Message:
-----------
[AMDGPU] Validate WMMA scale/format combination (#203074)
Only some combinations are listed as supported.
Fixes: https://github.com/ROCm/llvm-project/issues/2634
Commit: 3ef102be08a0b9c3bd948e651d70f36dc73cc5ae
https://github.com/llvm/llvm-project/commit/3ef102be08a0b9c3bd948e651d70f36dc73cc5ae
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowExtractor.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowTest.cpp
Log Message:
-----------
[SSAF][PointerFlowExtractor] Handle empty initializer lists for scalars and unions (#201968)
Empty initializer lists for scalars and unions are corner cases that
were previously missed by the PointerFlowExtractor. This commit adds
support for these cases. Because the initializing values are implicitly
constant 0 (or nullptr), they do not bridge entity pointer levels.
rdar://178856689
---------
Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
Commit: d583701b350c8b8767cc8e6c17f03aa6336cfc1d
https://github.com/llvm/llvm-project/commit/d583701b350c8b8767cc8e6c17f03aa6336cfc1d
Author: Prabhu Rajasekaran <prabhukr at google.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M libc/config/baremetal/config.json
Log Message:
-----------
[libc] Enable baremetal printf float320 (#203421)
For memory constrained baremetal devices using float320 seems a
reasonable option by default.
Commit: d543c49ad6bf02434abc5db85332d5ab45e6e3ca
https://github.com/llvm/llvm-project/commit/d543c49ad6bf02434abc5db85332d5ab45e6e3ca
Author: yueshe <yueshe1996 at gmail.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/test/Driver/darwin-objc-selector-stubs.m
Log Message:
-----------
[clang][Darwin] Disable ObjC class selector stubs when using LLD (#203388)
LLD does not support ObjC class selector stubs yet (which requires
synthesizing `objc_msgSendClass$...` stubs). This change disables
`-fobjc-msgsend-class-selector-stubs` by default when the linker is LLD.
Ref: https://github.com/llvm/llvm-project/issues/203385
Commit: 95746377678925adfe39c83081b4144d92c5d3b8
https://github.com/llvm/llvm-project/commit/95746377678925adfe39c83081b4144d92c5d3b8
Author: SiHuaN <liyongtai at iscas.ac.cn>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
Log Message:
-----------
[Clang][RISCV] packed comparison intrinsics (#203191)
Add header wrappers for pmseq/pmsne/pmslt[u]/pmsgt[u]/pmsge[u]/pmsle[u]
as element-wise vector comparisons cast to the unsigned result type.
Commit: 7dcd1d2ad104c3f9748370a42dc775cd6e7e34dc
https://github.com/llvm/llvm-project/commit/7dcd1d2ad104c3f9748370a42dc775cd6e7e34dc
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowExtractor.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.h
M clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
Log Message:
-----------
Revert "[SSAF][Extractor] Make hard errors in PointerFlow and UnsafeBufferUsage Extractors quiet (#201953)" (#203432)
This reverts commit 9f1e08fa8ed7bcf4b7cfaf9eaaa7c23a2d3ed347.
It causes build error:
https://lab.llvm.org/buildbot/#/builders/2/builds/53597.
The use of 'setCurrentDebugType' should be guarded by '#ifndef NDEBUG'
Commit: 8433cf6d6ccc49a0fd99ed86c7d94a1fbb2fd1be
https://github.com/llvm/llvm-project/commit/8433cf6d6ccc49a0fd99ed86c7d94a1fbb2fd1be
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
Log Message:
-----------
[AMDGPU] Make v2f64 fneg legal on gfx1251 (#203427)
Commit: b9704de13ca5ce3158c6681839162a791042c6f9
https://github.com/llvm/llvm-project/commit/b9704de13ca5ce3158c6681839162a791042c6f9
Author: David Zbarsky <dzbarsky at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Passes/PassBuilder.cpp
Log Message:
-----------
[PassBuilder] Table-drive pass name printing (#202656)
Replace the macro-expanded raw_ostream operations in
PassBuilder::printPassNames with static pass-name arrays and two shared
noinline printing loops. Preserve the generated category order and the
exact spelling of parameterized pass names.
The change only executes when a client requests the pass-name listing;
normal pipeline parsing and optimization do not access the new tables or
helpers.
A stripped opt binary shrinks from 115,493,720 to 115,394,640 bytes,
saving 99,080 bytes. The linked __TEXT section shrinks by 98,304 bytes.
Work towards #202616
AI tool disclosure: Co-authored with OpenAI Codex.
Commit: 15fdc79231b9d32a6bef89f5fc89105b8d3f9363
https://github.com/llvm/llvm-project/commit/15fdc79231b9d32a6bef89f5fc89105b8d3f9363
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel][DirectX] Fix 2bccbf23edddf216ef060d34443f60f644d0fb06 (#203442)
Add new dep on MC
Commit: 56f8fbb0149146f50aa8c905467b9384e8cb7bad
https://github.com/llvm/llvm-project/commit/56f8fbb0149146f50aa8c905467b9384e8cb7bad
Author: TelGome <93700071+TelGome at users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsRISCV.td
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Log Message:
-----------
[RISCV][P-ext] Support Packed Averaging Addition and Subtraction intrinsics(#203147)
Commit: 69371e6c313063fac7fb580c126cb17996d71a01
https://github.com/llvm/llvm-project/commit/69371e6c313063fac7fb580c126cb17996d71a01
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel][libc] Fix 8acfc364e9f788367ff0beab5c76a3527a689a0b (#203443)
Add extra htons yaml deps
Commit: 0591eef767078a0a079469656658c4a2fc017bbe
https://github.com/llvm/llvm-project/commit/0591eef767078a0a079469656658c4a2fc017bbe
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/assume.ll
Log Message:
-----------
[InstCombine] Move noundef assume bundles on loads into metadata (#203395)
Commit: beb2614e3ec915069380107409e88d002404aee9
https://github.com/llvm/llvm-project/commit/beb2614e3ec915069380107409e88d002404aee9
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel][libc] Fix 582643f1ec62d0c81d97afcf1b741babb3152728 (#203449)
Add dep for dyadic float -> attributes
Commit: 2a6cfc5643053117b3baa301b91afaf9fc5edede
https://github.com/llvm/llvm-project/commit/2a6cfc5643053117b3baa301b91afaf9fc5edede
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M compiler-rt/test/fuzzer/features_dir.test
M compiler-rt/test/fuzzer/merge-posix.test
Log Message:
-----------
[Fuzzer] Make two tests compatible with the internal shell. (#203448)
1. Remove redundant parntheses that broke the internal shell's parsing
logic.
2. Use env when specifying environment variables.
3. Rewrite a bash one-line loop in python.
Commit: 62847ab7593df144a5708406e6240ec5e8a3a101
https://github.com/llvm/llvm-project/commit/62847ab7593df144a5708406e6240ec5e8a3a101
Author: Jiahao Guo <eoonguo at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
Log Message:
-----------
[CIR] Support zero/one result trivial operation lower via tablegen (#203183)
### summary
Lower zero result operation have been supported in this PR:
https://github.com/llvm/llvm-project/pull/202273
In this PR, the lowering of operations with zero-result and one-result
is changed to be automatically lowered via TableGen. This helps reduce
the size of the file
`clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp`
#### test
I thought existing lower tests can cover this PR, so I didn't add more
tests.
Assisted-by: Claude Opus 4.8
Commit: c1991da69a5f6bd7117224c68f2f66546264a743
https://github.com/llvm/llvm-project/commit/c1991da69a5f6bd7117224c68f2f66546264a743
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
M mlir/test/Target/LLVMIR/nvvm/barrier.mlir
Log Message:
-----------
[MLIR][NVVM] Update nvvm.barrier.arrive Op (#202608)
This change updates the `nvvm.barrier.arrive` Op to lower using
intrinsics instead of inline PTX. It also adds a new `aligned` attribute
to the Op to lower to both aligned and unaligned forms.
PTX Spec Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar
Commit: f3f7317aaf39928329dd453a6a340e6ddd027b81
https://github.com/llvm/llvm-project/commit/f3f7317aaf39928329dd453a6a340e6ddd027b81
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_err.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
Log Message:
-----------
[AMDGPU] Add MC clamp support for bf16 trans instructions (#203433)
Based on recent gfx1250 sp3 update. Refer to DEGFXSP3-664
Commit: 8679ab6267aeae9971cae4ed7eff9966e813e28d
https://github.com/llvm/llvm-project/commit/8679ab6267aeae9971cae4ed7eff9966e813e28d
Author: Hoàng Minh Thiên <hoangminhthien05022009 at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M libc/test/src/math/RoundToIntegerTest.h
Log Message:
-----------
[libc] [math] Fix build bot failure introduced by unit test in PR #201154 (#203457)
The root cause is that the unit test
`libc/test/src/math/RoundToIntegerTest.h` `#include <cfenv>` which
requires the macro `__GLIBC_PREREQ` to be defined. But in that riscv32
runtime, seems like it's not defined.
Removing the include works fine, and at the same time, would resolve the
failure.
Commit: 89a5c690e51a0ea33c962842f90a8ec89965afa3
https://github.com/llvm/llvm-project/commit/89a5c690e51a0ea33c962842f90a8ec89965afa3
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M clang/lib/CodeGen/Targets/RISCV.cpp
Log Message:
-----------
[RISCV] Return the type from detectVLSCCEligibleStruct instead of using an output argument. NFC (#203423)
We can replace the previous bool return with the type and use nullptr for
false.
Commit: 452f59c8dc30a3bc16c691f5862bc5b39d97319a
https://github.com/llvm/llvm-project/commit/452f59c8dc30a3bc16c691f5862bc5b39d97319a
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
A llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions-min-max.ll
Log Message:
-----------
Reapply "[LoopUnroll] Support parallel reductions for minmax" (#201010)
Reapplies 1e79ea1f5b3e (#182473) reverted by 56ccbc253150 (#200892). The
revert was due to a profcheck failure: prof-verify reported "select
annotation missing" on the combine select createMinMaxOp emits for FP
fcmp+select min/max.
This patch fixes it by marking the branch weights of newly inserted
selects as explicitly unknown.
Commit: efb038f38f23ee201ac872ae98668c2ef922f0fa
https://github.com/llvm/llvm-project/commit/efb038f38f23ee201ac872ae98668c2ef922f0fa
Author: ShashwathiNavada <shashwathinavada at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/Todo/error.f90
A flang/test/Lower/OpenMP/nothing.f90
Log Message:
-----------
[Flang][Openmp]Prevent TODO abort on nothing directive (#202679)
Since nothing is a no-op directive (OpenMP 5.2, 8.4), handle it during
lowering instead of falling through to the generic unimplemented
utility-directive path and triggering a TODO abort.
Commit: 06c7de45221621a0773d125ff7d016df87eb3d62
https://github.com/llvm/llvm-project/commit/06c7de45221621a0773d125ff7d016df87eb3d62
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
Log Message:
-----------
[LoopFusion][NFC] Avoid copying fusion candidates per pair (#203461)
`fuseCandidates()` copied both candidates (each holding two
`SmallVector<Instruction *, 16>`) for every adjacent pair examined, even
pairs rejected by an early continue. Bind them by const reference; they
are only read before being erased from the list, and performFusion runs
before the erases.
Commit: 15e7f2e8f2a14e5d574eb8894a4cbba8546291ca
https://github.com/llvm/llvm-project/commit/15e7f2e8f2a14e5d574eb8894a4cbba8546291ca
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/X86/pre-aggregated-perf.test
Log Message:
-----------
[BOLT] Propagate DataAggregator parse errors
Propagate perf/preaggregated input parsing errors through DataAggregator
instead of terminating from per-input aggregation jobs.
This lets multi-input aggregation report failed inputs as warnings when
at least one input succeeds while returning errors when all inputs fail.
It also converts pre-aggregated parsing diagnostics to returned Error
values and removes worker-path exits from perf setup and parsing.
Test Plan: updated pre-aggregated-perf.test
Reviewers: maksfb, rafaelauler, ayermolo, yozhu, yavtuk
Reviewed By: rafaelauler
Pull Request: https://github.com/llvm/llvm-project/pull/200476
Commit: 2b04d746524f6970523ceda9a6a9489caa4f2337
https://github.com/llvm/llvm-project/commit/2b04d746524f6970523ceda9a6a9489caa4f2337
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/include/bolt/Profile/DataReader.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/X86/pre-aggregated-perf.test
Log Message:
-----------
[BOLT] Buffer DataAggregator diagnostics
To avoid mixed up error messages in multi-perf case, provide diagnostics
buffer and stream for each aggregator job.
Test Plan: updated pre-aggregated-perf.test
Reviewers: yavtuk, maksfb, rafaelauler, ayermolo, paschalis-mpeis, yozhu
Reviewed By: yavtuk
Pull Request: https://github.com/llvm/llvm-project/pull/203464
Commit: 62a2af17a33394ac6f286dc110633013cb01ed7d
https://github.com/llvm/llvm-project/commit/62a2af17a33394ac6f286dc110633013cb01ed7d
Author: Bastian Hagedorn <bhagedorn at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
Log Message:
-----------
[MLIR][NVVM] Preserve PTX special registers in inline_ptx lowering (#203251)
`PtxBuilder::build()` converted operand placeholders (written as %0, %1,
and the predicate as @%N, since TableGen string attributes cannot
contain '$') to the inline-asm operand form with a blanket `replace(ptx,
'%', '$')`. That also rewrote literal PTX special-register names such as
%tid.x, %laneid and %dynamic_smem_size into $tid.x etc., producing
invalid PTX for any `nvvm.inline_ptx` whose body reads a special
register.
Convert only a '%' that is immediately followed by a digit (operand
placeholders and the @%N predicate); leave %<name> special registers
intact. PTX special registers always begin with a letter after '%', so
the digit test unambiguously distinguishes them from operand
placeholders.
Add an NVVMToLLVM regression test that reads %laneid through
nvvm.inline_ptx.
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: 7adb63de37b95dfbbb67ff775ba5e2bc93f15458
https://github.com/llvm/llvm-project/commit/7adb63de37b95dfbbb67ff775ba5e2bc93f15458
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosa.h
M mlir/lib/Conversion/TosaToSPIRVTosa/CMakeLists.txt
A mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaCustom.cpp
M mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaPass.cpp
A mlir/test/Conversion/TosaToSPIRVTosa/custom-op-domain-to-opcode-invalid.mlir
A mlir/test/Conversion/TosaToSPIRVTosa/custom-op-domain-to-opcode.mlir
Log Message:
-----------
[mlir][spirv] Lower mapped TOSA custom ops to ExperimentalML.Call (#202581)
Extend the TOSA to SPIR-V Graph conversion with an optional
custom-op-domain-to-opcode mapping. TOSA custom ops whose domain appears
in this mapping are lowered to spirv.ExperimentalML.Call using the
mapped CALL opcode. Later mappings for the same domain override earlier
ones, matching command-line option precedence.
For this TOSA lowering, CALL operands start with a spirv.array<N x i8>
carrying the operator_name byte blob. This is followed by another i8
array for implementation_attrs, then the original tensor inputs. Empty
strings are encoded as a single NUL byte because SPIR-V array types
require at least one element.
Use existing SPIR-V array constants for the metadata operands so the
target test stays on the SPIR-V binary round-trip path.
Signed-off-by: Niklas Lithammer <niklas.lithammer at arm.com>
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Co-authored-by: Niklas Lithammer <niklas.lithammer at arm.com>
Commit: fc8d61811e16874575a73df5e919201c903513c9
https://github.com/llvm/llvm-project/commit/fc8d61811e16874575a73df5e919201c903513c9
Author: Sven van Haastregt <sven.vanhaastregt at arm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/IR/Value.cpp
Log Message:
-----------
[IR] Fix deprecated-enum-enum-conversion C++20 warnings; NFC (#203277)
This addition of enum values resulted in many warnings of the form
warning: arithmetic between different enumeration types
'llvm::Value::ValueTy' and 'llvm::Instruction::TermOps' is
deprecated
Commit: 5ea65dfac0023ca82b8961f188d574c228657d22
https://github.com/llvm/llvm-project/commit/5ea65dfac0023ca82b8961f188d574c228657d22
Author: yueshe <yueshe1996 at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/test/Driver/darwin-objc-selector-stubs.m
Log Message:
-----------
Revert "[clang][Darwin] Disable ObjC class selector stubs when using LLD" (#203456)
Reverts llvm/llvm-project#203388
Unfortunately this breaks a bunch of tests on CI bots because they seem
to have LLD configured as the default linker. The tests were originally
written to expect `-fobjc-msgsend-class-selector-stubs`. Will have to
modify the tests as well
Commit: b086e198e241fdcde57a3f9961e7d8d3c3ca4a99
https://github.com/llvm/llvm-project/commit/b086e198e241fdcde57a3f9961e7d8d3c3ca4a99
Author: Tim Corringham <timothy.corringham at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/Basic/Attr.td
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaType.cpp
A clang/test/ParserHLSL/hlsl_is_array_attr.hlsl
A clang/test/ParserHLSL/hlsl_is_array_attr_error.hlsl
Log Message:
-----------
[HLSL] Add IsArray resource attribute (#201163)
First part of changes to add support for the IsArray resource attribute,
which will be used by the resource array types (Texture2DArray etc.).
These types will be implemented in subsequent changes.
This implements the attribute parsing and associated tests, and
implements the first part of #194910.
The Sema builtin argument checking and CodeGen will be included in a
subsequent PR which will implement a resource array type which will
allow those changes to be tested.
---------
Co-authored-by: Tim Corringham <tcorring at amd.com>
Commit: 630f30ca579575632937ff226c0feebb15d03623
https://github.com/llvm/llvm-project/commit/630f30ca579575632937ff226c0feebb15d03623
Author: Endre Fülöp <endre.fulop at sigmatechnology.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/StaticAnalyzer/Checkers/PthreadLockChecker.cpp
A clang/test/Analysis/pthreadlock-notes.c
Log Message:
-----------
[analyzer] Add path notes to PthreadLockChecker (#202473)
Bug reports from this checker lack context about where mutexes were
locked or unlocked, making it hard to understand the diagnostic without
reading surrounding code.
Add NoteTag on lock, unlock, destroy, and init events. Notes name the
mutex when possible and are filtered to only appear when the mutex is
relevant to the reported bug.
Commit: dbaa5e601ca06a88e66b95b94dc9d2974b1abded
https://github.com/llvm/llvm-project/commit/dbaa5e601ca06a88e66b95b94dc9d2974b1abded
Author: Fan Mo <w007878 at hotmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl07.rst
M llvm/examples/Kaleidoscope/Chapter7/toy.cpp
Log Message:
-----------
[docs] Kaleidoscope Tutorial Chapter 7 - base class Value* used for AllocaInst for assignment expression (#202101)
Eariler in this chapther, the value type of `NamedValues` was changed to
`AllocaInst*`, and so did all other occurs for example in
`VariableExprAST` and `ForExprAST`.
https://github.com/llvm/llvm-project/blob/6f8a363a483489687597e29b8bda0975e821f188/llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl07.rst?plain=1#L321-L324
However, the newly added assignment expression is still using `Value*`
as the type for LHS. Although `Value` is the base class of `AllocaInst`
therefore the code compiles and works well, it's better to keep it
consistent
Commit: cb098aa073bbb6ce5d5854d402fbb3e9ecbaaca8
https://github.com/llvm/llvm-project/commit/cb098aa073bbb6ce5d5854d402fbb3e9ecbaaca8
Author: David Green <david.green at arm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-fadd.ll
Log Message:
-----------
[AArch64] Change f128 costs to 10 * legalization factor. (#202555)
Lowering fadd, fsub, fmul, fdiv and frem will produce a libcall,
something that is always difficult to costmodel. This changes the cost
model to 10 to line up with the value we use for other libcalls.
Non-rthru costs will start to be used when we start producing accurate
non-rthru costs in getArithmeticInstrCost.
Commit: ce7dae3727322304712f6a1bcdebb254cad9ee60
https://github.com/llvm/llvm-project/commit/ce7dae3727322304712f6a1bcdebb254cad9ee60
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
Log Message:
-----------
[LV][NFC] Regenerate some CHECK lines (#203343)
Commit: 6a8ad9d1b5c2efc07899796d41956761bd4247b8
https://github.com/llvm/llvm-project/commit/6a8ad9d1b5c2efc07899796d41956761bd4247b8
Author: Piotr Sobczak <piotr.sobczak at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
[AMDGPU][NFC] Simplify assertions (#203472)
Replace assertions that listed concrete types with generic ones that
check that the type is a vector with an even number of elements.
This keeps the spirit of the assertions and matches the code.
Commit: 15a37869a788864e6d12e805dd0de2dc07a0d764
https://github.com/llvm/llvm-project/commit/15a37869a788864e6d12e805dd0de2dc07a0d764
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
Log Message:
-----------
[SPIR-V] Merge duplicate case bodies in addInstrRequirements (NFC) (#203177)
Commit: 90ca88b509d5c70e98002bde45453877a404ffc8
https://github.com/llvm/llvm-project/commit/90ca88b509d5c70e98002bde45453877a404ffc8
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
Log Message:
-----------
[SPIR-V] Replace custom bitcast in FPMaxError decoration handling (NFC) (#203179)
Commit: 7acd9402f2dbf57e56703ccc2e2b97f51cc7e9dc
https://github.com/llvm/llvm-project/commit/7acd9402f2dbf57e56703ccc2e2b97f51cc7e9dc
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for init_whole_wave intrinsic (#203286)
Commit: 2e7e9c112d320d1ad032a14621c68b6b5c69a519
https://github.com/llvm/llvm-project/commit/2e7e9c112d320d1ad032a14621c68b6b5c69a519
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for load_to_lds intrinsic (#203282)
Commit: 81e9fa8d82fd2b6277362c9f27f25ffd24723cb0
https://github.com/llvm/llvm-project/commit/81e9fa8d82fd2b6277362c9f27f25ffd24723cb0
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/asyncmark-max-pregfx12.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for global_load_async_lds (#203280)
Commit: 03afb2a0d6becb394901328f051ee9452fb66057
https://github.com/llvm/llvm-project/commit/03afb2a0d6becb394901328f051ee9452fb66057
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for G_PREFETCH (#203265)
Commit: 1a4f405c318131c79df259008f76b0d0730d6130
https://github.com/llvm/llvm-project/commit/1a4f405c318131c79df259008f76b0d0730d6130
Author: Dan Bonachea <dobonachea at lbl.gov>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang-rt/lib/runtime/__fortran_builtins.f90
M flang/CMakeLists.txt
Log Message:
-----------
[flang] __fortran_builtins: Update __builtin_team_type to meet PRIF specification (#202450)
The representation of `TEAM_TYPE` in the `ISO_FORTRAN_ENV` module is
opaque to the compiler, but the size (and alignment) needs to match the
PRIF specification for `prif_team_type` to ensure ABI compatibility with
the multi-image runtime library.
Flang's old definition as a derived type containing only an
`integer(int64)` component was leading to an 8-byte `TEAM_TYPE`. However
PRIF specifies the `prif_team_type` component as a `pointer` to an
opaque scalar type, which flang compiles to a 40-byte representation.
This mismatch was leading to incorrect behavior at runtime for programs
compiled with `-fcoarray` and using `TEAM_TYPE`, where `TEAM_TYPE`
values returned by PRIF were being silently truncated by the compiler.
Change the declaration of `__builtin_team_type` to match the PRIF
specification, thus ensuring the representation of `TEAM_TYPE` has the
required size.
Commit: b9339f0c9416b327f5130a78f33d4cbca5962fec
https://github.com/llvm/llvm-project/commit/b9339f0c9416b327f5130a78f33d4cbca5962fec
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M orc-rt/include/orc-rt-c/ExternC.h
Log Message:
-----------
[orc-rt] Fix an incorrect comment. (#203482)
Commit: a80153ea4f7dfcd6e0dcf2b415f9ace3cd54015a
https://github.com/llvm/llvm-project/commit/a80153ea4f7dfcd6e0dcf2b415f9ace3cd54015a
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for gfx950 smfmac intrinsics (#203287)
Commit: 951c67d4dbed4f87f366f1f911bc061bc6da1912
https://github.com/llvm/llvm-project/commit/951c67d4dbed4f87f366f1f911bc061bc6da1912
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.h
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
A clang/test/Driver/offload-darwin-host.hip
A clang/test/Driver/openmp-Xopenmp-target-forward-args.c
Log Message:
-----------
clang/AMDGPU: Use TranslateArgs from the base toolchain instead of the host (#198627)
This fixes -Xopenmp-target / -Xarch for arbitrary arguments. HIP and
OpenMP had cargo-cult broken implementations of TranslateArgs, which called the
host toolchain's implementation, and then special case transferred either
-march or -mcpu to the device argument list. The respective device forwarding
flags should work for any argument, not just this one. The main feature that
needs to be preserved is the shared filtering of unsupported sanitizers to
degrade them into warnings.
Most of the changes here are dealing with fallout observed when
the host target is darwin. The darwin toolchain happens to have
some hacky statefulness tracking the compile target version, which
gets written and rewritten on argument parsing. To maintain this hack,
there are a few unused calls to getArgsForToolChain; start passing
OFK_Host to these so the offload toolchains don't get confused and think
they're in a non-offload context.
Commit: ec60d62118bf17328b4d63c67eb981f9c8347d56
https://github.com/llvm/llvm-project/commit/ec60d62118bf17328b4d63c67eb981f9c8347d56
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
M llvm/test/Transforms/LoopVectorize/RISCV/gather-scatter-cost.ll
A llvm/test/Transforms/LoopVectorize/RISCV/stepvector-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-gather-scatter.ll
M llvm/test/Transforms/LoopVectorize/cast-costs.ll
M llvm/test/Transforms/LoopVectorize/vscale-cost.ll
Log Message:
-----------
[LV] Reland "Add costs for VPInstructionWithType::computeCost" (#202952)
The original change PR #198291 caused a crash due to an unreachable
opcode. I've added support for the missing opcode.
Commit: a0bad855ccb86c0ace7be1eb05e51895d61afecc
https://github.com/llvm/llvm-project/commit/a0bad855ccb86c0ace7be1eb05e51895d61afecc
Author: Abhinav Garg <abhinav.garg at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.subdword.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
Log Message:
-----------
[AMDGPU][GlobalIsel] Add RegBankLegalize rules and lowering for G_AMDGPU_S_BUFFER_LOAD (#192480)
Add RegBankLegalize rules and lowering for G_AMDGPU_S_BUFFER_LOAD and
sub-dword variants (UBYTE, SBYTE, USHORT, SSHORT). The lowering covers
all four rsrc/offset divergence combinations:
- Uniform rsrc + uniform offset → scalar SMEM (stays as-is)
- Uniform rsrc + divergent offset → MUBUF (S_BUF_to_BUF, no waterfall)
- Divergent rsrc + uniform offset → SMEM in waterfall loop over rsrc
- Divergent rsrc + divergent offset → MUBUF + waterfall over rsrc
TODO:
1. Fix legalize rule for intrinsic amdgcn_cvt_pkrtz to emit scalar cvt
operation in _/AMDGPU/scalar-float-sop2.ll_
2. Fix offset for GFX1250 in
_/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll_ as done by
PR#178389
Commit: 3922f3c505a4a9dffca840508d2ea3e5f0549412
https://github.com/llvm/llvm-project/commit/3922f3c505a4a9dffca840508d2ea3e5f0549412
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/ExceptionRecord.cpp
M lldb/source/Plugins/Process/Windows/Common/ExceptionRecord.h
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
Log Message:
-----------
[lldb][Windows] Use uint64 for GetExceptionArguments (#203485)
Intended to fix the build failure mentioned in
https://github.com/llvm/llvm-project/pull/203301#issuecomment-4688315446.
Makes sure we always use a 64 bit int, as the minidump exception record
specifies the arguments to be 64 bit. `unsigned long long` is also 64
bit on Windows, but I think `uint64_t` conveys that we actually want a
64bit int.
Then updates uses of the return value to use `uint64_t` over
`ULONG_PTR`.
Commit: 1727b22f5ab476db6b67ff93d5eaf1187e0ecc29
https://github.com/llvm/llvm-project/commit/1727b22f5ab476db6b67ff93d5eaf1187e0ecc29
Author: Konstantin Belochapka <konstantin.belochapka at sony.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/DTLTO/DTLTO.cpp
M llvm/test/ThinLTO/X86/dtlto/timetrace.ll
Log Message:
-----------
[DTLTO] Added missing timetrace "Check cache for DTLTO" message. (#203215)
After the DTLTO refactor commit, the time trace "Chack cache for DTLTO"
message was unintentionally omitted. This patch corrects this omission.
Commit: 29e27fd572050cc0dca003704309c1bf0eded89a
https://github.com/llvm/llvm-project/commit/29e27fd572050cc0dca003704309c1bf0eded89a
Author: Utkarsh Saxena <usx at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M .github/new-prs-labeler.yml
R clang/test/Sema/Inputs/lifetime-analysis.h
A clang/test/Sema/LifetimeSafety/Inputs/lifetime-analysis.h
A clang/test/Sema/LifetimeSafety/annotation-suggestions-fixits.cpp
A clang/test/Sema/LifetimeSafety/annotation-suggestions.cpp
A clang/test/Sema/LifetimeSafety/attr-lifetimebound-no-crash.cpp
A clang/test/Sema/LifetimeSafety/attr-lifetimebound.c
A clang/test/Sema/LifetimeSafety/capture-by.cpp
A clang/test/Sema/LifetimeSafety/cfg-bailout.cpp
A clang/test/Sema/LifetimeSafety/dangling-field.cpp
A clang/test/Sema/LifetimeSafety/dangling-global.cpp
A clang/test/Sema/LifetimeSafety/invalidations.cpp
A clang/test/Sema/LifetimeSafety/lifetime-facts.cpp
A clang/test/Sema/LifetimeSafety/lifetimebound-violation.cpp
A clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-cross-tu.cpp
A clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-intra-tu.cpp
A clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-macro.cpp
A clang/test/Sema/LifetimeSafety/missing-origin-stats.cpp
A clang/test/Sema/LifetimeSafety/nocfg-disabled.cpp
A clang/test/Sema/LifetimeSafety/nocfg.cpp
A clang/test/Sema/LifetimeSafety/noescape-violation.cpp
A clang/test/Sema/LifetimeSafety/safety.cpp
R clang/test/Sema/attr-lifetimebound-no-crash.cpp
R clang/test/Sema/attr-lifetimebound.c
R clang/test/Sema/warn-lifetime-analysis-capture-by.cpp
R clang/test/Sema/warn-lifetime-analysis-nocfg-disabled.cpp
R clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
R clang/test/Sema/warn-lifetime-safety-cfg-bailout.cpp
R clang/test/Sema/warn-lifetime-safety-dangling-field.cpp
R clang/test/Sema/warn-lifetime-safety-dangling-global.cpp
R clang/test/Sema/warn-lifetime-safety-dataflow.cpp
R clang/test/Sema/warn-lifetime-safety-fixits.cpp
R clang/test/Sema/warn-lifetime-safety-invalidations.cpp
R clang/test/Sema/warn-lifetime-safety-lifetimebound.cpp
R clang/test/Sema/warn-lifetime-safety-misplaced-lifetimebound-cross-tu.cpp
R clang/test/Sema/warn-lifetime-safety-misplaced-lifetimebound-intra-tu.cpp
R clang/test/Sema/warn-lifetime-safety-misplaced-lifetimebound-macro.cpp
R clang/test/Sema/warn-lifetime-safety-missing-origin-stats.cpp
R clang/test/Sema/warn-lifetime-safety-noescape.cpp
R clang/test/Sema/warn-lifetime-safety-suggestions.cpp
R clang/test/Sema/warn-lifetime-safety.cpp
Log Message:
-----------
[LifetimeSafety] Reorganize tests into `LifetimeSafety/` subdirectory (#203363)
Commit: 125242eb15b6b74e8ad6ab81a760ef4c1b2deea7
https://github.com/llvm/llvm-project/commit/125242eb15b6b74e8ad6ab81a760ef4c1b2deea7
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/test/CodeGen/SPIRV/FCmpFalse_Vec.ll
A llvm/test/CodeGen/SPIRV/constant/local-zero-constants.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/is_fpclass.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/signed_arithmetic_overflow.ll
Log Message:
-----------
[LLVM][CodeGen][SPIRV] Match NULL splat to OpConstantNull. (#201313)
Commit: ab5da4b999f862e5b165ac87dd9b90ff162e048b
https://github.com/llvm/llvm-project/commit/ab5da4b999f862e5b165ac87dd9b90ff162e048b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
Log Message:
-----------
[X86] Add test showing failure to concat X86ISD::PERMI nodes with different immediates (#203487)
Commit: 4a3946fc690c461417d38b6264a1f7a70f5dd364
https://github.com/llvm/llvm-project/commit/4a3946fc690c461417d38b6264a1f7a70f5dd364
Author: ambergorzynski <120007557+ambergorzynski at users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
A llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
R llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll
Log Message:
-----------
[AMDGPU][NFC] New tests for uncovered cases in SIInstrInfo.cpp (#200414)
Several cases in [the AMDGPU
backend](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp)
are not covered by the existing tests. We are proposing a new set of
tests to cover these lines.
We demonstrate that these cases are not covered by showing that no test
fails when `abort` statements are included. These are removed for the
final PR. You can check the lines of interest in [this
commit](https://github.com/llvm/llvm-project/pull/200414/commits/84d4587b784014ace546d23beaf6ed8d703452d3).
Commit: da65d6afe74463745dae9af0ce47f31e4186778e
https://github.com/llvm/llvm-project/commit/da65d6afe74463745dae9af0ce47f31e4186778e
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Support/KnownFPClass.cpp
M llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-canonicalize.ll
Log Message:
-----------
[KnownFPClass] Fix canonicalize incorrectly dropping fcNegZero under positive-zero denormal mode (#202268)
The denormal mode only flushes *denormal* (subnormal) values; -0.0 is
not a denormal, and per LangRef canonicalize must conserve the sign of
zero (canonicalize(-0.0) == -0.0).
Alive2 (InstCombine fold of canonicalize on a {+/-0, nan} value):
before (miscompiles -0.0 -> +0.0): https://alive2.llvm.org/ce/z/ZRK-sr
after (verifies): https://alive2.llvm.org/ce/z/L3tPu3
Commit: dbc255bedbf5099f32409d41a77bdf0730f4963a
https://github.com/llvm/llvm-project/commit/dbc255bedbf5099f32409d41a77bdf0730f4963a
Author: Nathan Corbyn <n_corbyn at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.h
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
Log Message:
-----------
[AArch64](NFC) Introduce unified `isLegalArithImmed()` and `isLegalCmpImmed()` (#203020)
Quick tidy up to factor out some common helpers into
`AArch64AddressingModes.h`.
Commit: 274331053cd6b567a02d7ef8a85adcb403dffcb0
https://github.com/llvm/llvm-project/commit/274331053cd6b567a02d7ef8a85adcb403dffcb0
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
Log Message:
-----------
[AMDGPU] Regenerate cluster ID checks (#203494)
Commit: 056b4a71c07ff19e38c5cf475fa31fd1271b460d
https://github.com/llvm/llvm-project/commit/056b4a71c07ff19e38c5cf475fa31fd1271b460d
Author: Diego Novillo <dnovillo at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-vector-skipped.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-vector.ll
Log Message:
-----------
Emit debug type vector (#200056)
This emits `DebugTypeVector` for HLSL `float4`-style vectors.
`partitionTypes()` separates vector `DICompositeType` nodes from basic
types so both can be visited in a single pass over the debug metadata. A
new `emitDebugTypeVector()` helper builds the `DebugTypeVector`
instruction and looks up the base-type register in `DebugTypeRegs`.
The helper skips four cases silently:
1. Absent or non-`DIBasicType` base type: only scalar element types are
supported for now.
2. Base type not yet emitted: the type was not reached during the
`DebugTypeBasic` pass.
3. Multiple subranges: `DebugTypeVector` models one-dimensional vectors
only (NSDI cannot encode multi-subrange types).
4. Non-constant subrange count: NSDI cannot represent variable-length
counts.
Added a new test in
`test/CodeGen/SPIRV/debug-info/debug-type-vector.ll`.
Commit: 663bcb3574d72552b41de6a740e454f2f53e2f4a
https://github.com/llvm/llvm-project/commit/663bcb3574d72552b41de6a740e454f2f53e2f4a
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll
Log Message:
-----------
[SVE] Replace unnecessary Intrinsic::aarch64_sve_ptrue construction. (#203349)
Prefer ConstantInt::getTrue() over sve.ptrue(31) when creating
all-active boolean vectors.
Commit: 66842786198f6fe58dc20813e45d216f838db2f4
https://github.com/llvm/llvm-project/commit/66842786198f6fe58dc20813e45d216f838db2f4
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M .git-blame-ignore-revs
Log Message:
-----------
Add "Split clang/lib/CodeGen/CGBuiltin.cpp" to .git-blame-ignore-revs (#203419)
Commit: 23d906e24b06f27749c84229e4a3043b7e63a2d5
https://github.com/llvm/llvm-project/commit/23d906e24b06f27749c84229e4a3043b7e63a2d5
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M openmp/runtime/cmake/LibompExports.cmake
Log Message:
-----------
[openmp] Fix export file paths (#202692)
The files omp_lib.h and omp-tools.h are the outputs of two
configure_file invocations which specify the full path of the outputs.
Use these full paths in LibompExports.cmake so they can actually be
found.
Commit: 9623ae8878b1d2d7ff39f9ce5c30e8bf82dd1896
https://github.com/llvm/llvm-project/commit/9623ae8878b1d2d7ff39f9ce5c30e8bf82dd1896
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpHelpers.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx20.cpp
Log Message:
-----------
[clang][bytecode] Add `PtrView` for non-tracking pointers (#184129)
Currently, when creating a `Pointer` (of block type, which I will assume
here), the pointer will add itself (via its address) to its block's
pointer list. This way, a block always knows what pointers point to it.
That's important so we can handle the case when a block (which was e.g.
created for a local variable) is destroyed and we now need to update its
pointers.
However, since always do this for all `Pointer` instances, it creates a
weird performance problem where we do this dance all the time for no
reason, e.g. consider `Pointer::stripBaseCasts()`:
https://github.com/llvm/llvm-project/blob/88693c49d9ac58a33af5978d31f6c70fe1d5b45b/clang/lib/AST/ByteCode/Pointer.h#L778-L783
This will add and remove the newly created pointer from the block's
pointer list every iteration. Other offenders are `Pointer::toRValue()`,
`EvaluationResult::checkFullyInitialized()` or
`Pointer::computeOffsetForComparison()`.
This commit introduces a `PtrView` struct, which is like a
`BlockPointer`, but without the prev/next next links to other `Pointer`s
in the block's pointer list. It also moves a lot of the accessors from
`Pointer` to `PtrView` (e.g. `isRoot()` or `getFieldDesc()`, etc.).
compile-time-tracker:
https://llvm-compile-time-tracker.com/compare.php?from=4716dc8c51719cbcc82928cd00e41a29e5b9adff&to=28d69d4ec16e77370938675826b07752e108eede&stat=instructions:u
Commit: 2b4e89bc254dab3f18b59cd275519d256267b88e
https://github.com/llvm/llvm-project/commit/2b4e89bc254dab3f18b59cd275519d256267b88e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
Log Message:
-----------
[X86] combineConcatVectorOps - concat(permi(x,imm0),permi(y,imm1)) -> vpermv3(widen(x),m,widen(y)) (#203508)
Add handling for X86ISD::VPERMI nodes with different immediates -
folding to a X86ISD::VPERMV3 instead, replacing a
INSERT_SUBVECTOR+2xPERMI nodes with a mask load
We don't need to concat the source operands - we have other folds that
will do this if beneficial - we just rely on (free) implicit widening.
Commit: 8f069e7aea7dbf35d87c8a7a700ae6871b831298
https://github.com/llvm/llvm-project/commit/8f069e7aea7dbf35d87c8a7a700ae6871b831298
Author: Joachim Meyer <5982050+fodinabor at users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/docs/CommandGuide/lit.rst
M llvm/utils/lit/lit/TestRunner.py
M llvm/utils/lit/tests/substitutions.py
Log Message:
-----------
[lit] Add support for %{s:stem} substitution. (#202885)
It provides the source file name with the (last) extension removed.
This is to align with what is available for %t and actually needed
downstream.
Commit: 1f21f15e6503053b3f5cfed3689829ba16a60ce0
https://github.com/llvm/llvm-project/commit/1f21f15e6503053b3f5cfed3689829ba16a60ce0
Author: Rohit Aggarwal <Rohit.Aggarwal at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/test/CodeGen/X86/avx512f-builtins-constrained-cmp.c
Log Message:
-----------
[X86] - Prevent the wrong fold of x86_avx512_mask_cmp_ss/sd to fcmp (#202321)
The issue is based upon the SemiAnalysisAI by @jlebar.
[058-mask-cmp-ss-imm-immediate-not-validated](https://github.com/SemiAnalysisAI/FuzzX/blob/master/x86/bugs/058-mask-cmp-ss-imm-immediate-not-validated/NOTES.md)
It is not a real bug, just a warning for the future fold implementation
of mask_cmp → fcmp.
There is non to fix as of now in the source code. Added a few comments
and test cases for the future implementation of the folds.
@topperc @phoebewang
Commit: fb009c38d86c4a3c5b13b0ea90bbdb7665670096
https://github.com/llvm/llvm-project/commit/fb009c38d86c4a3c5b13b0ea90bbdb7665670096
Author: Harald van Dijk <hdijk at accesssoftek.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/DirectX/DirectXIRPasses/DXILDebugInfo.cpp
A llvm/test/CodeGen/DirectX/DebugInfo/di-commonblock.ll
A llvm/test/tools/dxil-dis/di-commonblock.ll
Log Message:
-----------
[DirectX] Drop DICommonBlock metadata (#201948)
DICommonBlock cannot be represented in LLVM 3.7, but it is a scope
within a parent scope, so we can refer to the parent scope instead.
Commit: a4bdf9d6ccdfcd9300164d9d043d74c78b2624cc
https://github.com/llvm/llvm-project/commit/a4bdf9d6ccdfcd9300164d9d043d74c78b2624cc
Author: Harald van Dijk <hdijk at accesssoftek.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/DirectX/DirectXIRPasses/DXILDebugInfo.cpp
A llvm/test/CodeGen/DirectX/DebugInfo/dbg-assign.ll
A llvm/test/CodeGen/DirectX/DebugInfo/dbg-value-arglist.ll
A llvm/test/tools/dxil-dis/dbg-assign.ll
A llvm/test/tools/dxil-dis/dbg-value-arglist.ll
Log Message:
-----------
[DirectX] Lower DbgAssign to DbgValue (#200267)
DbgAssign is not representable in LLVM 3.7.
Commit: f77a290a2ffeda2a9974e87fa9120044de0ed93f
https://github.com/llvm/llvm-project/commit/f77a290a2ffeda2a9974e87fa9120044de0ed93f
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/MergeICmps.cpp
M llvm/test/Transforms/MergeICmps/X86/no-gep-other-work.ll
M llvm/test/Transforms/MergeICmps/X86/opaque-ptr.ll
Log Message:
-----------
[MergeICmps] Perform dereferenceability check with context (#202884)
To support deref-at-point semantics, we need to check dereferenceability
with a context instruction. Currently, MergeICmps does the check for
each individual load instruction. In this PR, I'm replacing this with a
check for all the loads that are part of a chain after they have been
collected, so we do the context-sensitive check only once.
The choice of context instruction is a bit tricky: Normally, this would
just be the first block in the chain (the "entry block"), but it's also
possible for the block to "do extra work", in which case it will get
split. If this happens, we should be checking at the splitting point, as
the extra work might be freeing the pointer.
Another question to consider here is whether we need to be concerned
about frees at all: After all, the original code will be accessing at
least one byte of the two objects, so doesn't that imply that it wasn't
freed already? This is indeed the case, as long as allocations cannot
shrink. This is something we currently don't allow, but I think it's
something we want to allow, so I'm going with the conservative treatment
here.
Commit: 3b63f045b9a994e275d8fd186f2de96939c38378
https://github.com/llvm/llvm-project/commit/3b63f045b9a994e275d8fd186f2de96939c38378
Author: Federico Bruzzone <federico.bruzzone.i at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/Vector/Utils/VectorUtils.h
M mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp
Log Message:
-----------
[mlir][vector] extend `createReadOrMaskedRead`/`createWriteOrMaskedWrite` with permutation map support (#202766)
Follow-up to #201180.
Extends the existing `createReadOrMaskedRead` and
`createWriteOrMaskedWrite` utilities in `VectorUtils` with two optional
trailing parameters:
- `ArrayRef<Value> indices`
- `AffineMap permutationMap`
The affine super-vectorizer is updated to call these functions instead
of constructing `TransferReadOp`/`TransferWriteOp` directly.
@banach-space, please correct me if this wasn't what you meant in the
previous PR.
---------
Signed-off-by: Federico Bruzzone <federico.bruzzone.i at gmail.com>
Co-authored-by: Andrzej Warzyński <andrzej.warzynski at gmail.com>
Commit: 055ef48e1a98545c7ebb9246bb134fecfcc23cae
https://github.com/llvm/llvm-project/commit/055ef48e1a98545c7ebb9246bb134fecfcc23cae
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
Log Message:
-----------
[X86] Add tests showing failure to concat 256-bit rotate nodes on non-vlx targets (#203517)
These are widened in tablegen, we don't need to limit these to VLX targets
Commit: fc15b715917aea09851c41a0c5406d820709d35b
https://github.com/llvm/llvm-project/commit/fc15b715917aea09851c41a0c5406d820709d35b
Author: Zibi Sarbinowski <zibi at ca.ibm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CodeGen/Targets/SystemZ.cpp
Log Message:
-----------
[SystemZ] Rename GetSingleElementType to getSingleElementType (#203078)
# Refactor: Rename GetSingleElementType to getSingleElementType in
SystemZ ABI
## Summary
This PR refactors the SystemZ ABI code to follow LLVM coding standards
by renaming `GetSingleElementType` to `getSingleElementType` (camelCase
convention).
## Motivation
Rename to avoid having 'GetSingleElementType` in one class and
`getSingleElementType` in another one.
Commit: 7c0a3a52cf967da9c41d009fb92453b272d0d04a
https://github.com/llvm/llvm-project/commit/7c0a3a52cf967da9c41d009fb92453b272d0d04a
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/test/CodeGenHIP/offload-pgo-sections.hip
M clang/test/Driver/hip-profile-rocm-runtime.hip
M compiler-rt/lib/profile/InstrProfilingFile.c
M compiler-rt/lib/profile/InstrProfilingPlatformROCm.cpp
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
Log Message:
-----------
[PGO][HIP] Fix HIP device profile collection and sections emission (#202095)
Several related HIP device-PGO fixes:
Windows device collection. HIP rejects a hipMemcpy that reads past the
bounds
of a symbol registered with __hipRegisterVar, but device
data/counters/names
live in merged linker sections. Register a separate shadow for each
device
data, counters, and names symbol and copy each one by its exact
hipGetSymbolSize
size; this also lets static TUs with several kernels keep all their
profile
data. Open the device profile file in binary mode and pass the device
names to
the correct lprofWriteDataImpl arguments so llvm-profdata can read the
raw
profile. Open the versioned amdhip64_7.dll first, falling back to
amdhip64.dll.
Per-TU sections struct. Clang CodeGen emitted the
__llvm_profile_sections_<CUID>
struct (and its section start/stop references) for any profiling-enabled
device
TU. A TU with no instrumented device functions then referenced sections
nothing
populates, so the RDC device link failed under --no-undefined (and
duplicated
__llvm_prf_nm before per-CUID naming). Move the struct emission from
CGCUDANV
into the InstrProfiling pass, which emits it only when the TU has
profile data;
clang emits only the per-TU names-postfix marker, also making names
unique per
TU so RDC builds do not clash.
Dynamic-module interceptors. The hipModuleLoad* interceptors live in a
constructor-only object in clang_rt.profile_rocm that nothing
references, so the
linker drops it and dynamic-module programs collect no device profile.
When
linking clang_rt.profile_rocm, emit a force-link reference (-u on ELF,
-include: on COFF); the constructor self-skips when the program does not
use
hipModuleLoad.
Multi-device profile collection. On Linux, static profile collection
used to
try reading profile data from every visible HIP device. This could fault
when a
device was visible but had not launched the instrumented kernel. Track
HIP
devices that successfully launch kernels, and skip unused devices during
static
profile collection. If tracking is not available, keep the old
collect-all
behavior.
Depends on #201607 (reland HIP offload PGO compiler support and link the
device-profile runtime); that PR must land first.
Commit: 7d42028e806ab2b17af22ddb8417432e4781d4aa
https://github.com/llvm/llvm-project/commit/7d42028e806ab2b17af22ddb8417432e4781d4aa
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
Log Message:
-----------
[lldb][Windows] Make RM_RF a no-op on an empty argument and swallow errors (#203040)
This patch makes the Windows `RM_RF` a no-op on an empty argument and
swallow errors, matching Unix `rm -rf`. This fixes issues in swiftlang
on fresh builds.
This is needed for https://github.com/swiftlang/llvm-project/pull/13180
Commit: 1badbb2a77f6937c9af84a694e1d949c7952b744
https://github.com/llvm/llvm-project/commit/1badbb2a77f6937c9af84a694e1d949c7952b744
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
[AMDGPU] Fix copy-paste in hasNon16BitAccesses OpIs16Bit check (#203499)
OpIs16Bit tested TempOtherOp width instead of TempOp, mismatching
symmetric OtherOpIs16Bit clause
No observed miscompiles or direct issues to due to that so far
Commit: 5096057eb8254c7d56e1b70c4ba2fbf3ac215b73
https://github.com/llvm/llvm-project/commit/5096057eb8254c7d56e1b70c4ba2fbf3ac215b73
Author: Aditya Trivedi <120598696+adit4443ya at users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/linear-clause01.f90
Log Message:
-----------
[Flang][OpenMP] Fix crash when common block name is used in LINEAR clause (#203250)
[Flang][OpenMP] Fix crash when common block name is used in LINEAR
clause
Using a common block name in a LINEAR clause (e.g. linear(/c/))
caused
a symbol-must-have-a-type crash during lowering. The semantic checker
was not emitting an error because GetSymbolsInObjectList expands /c/
to its member variables before the check runs, so the
symbol->has<CommonBlockDetails>() guard was never reached.
Fix by checking for common block names directly on the OmpObjectList
before the expansion, where the Name variant of OmpObject still holds
the common block symbol.
Fixes #202329
Commit: b0cc3225b2f618b5760552b1dc7ce0ea26225c8f
https://github.com/llvm/llvm-project/commit/b0cc3225b2f618b5760552b1dc7ce0ea26225c8f
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
A mlir/test/IR/test-func-erase-arg-error.mlir
M mlir/test/lib/IR/TestFunc.cpp
Log Message:
-----------
[mlir] Check for argument uses in test-func-erase-arg pass (#203367)
The -test-func-erase-arg pass crashed when erasing arguments that still
had uses. Diagnose every such argument and fail the pass without
erasing.
Fixes https://github.com/llvm/llvm-project/issues/203218
Assisted-by: Claude (Claude Code)
Commit: daa9ecff7ea3ed9a99fd5b486516495655259971
https://github.com/llvm/llvm-project/commit/daa9ecff7ea3ed9a99fd5b486516495655259971
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
Log Message:
-----------
[X86] combineConcatVectorOps - concat(roti(x,i),roti(y,i)) -> roti(concat(x,y),i) on non-vlx targets (#203528)
128/256-bit rotates are widened in tablegen, we don't need to limit
these to VLX targets - any AVX512 target can perform these
We already have test coverage to ensure 128-bit XOP rotates don't get
concatenated to 256-bit
Commit: 75383d62ecde9e4948c6146662707d53cb496e08
https://github.com/llvm/llvm-project/commit/75383d62ecde9e4948c6146662707d53cb496e08
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/test/Format/lit.local.cfg
Log Message:
-----------
clang-format/test: Anchor the empty .clang-format-ignore to test_exec_root (#203444)
The test suite's lit.local.cfg creates an empty .clang-format-ignore at
config discovery time to protect the multiple-inputs[-inplace].cpp tests
that work on files in temporary locations.
This file should be written to where the tests execute instead of the
CWD during config discovery. The CWD might not even be an ancestor of
where the tests execute, and it might be the repository root which does
have a .clang-format-ignore that is incorrectly clobbered without this
change.
An alternative would be to just fix the tests that need to be protected,
but having a blanket guard like this does seem like a reasonable thing
to do.
Fixes: 915de1a5889c ("Generate empty .clang-format-ignore before running
tests (#136154)")
Commit: 95ca0744abc76f10da86bdd6e74f674a10a869f2
https://github.com/llvm/llvm-project/commit/95ca0744abc76f10da86bdd6e74f674a10a869f2
Author: NeKon69 <nobodqwe at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Origins.h
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Analysis/LifetimeSafety/Origins.cpp
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/test/Sema/LifetimeSafety/annotation-suggestions-fixits.cpp
M clang/test/Sema/LifetimeSafety/annotation-suggestions.cpp
M clang/test/Sema/LifetimeSafety/dangling-field.cpp
A clang/test/Sema/LifetimeSafety/inapplicable-lifetimebound.cpp
M clang/test/Sema/LifetimeSafety/lifetime-facts.cpp
M clang/test/Sema/LifetimeSafety/lifetimebound-violation.cpp
M clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-cross-tu.cpp
M clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-intra-tu.cpp
M clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-macro.cpp
M clang/test/Sema/LifetimeSafety/nocfg.cpp
M clang/test/Sema/LifetimeSafety/noescape-violation.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
Log Message:
-----------
[LifetimeSafety] Warn on inapplicable [[clang::lifetimebound]] parameters (#201101)
Adds `-Wlifetime-safety-inapplicable-lifetimebound` to diagnose
`[[clang::lifetimebound]]` annotations that have no effect because the
parameter type cannot carry a lifetime.
This currently diagnoses scalar parameters and `gsl::Owner` parameters
and unannotated record values (because they currently do not have
origins), while still allowing references, pointers and `gsl::Pointer`
values.
Closes #177184
Commit: 0246e4c1322e833ab6eb92b73cb618a66e693282
https://github.com/llvm/llvm-project/commit/0246e4c1322e833ab6eb92b73cb618a66e693282
Author: Vicky Nguyen <vicky.trucviennguyen at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
A clang/test/CodeGen/AArch64/neon/add.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
R clang/test/CodeGen/AArch64/poly-add.c
Log Message:
-----------
[CIR][AArch64] Upstream addition and polynomial-addition NEON builtins (#202005)
Related to https://github.com/llvm/llvm-project/issues/185382
CIR lowering for
- addition intrinsics
(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#addition)
- polynomial-addition intrinsics
(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#polynomial-addition)
Port tests:
- `clang/test/CodeGen/AArch64/neon_intrinsics.c` to
`clang/test/CodeGen/AArch64/neon/intrinsics.c`
- `clang/test/CodeGen/AArch64/poly-add.c` to
`clang/test/CodeGen/AArch64/neon/add.c`
Commit: 0e704a021a5b9c82ee59d855401ef427385e4af1
https://github.com/llvm/llvm-project/commit/0e704a021a5b9c82ee59d855401ef427385e4af1
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
Log Message:
-----------
[AMDGPU] Fix illegal AGPR reclassification in RewriteMFMAFormStage (#200972)
If src2 escapes rewrite group then bridge copy AGPR -> VGPR must be
inserted.
Fixes a regression after
https://github.com/llvm/llvm-project/pull/198555
Commit: d426cca8835e109069f60630f886574af273e803
https://github.com/llvm/llvm-project/commit/d426cca8835e109069f60630f886574af273e803
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp
M mlir/test/Dialect/SPIRV/Transforms/canonicalize.mlir
Log Message:
-----------
[mlir][SPIR-V] Guard UMod canonicalization against zero divisor (#203513)
Chained `spirv.UMod` with a zero outer divisor reached `APInt::urem`
which causes UB
Commit: 7125490395b06f850f3ae02ae7ae69a6b2a647c2
https://github.com/llvm/llvm-project/commit/7125490395b06f850f3ae02ae7ae69a6b2a647c2
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
Log Message:
-----------
[mlir][SPIR-V] Collapse duplicated i1-extension patterns in ArithToSPIRV (NFC) (#203247)
Commit: 43dc65d46b54415ea474b0bf0ad8b761444a7ba2
https://github.com/llvm/llvm-project/commit/43dc65d46b54415ea474b0bf0ad8b761444a7ba2
Author: Marina Taylor <marina_taylor at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
A llvm/test/Analysis/ValueTracking/known-non-zero-shr-add.ll
Log Message:
-----------
[ValueTracking] Infer non-zero from shr (add nuw A, B), C (#203039)
...if either A or B has a known-one bit at position >= C.
https://alive2.llvm.org/ce/z/ELYTjh
This eliminates null checks in some internal workloads.
Assisted-by: claude
Commit: ad6449fa73fd27b6d3493ab1999befd272e7fb31
https://github.com/llvm/llvm-project/commit/ad6449fa73fd27b6d3493ab1999befd272e7fb31
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
Log Message:
-----------
[gn] "port" 93e03fc2666e (#203536)
Commit: d6ddc21af729fc145477e75ada8621e27e017b4e
https://github.com/llvm/llvm-project/commit/d6ddc21af729fc145477e75ada8621e27e017b4e
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[gn build] Port b000f9032911 (#203537)
Commit: c8711e5db4fbe436a5aeede159e1a3c3eae08bf5
https://github.com/llvm/llvm-project/commit/c8711e5db4fbe436a5aeede159e1a3c3eae08bf5
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Windows/Common/BUILD.gn
Log Message:
-----------
[gn build] Port b57c32db810b (#203538)
Commit: e302e85180ab0601ee564237a8cd75184bef5feb
https://github.com/llvm/llvm-project/commit/e302e85180ab0601ee564237a8cd75184bef5feb
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port caea95990515 (#203539)
Commit: 71ff21aa50f07b0cadb929fe14fafda8b1f8243f
https://github.com/llvm/llvm-project/commit/71ff21aa50f07b0cadb929fe14fafda8b1f8243f
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/ObjectFile/Mach-O/BUILD.gn
Log Message:
-----------
[gn build] Port d0a1f86e7890 (#203540)
Commit: 422d559a3a3af94c9e74c098761b110d749e248a
https://github.com/llvm/llvm-project/commit/422d559a3a3af94c9e74c098761b110d749e248a
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/MC/BUILD.gn
Log Message:
-----------
[gn build] Port df75b5d458b9 (#203541)
Commit: 305faf498a4e0b52b40742c927af63ab2082e1a9
https://github.com/llvm/llvm-project/commit/305faf498a4e0b52b40742c927af63ab2082e1a9
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/readability/BUILD.gn
Log Message:
-----------
[gn build] Port fc1f754c397b (#203542)
Commit: 3255d4d7628719c4b6254db5780ec50862584896
https://github.com/llvm/llvm-project/commit/3255d4d7628719c4b6254db5780ec50862584896
Author: Drew Kersnar <dkersnar at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
A llvm/test/Bitcode/byte-constants.ll
Log Message:
-----------
[Bitcode] Decode small byte constants as signed values (#203408)
Decode small byte constants the same way we encode them. The bitcode
writer stores ConstantByte values as signed integers, so the reader must
rebuild them using the signed ConstantByte::get path. This has high-bit
values like b8 255 round-trip as their canonical signed form, b8 -1,
instead of tripping the APInt width assertion. This matches current i8
behavior.
Before the fix, the new test crashes in llvm-dis with: "APInt.h:
Assertion `llvm::isUIntN(BitWidth, val) && "Value is not an N-bit
unsigned value"' failed."
Bug found while investigating this PR
(https://github.com/llvm/llvm-project/pull/177908), which transitions
the LSV to emitting the byte type. Fix assisted by AI.
Commit: 09e3e004c66bea58525385486ab04327a51af9de
https://github.com/llvm/llvm-project/commit/09e3e004c66bea58525385486ab04327a51af9de
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
Log Message:
-----------
[gn] port 127a4c1a883d333 (LLVM_TARGETS_TO_BUILD for lldb shell tests) (#203547)
Commit: 6c3d7edcfa4a266681f19e6a002766c5a7066e34
https://github.com/llvm/llvm-project/commit/6c3d7edcfa4a266681f19e6a002766c5a7066e34
Author: anjenner <161845516+anjenner at users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
Log Message:
-----------
[AMDGPU][GISel] Add register bank legalization rules for amdgcn_cvt_sr_f16_f32. (#203253)
Commit: d46513abff5bfaf58de8169db033e54b9e24d7c2
https://github.com/llvm/llvm-project/commit/d46513abff5bfaf58de8169db033e54b9e24d7c2
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M bolt/lib/Profile/Heatmap.cpp
M bolt/test/X86/heatmap-preagg.test
Log Message:
-----------
[BOLT] Fix heatmap with external addresses (#203479)
External samples (X:0) were breaking heatmap printing, e.g.
```
0x00000000: O0x00000000: ........
```
Explicitly track `IsFirst` instead of relying on zero.
Test Plan:
updated heatmap-preagg.test
Commit: 52751a0fda17f0dac1c441aee6617ab1b1434f4d
https://github.com/llvm/llvm-project/commit/52751a0fda17f0dac1c441aee6617ab1b1434f4d
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/hip-toolchain-no-rdc.hip
Log Message:
-----------
[AMDGPU][SPIR-V] Fix treating SPIR-V input as the wrong LLVM-IR (#202986)
Summary:
This hack is intended for non-RDC AMDGCN.
Commit: c3a146a4e8fab800c621acc401dbdf1d0c960be8
https://github.com/llvm/llvm-project/commit/c3a146a4e8fab800c621acc401dbdf1d0c960be8
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for sched barriers intrinsics (#203425)
Add rules for sched barrier intrinsics. Note, there are regressions due
to AGPR results being copied back to VGPR un-necessarily. That will be
addressed in a future follow-up patch.
Commit: 8d2661b2d54e9dec96cba72ff5089c6fa7482bf3
https://github.com/llvm/llvm-project/commit/8d2661b2d54e9dec96cba72ff5089c6fa7482bf3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
Log Message:
-----------
[X86] combineConcatVectorOps - concat(rotate(x,a),rotate(y,b)) -> rotate(concat(x,y),concat(a,b)) (#203553)
128/256-bit rotates are widened in tablegen, we don't need to limit
these to VLX targets - any AVX512 target can perform these
We already have test coverage to ensure 128-bit XOP rotates don't get
concatenated to 256-bit
Commit: bdc06892cdd37c0a52717373ad7774136ca72b63
https://github.com/llvm/llvm-project/commit/bdc06892cdd37c0a52717373ad7774136ca72b63
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/test/Fir/mem2reg.mlir
Log Message:
-----------
[flang] Avoid invalid declare_value for promoted dummy-scope variables (#202498)
This fixes a verifier failure in mem2reg after inlining a CUDA device
procedure. When a promoted FIR alloca had an associated fir.declare with
a dummy_scope, mem2reg could create a fir.declare_value at a loop header
where the original dummy scope did not dominate.
Skip creating block-argument fir.declare_value ops for such
declarations, matching the existing replaced-value handling. Add a FIR
mem2reg regression test for the loop-header block argument case.
Commit: bbeb2d519171b57bbabb25ca07223c286cdecea2
https://github.com/llvm/llvm-project/commit/bbeb2d519171b57bbabb25ca07223c286cdecea2
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
A flang/test/Lower/OpenACC/Todo/acc-unstructured-combined-construct.f90
A flang/test/Lower/OpenACC/Todo/acc-unstructured-loop-construct.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
Log Message:
-----------
[OpenACC][flang] Emit NYI when unstructured loops are associated with OpenACC directives (#202948)
Commit: 168666950ea9cd85471053319e216399e9750028
https://github.com/llvm/llvm-project/commit/168666950ea9cd85471053319e216399e9750028
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/IR/Value.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
Log Message:
-----------
[IR] Make CanBeFreed calculation optional (NFC) (#203490)
Make the CanBeFreed argument of getPointerDereferenceableBytes() a
pointer, so that nullptr can be passed if we're not interested in
whether frees are possible or not.
Nearly all places don't actually care about frees, including BasicAA,
which is the hottest caller of this API. This improves compile-time when
deref-at-point semantics are enabled.
I've kept the argument required so that callers still have to make an
explicit choice to ignore frees. (I'd be open to making it optional
though, given that only a single caller actually cares...)
Commit: c5654d53c008522d2da165f05b682aafa36d7189
https://github.com/llvm/llvm-project/commit/c5654d53c008522d2da165f05b682aafa36d7189
Author: Yuan Suo <suoyuan666 at s5n.xyz>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/test/Sema/LifetimeSafety/annotation-suggestions.cpp
M clang/test/Sema/LifetimeSafety/nocfg.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
Log Message:
-----------
[LifetimeSafety] Introduce buildOriginFlowChain for use-after-scope (#199345)
After adding `buildOriginFlowChain`, we need to choose a diagnostic type
that is as simple as possible to verify its feasibility during `Sema`
diagnostics.
I did not choose the annotation suggestions described in
https://github.com/llvm/llvm-project/pull/188467/#issuecomment-4359071778
as the first target to implement, because it does not seem to occur
within a single CFG block. The `IssueFact` always resides in the block
preceding the `OriginEscapesFact`, which causes me to always get an
empty `OriginFlowChain`.
Since we use `buildOriginFlowChain`, we can directly trace distinct
assignment steps that occur within a single source-level expression. For
example:
```cpp
#include <vector>
#include <string>
template<class... T> void use(T... arg);
void operator_star_arrow_of_iterators_false_positive_no_cfg_analysis() {
std::vector<std::pair<int, std::string>> v;
const char* p = v.begin()->second.data();
const char* q = (*v.begin()).second.data();
const std::string& r = (*v.begin()).second;
auto temporary = []() { return std::vector<std::pair<int, std::string>>{{1, "1"}}; };
const char* x = temporary().begin()->second.data();
const char* y = (*temporary().begin()).second.data();
const std::string& z = (*temporary().begin()).second;
use(p, q, r, x, y, z);
}
```
The code above produces the following diagnostic output:
```txt
pr.cpp:13:19: warning: local temporary object does not live long enough [-Wlifetime-safety-use-after-scope]
13 | const char* x = temporary().begin()->second.data();
| ^~~~~~~~~~~
pr.cpp:13:52: note: destroyed here
13 | const char* x = temporary().begin()->second.data();
| ^
pr.cpp:13:19: note: expression aliases the storage of local temporary object
13 | const char* x = temporary().begin()->second.data();
| ^~~~~~~~~~~~~~~~~~~
pr.cpp:13:19: note: expression aliases the storage of local temporary object
13 | const char* x = temporary().begin()->second.data();
| ^~~~~~~~~~~~~~~~~~~~~
pr.cpp:13:19: note: expression aliases the storage of local temporary object
13 | const char* x = temporary().begin()->second.data();
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
pr.cpp:16:16: note: later used here
16 | use(p, q, r, x, y, z);
| ^
pr.cpp:15:28: warning: local temporary object does not live long enough [-Wlifetime-safety-use-after-scope]
15 | const std::string& z = (*temporary().begin()).second;
| ^~~~~~~~~~~
pr.cpp:15:49: note: destroyed here
15 | const std::string& z = (*temporary().begin()).second;
| ^
pr.cpp:15:28: note: expression aliases the storage of local temporary object
15 | const std::string& z = (*temporary().begin()).second;
| ^~~~~~~~~~~~~~~~~~~
pr.cpp:15:27: note: expression aliases the storage of local temporary object
15 | const std::string& z = (*temporary().begin()).second;
| ^~~~~~~~~~~~~~~~~~~~
pr.cpp:16:22: note: later used here
16 | use(p, q, r, x, y, z);
| ^
pr.cpp:14:21: warning: local temporary object does not live long enough [-Wlifetime-safety-use-after-scope]
14 | const char* y = (*temporary().begin()).second.data();
| ^~~~~~~~~~~
pr.cpp:14:54: note: destroyed here
14 | const char* y = (*temporary().begin()).second.data();
| ^
pr.cpp:14:21: note: expression aliases the storage of local temporary object
14 | const char* y = (*temporary().begin()).second.data();
| ^~~~~~~~~~~~~~~~~~~
pr.cpp:14:20: note: expression aliases the storage of local temporary object
14 | const char* y = (*temporary().begin()).second.data();
| ^~~~~~~~~~~~~~~~~~~~
pr.cpp:14:19: note: expression aliases the storage of local temporary object
14 | const char* y = (*temporary().begin()).second.data();
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
pr.cpp:16:19: note: later used here
16 | use(p, q, r, x, y, z);
| ^
3 warnings generated.
```
---------
Signed-off-by: Yuan Suo <suoyuan666 at s5n.xyz>
Commit: 422af7cca672a717bd9505a486e287fa2734bbc9
https://github.com/llvm/llvm-project/commit/422af7cca672a717bd9505a486e287fa2734bbc9
Author: Quentin Colombet <quentin.colombet at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MIRPrintingPass.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/VirtRegMap.cpp
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-phys.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-split.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-self-split.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash.mir
Log Message:
-----------
[MIR] Save internal VirtRegMap state in MIR (#197361)
Adds two optional fields to the per-vreg YAML record so MIR tests can
express VirtRegMap state that previously had no representation:
registers:
- { id: 1, class: vgpr_32, split-from: '%0', assigned-phys: '$vgpr5' }
Testing passes that consume sibling-register information (e.g.
InlineSpiller) requires constructing a VirtRegMap with split
relationships from a MIR test, which implies triggering live-range
splitting at minimum and make reproducers unnecessarily complicated.
So this change introduces a mechanism to serialize/deserialize the state
of the VirtRegMap pass.
Mechanism:
- For serialization:
- MIRPrinter emits the new fields only when the VirtRegMap is available.
- For deserialization:
- MIRParser stashes parsed entries in the MachineRegisterInfo object
- VirtRegMap::init() drains the stash via assignVirt2Phys and
setIsSplitFromReg, then clears it.
Validation at parse time:
- 'assigned-phys' must be a physical register.
- 'split-from' must reference a different vreg than 'id'.
- 'split-from' physregs / named-vreg references already rejected
by parseStandaloneVirtualRegister.
I'm not super happy about stashing the VRM info in the MRI, but that's
a small price to pay.
Commit: 1b774ab021698428374815fb8d4d88855c3b2a48
https://github.com/llvm/llvm-project/commit/1b774ab021698428374815fb8d4d88855c3b2a48
Author: Mikołaj Piróg <mikolaj.maciej.pirog at intel.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/test/CodeGen/X86/stack-coloring-setjmp.ll
Log Message:
-----------
[StackColoring] Cleanup stack-coloring test (NFC) (#203551)
This simply applies postcommit suggestions made here:
https://github.com/llvm/llvm-project/pull/199959
Commit: 7814cc9454cf454acdc7385fc41809a6bdf5d7f8
https://github.com/llvm/llvm-project/commit/7814cc9454cf454acdc7385fc41809a6bdf5d7f8
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/Basic/arm_sve.td
A clang/test/CodeGen/AArch64/sme2p3-intrinsics/acle_sme2p3_luti6.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6_lane_x2.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2p3.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2p3___sme_AND_LP_sve2p3_OR_sme2p3_RP.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve2p3.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme2p3.c
A clang/test/Sema/aarch64-sme2p3-intrinsics/acle_sme2p3_imm.c
M clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_imm.cpp
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/sme2p3-intrinsics-luti6.ll
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics-luti6.ll
Log Message:
-----------
[AArch64][clang][llvm] Add ACLE Armv9.7 lookup table intrinsics (#187046)
Add support for the following Armv9.7-A Lookup Table (lut)
instruction intrinsics, as defined in the ACLE[1]:
SVE2.3:
```c
// Variants are also available for: _u8 _mf8
svint8_t svluti6[_s8](svint8x2_t table, svuint8_t indices);
```
SVE2.3 and SME2.3:
``` c
// Variants are also available for _u16_x2 and _f16_x2.
svint16_t svluti6_lane[_s16_x2](svint16x2_t table, svuint8_t indices, uint64_t imm_idx);
```
SME2.3:
```c
// Variants are also available for: _u16, _f16 and _bf16.
svint16x4_t svluti6_lane_s16_x4[_s16_x2](svint16x2_t table, svuint8x2_t indices, uint64_t imm_idx);
// Variants are also available for: _u8 and _mf8.
svint8x4_t svluti6_zt_s8_x4(uint64_t zt0, svuint8x3_t zn) __arm_streaming __arm_in("zt0");
// Variants are also available for: _u8 and _mf8.
svint8_t svluti6_zt_s8(uint64_t zt0, svuint8_t zn) __arm_streaming __arm_in("zt0");
```
[1] https://github.com/ARM-software/acle/pull/428/
Commit: 5906827e155cc5fca10cd505b88a4e21b861d65b
https://github.com/llvm/llvm-project/commit/5906827e155cc5fca10cd505b88a4e21b861d65b
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.h
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.h
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h
Log Message:
-----------
[lldb][Windows] Forward OUTPUT_DEBUG_STRING_EVENT through lldb-server (#203546)
Hoist `ReadDebugString` into `ProcessDebugger` so both plugins share it,
then add
`NativeProcessWindows::OnDebugString` that reads the string, converts
UTF-16 to
UTF-8 when needed, and delivers via `NativeDelegate::NewProcessOutput`.
Fixes `Process/Windows/output_debug_string.cpp` on Windows under
`LLDB_USE_LLDB_SERVER=1`.
Commit: 9f3ac763bd8c4be2db1a97cec13bb59c87a9595f
https://github.com/llvm/llvm-project/commit/9f3ac763bd8c4be2db1a97cec13bb59c87a9595f
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
Log Message:
-----------
[MLIR][XeGPU] Fix issue with expandDim (#203299)
In case, sgData is replicated or
bool sgDataReplicated = hasSgData && origSgDataDim ==
computeProduct(targetShape);
sgDataReplicate is evaluated to "true"
dimSizeCap and perSgShape shouldn't be divided by expSgLayout
Add a regression test (shape_cast_collapse_replicated) covering the
replicated sg_data collapse.
Commit: 9bbed741e260753de029fcf7b22844fe23362a39
https://github.com/llvm/llvm-project/commit/9bbed741e260753de029fcf7b22844fe23362a39
Author: dibrinsofor <64705019+dibrinsofor at users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/ext-narrow-index.ll
M llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
A llvm/test/CodeGen/AArch64/shuffle-slide-to-shift.ll
Log Message:
-----------
[AArch64] Optimize vector slide shuffles with zeros to use shift instructions (#185170)
We currently emit `movi`+`ext` instructions when generating code for
shuffle slides of a 64-bit vector left/right and fill it with zeros.
This patch optimizes these patterns to use a single `ushr`/`shl`
instruction instead.
Example:
```llvm
define <8 x i8> @slide_left(<8 x i8> %v) {
%r = shufflevector <8 x i8> %v, <8 x i8> zeroinitializer,
<8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
ret <8 x i8> %r
}
```
Before, we generate:
```
movi v1.2d, #0
ext v0.8b, v0.8b, v1.8b, #1
```
Now:
```
ushr d0, d0, #8
```
Fixes: #183398
Alive2 proof: https://alive2.llvm.org/ce/z/QaW5CQ
---------
Signed-off-by: Dibri Nsofor <dibrinsofor at gmail.com>
Commit: c9938eb76ca653abff8d0b7c99bd74aec57c4758
https://github.com/llvm/llvm-project/commit/c9938eb76ca653abff8d0b7c99bd74aec57c4758
Author: nirhersh <77844231+nirhersh at users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/lib/Dialect/Arith/IR/ArithDialect.cpp
M mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp
M mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir
Log Message:
-----------
[mlir][arith] Implement ValueBoundsOpInterface for min/max ops (#203269)
Add ValueBoundsOpInterface external models for the arith integer min/max operations: arith.minsi and arith.maxsi.
---------
Co-authored-by: Nir Herscovici <nir.herscovici at mobileye.com>
Commit: c62768b10e5e16c494eef8289452a7d7d97798bf
https://github.com/llvm/llvm-project/commit/c62768b10e5e16c494eef8289452a7d7d97798bf
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/test/Target/LLVMIR/nvvm/tensormap_replace_invalid.mlir
Log Message:
-----------
[MLIR][NVVM] Fix valid range of ord in tensormap.replace op (#202853)
Fixes the valid range of the `ord` attribute in the NVVM dialect
`tensormap.replace` op to be `0-4` as indicated in the PTX ISA.
PTX ISA Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-tensormap-replace
Commit: 2d1fb738d6f9eb109a2f1e0405397565f25fece4
https://github.com/llvm/llvm-project/commit/2d1fb738d6f9eb109a2f1e0405397565f25fece4
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLAttrs.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLEnums.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/test/Dialect/GPU/module-to-binary-rocdl.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/module-roundtrip.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
A mlir/test/Target/LLVMIR/rocdl-module-flags.mlir
Log Message:
-----------
[mlir][LLVM][ROCDL] Add buffer oob mode module flags, flag interfaces (#202729)
Now that the out-of-bounds mode for buffer accesses will be controlled
by a module flag and is no longer a function of the subtarget triple (as
of #160922) and since `ptr addrpace(7)` lowering will start respecting
this mode soon, add MLIR-level support for setting this flag.
After a few iterations, I think adding this module flag to
`llvm.module.flags` but adding interfaces for module flag attributes (so
that those wishing to set this flag don't need to know it has `max`
combining semantics or look up the enum values) is a
minimally-disruptive way to get a more ergonomic wrapper around this
functionality.
AI note: AI generated the code hehe, I reviewed it. The documentation
update to ModuleFlagsOp is mine.
(The LLVM PR that would want people to start explicitly setting
`relaxed` is #134329)
Co-authored-by: Codex <codex at openai.com>
Commit: 484b955581d976f97a47ef621c441e21c231aa23
https://github.com/llvm/llvm-project/commit/484b955581d976f97a47ef621c441e21c231aa23
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/test/CIR/CodeGen/ternary-throw.cpp
Log Message:
-----------
[CIR] Implement throw within an aggregate expression (#203404)
This implements CIR support for throwing an exception from within a
branch of a ternary expression that represents an aggregate prvalue. We
previously had support for throwing an exception within a ternary
aggregate expression, but when the expression uses a prvalue, it goes
through a different code path. The new implementation is just calling an
existing function from a different place. The bulk of what's being added
here is the testing.
Commit: 99a37aedebd7c69680e74ac83769a11eaefef1e7
https://github.com/llvm/llvm-project/commit/99a37aedebd7c69680e74ac83769a11eaefef1e7
Author: Quentin <qcoelho at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/ADT/StringExtras.h
Log Message:
-----------
[ADT][NFC] Fix documentation for arrayRefFromStringRef (#203430)
The documentation was describing the opposite behavior of what it does.
Commit: 17207c8feb9fc6c576ce820ff4583e337dc0452e
https://github.com/llvm/llvm-project/commit/17207c8feb9fc6c576ce820ff4583e337dc0452e
Author: Utkarsh Saxena <usx at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/test/Sema/LifetimeSafety/annotation-suggestions.cpp
M clang/test/Sema/LifetimeSafety/nocfg.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
Log Message:
-----------
[LifetimeSafety] Change "local temporary object" to "temporary object" in diagnostics (#203573)
Commit: 878bbacfb0e6ced7c0313d5f7c097d7c94a1c4da
https://github.com/llvm/llvm-project/commit/878bbacfb0e6ced7c0313d5f7c097d7c94a1c4da
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/MC/MCWin64EH.cpp
M llvm/lib/Support/Win64EH.cpp
M llvm/test/MC/COFF/seh-unwindv3-inheritance.s
M llvm/test/tools/llvm-objdump/COFF/win64-unwindv3-multi-epilog.yaml
M llvm/test/tools/llvm-readobj/COFF/unwind-x86_64-v3-multi-epilog.yaml
M llvm/tools/llvm-objdump/COFFDump.cpp
M llvm/tools/llvm-readobj/Win64EHDumper.cpp
Log Message:
-----------
[win][x64] Windows x64 unwind v3: Update epilog inheritance per spec clarification (#202778)
The Windows x64 unwind v3 spec was clarified
(MicrosoftDocs/cpp-docs#5936) to state that an EPILOG_INFO_V3 record
with `NumberOfOps == 0` inherits its effective fields from the first
*preceding* descriptor with `NumberOfOps != 0` (the "base"), not the
immediately preceding one. Additionally, Flags bits 0 and 1 are no
longer inherited; the producer must replicate them so they match the
base descriptor.
- Encoder (MCWin64EH.cpp): compare each epilog against the tracked base
descriptor, and emit EPILOG_INFO_LARGE in inherited descriptors' own
flags byte.
- Decoder (Win64EH.cpp): track the base index and inherit from it; keep
the record's own flags byte instead of copying the previous record's.
- Dumpers (llvm-readobj, llvm-objdump): reword "previous epilog" to
"base epilog".
- Tests: update multi-epilog expectations and add a LARGE
inherited-epilog case to seh-unwindv3-inheritance.s.
Commit: 528e6f9a030c4b3bf760807c22c98f17fb582f5f
https://github.com/llvm/llvm-project/commit/528e6f9a030c4b3bf760807c22c98f17fb582f5f
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/test/CodeGen/AArch64/sme-intrinsics-mova-insert.ll
Log Message:
-----------
[AArch64] Avoid creating a new generic constant in SelectSMETileSlice (#203344)
This was creating a new ISD::Constant node during instruction selection,
which may also need lowering (e.g., to a `mov gpr, wzr`). The issue with
this is the new constant node will not end up on the instruction
selection worklist, as the complex pattern executes after the worklist
has been prepared. This means the constant will lower directly to an
immediate. This issue was hidden in some cases by `getConstant()`
returning a pre-existing `ISD::Constant` node already within the
instruction selection worklist.
This patch works around this by directly emitting a `CopyFromReg WZR`
within SelectSMETileSlice, which does not need further instruction
selection.
Fixes #203295
Commit: 9240c64f4528064cec31e8875fb891b473f8ca7c
https://github.com/llvm/llvm-project/commit/9240c64f4528064cec31e8875fb891b473f8ca7c
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/IR/BundleAttributes.h
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/IR/BundleAttributes.cpp
Log Message:
-----------
[LVI][ValueTracking] Merge checking whether assumes imply nonnull (#203523)
Commit: eaef650f57900b36751dea4e0383de1e73cdff29
https://github.com/llvm/llvm-project/commit/eaef650f57900b36751dea4e0383de1e73cdff29
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
A clang/test/CIR/CodeGen/cxx-construct-lvalue.cpp
Log Message:
-----------
[CIR] Implement handling for CXXConstructLValue expressions (#203402)
This implements the handling to emit an l-value for CXXConstructExpr and
CXXTemporaryObjectExpr expressions. This is a simple copy from the
equivalent code in classic codegen and uses existing CIR code for most
of the actual work.
A multi-argument constructor call written with explicit type syntax
produces a CXXTemporaryObjectExpr. Using it as the base of a member
access reaches emitLValue with that expression class. A single-argument
constructor call performs a constructor conversion, so the base of the
member access is a CXXFunctionalCastExpr whose subexpression is a
CXXConstructExpr. emitCastLValue forwards to the subexpression, reaching
emitLValue with the CXXConstructExpr class.
Commit: e476b23c5facd1705f06ee60f1e62869c638f395
https://github.com/llvm/llvm-project/commit/e476b23c5facd1705f06ee60f1e62869c638f395
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M compiler-rt/test/fuzzer/fork-sigusr.test
M compiler-rt/test/fuzzer/merge-sigusr.test
M compiler-rt/test/fuzzer/sigint.test
M compiler-rt/test/fuzzer/sigusr.test
Log Message:
-----------
[Fuzzer] Make signal tests work with internal shell (#203445)
Wrap some commands in bash as it seemed like the least bad option. The
alternative is to use setsid and run the other commands in the internal
shell, but them it's impossible to use wait and we run into reliability
issues because of that.
Commit: 473ca91cdb03d01394eea440ea4f3a14cdc04b6e
https://github.com/llvm/llvm-project/commit/473ca91cdb03d01394eea440ea4f3a14cdc04b6e
Author: Jan Korous <jkorous at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Frontend/FrontendOptions.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendAction.cpp
M clang/test/Analysis/Scalable/PointerFlow/external-inline-function-in-multi-tu.test
M clang/test/Analysis/Scalable/call-graph.cpp
A clang/test/Analysis/Scalable/cli-errors-compilation-unit-id.cpp
M clang/test/Analysis/Scalable/command-line-interface.cpp
M clang/test/Analysis/Scalable/downgradable-errors.cpp
M clang/test/Analysis/Scalable/extraction-works-alongside-compilation.cpp
M clang/test/Analysis/Scalable/help.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendActionTest.cpp
Log Message:
-----------
[clang][ssaf] Add --ssaf-compilation-unit-id= flag (#203345)
The TU summary extractor previously sourced the CompilationUnit
namespace name from clang's `InFile` argument, which made the identity
of a TU summary depend on the file path the build system passed to
clang. Have the build system pass the identifier directly:
- New driver/cc1 option `--ssaf-compilation-unit-id=<id>`, marshalled
into `FrontendOptions::SSAFCompilationUnitId`.
- `TUSummaryRunner` builds its `BuildNamespace(CompilationUnit, ...)`
from the new option's value; `InFile` is no longer threaded into the
runner.
- New diagnostic `warn_ssaf_tu_summary_requires_compilation_unit_id`
(under `-Wscalable-static-analysis-framework`, `DefaultError`) fires
when `--ssaf-tu-summary-file=` is set without a non-empty
`--ssaf-compilation-unit-id=`. The runner falls back to the wrapped
consumer alone in that case, matching the existing setup-time SSAF
diagnostics.
Assisted-By: Claude Opus 4.7
Commit: fdd939dce1eb145e386dc3242661c3a73b759e4f
https://github.com/llvm/llvm-project/commit/fdd939dce1eb145e386dc3242661c3a73b759e4f
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/Transforms/Transforms.h
M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Dialect/XeGPU/Utils/CMakeLists.txt
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute-unit.mlir
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
Log Message:
-----------
[MLIR][XeGPU] Use context-aware type converter in WgToSgDistribute and Blocking pass (#194685)
This PR replaces the TypeConverter in xegpu-wg-to-sg-distribute and
xegpu-blocking with a context-aware converter that picks each value's
converted type from the layout attached to its defining op/use, removing
the need for the UnrealizedConversionCastOpPattern workaround for scf
ops.
Commit: 6dbe068edef96c13930471d602fd5fb876e9da04
https://github.com/llvm/llvm-project/commit/6dbe068edef96c13930471d602fd5fb876e9da04
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/MC/MCWin64EH.cpp
Log Message:
-----------
[Win][x64] Fix -Wunused-variable (#203591)
BaseEpiFlags is only used in assertions, so mark it maybe_unused to
avoid the warning in release builds.
Commit: 0a9cf8c6c3038f1a02fa2051d12c9e9d7ddb4aad
https://github.com/llvm/llvm-project/commit/0a9cf8c6c3038f1a02fa2051d12c9e9d7ddb4aad
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes fdd939d (#203593)
This fixes fdd939dce1eb145e386dc3242661c3a73b759e4f.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: e4a63425ba266f6027e7d257c9a79141c26aa8d8
https://github.com/llvm/llvm-project/commit/e4a63425ba266f6027e7d257c9a79141c26aa8d8
Author: Jiaqi He <heturing at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/riscv/hwprobe.inc
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/TargetParser/Host.cpp
Log Message:
-----------
[RISC-V] Add newer Linux hwprobe extensions detection (#192761)
Commit: 660771d4359b14fe56a5eef19c33f93475aee39e
https://github.com/llvm/llvm-project/commit/660771d4359b14fe56a5eef19c33f93475aee39e
Author: Jiachen Yuan <jiacheny at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/ADT/Bitset.h
M llvm/unittests/ADT/BitsetTest.cpp
Log Message:
-----------
Reapply "[ADT] Bitset: add shift operators, word accessors, and etc" (#195874)
Reapplies #193400, which was reverted in #195848 because it broke
buildbots with:
```
Bitset.h:271: error: static assertion failed: Unsupported word size
```
Root cause: a `static_assert(BitwordBits == 32, ...)` inside the
discarded `else` branch of `if constexpr (BitwordBits == 64)` in
`getWord64()`. The assert's condition is non-template-dependent
(`BitwordBits` derives from `sizeof(uintptr_t)`, not from `NumBits`), so
it is checked even though the branch is discarded, and fires on 64-bit
hosts. Related:
https://stackoverflow.com/questions/38304847/how-does-a-failed-static-assert-work-in-an-if-constexpr-false-block
Fix: drop the redundant inner `static_assert`. The class-level
`static_assert(BitwordBits == 64 || BitwordBits == 32, ...)` already
enforces the same invariant.
No functional change beyond the original PR.
---------
Co-authored-by: Rahul Joshi <rjoshi at nvidia.com>
Commit: 5a52d68d6b030b155580ff03f5f8ad0cc9dc2fd9
https://github.com/llvm/llvm-project/commit/5a52d68d6b030b155580ff03f5f8ad0cc9dc2fd9
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/MC/MCParser/COFFMasmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/test/MC/COFF/seh-unwindv3-error.s
A llvm/test/tools/llvm-ml/beginepilog_error.asm
M llvm/test/tools/llvm-ml/builtin_symbols.asm
A llvm/test/tools/llvm-ml/epilog_directive_errors.asm
A llvm/test/tools/llvm-ml/epilog_directives.asm
A llvm/test/tools/llvm-ml/proc_frame_v3.asm
A llvm/test/tools/llvm-ml/prolog_directive_errors.asm
A llvm/test/tools/llvm-ml/unwindv3_required_errors.asm
M llvm/tools/llvm-ml/Opts.td
M llvm/tools/llvm-ml/llvm-ml.cpp
Log Message:
-----------
[llvm-ml] Add MASM unwind v3 support for x64 exception handling and improve MSVC compat (#202809)
New command-line options:
- `/unwindv3`: Enable V3 unwind information format
New MASM directives:
- `.push2reg` / `.pop2reg`: Push/pop register pairs (PUSH2/POP2)
- `.beginepilog` / `.endepilog`: Delimit epilog unwind regions
- `.popreg`, `.freestack`, `.restorereg`, `.restorexmm128`,
`.unsetframe`: Epilog counterparts of existing prolog directives
- `.pushframe code`: MASM syntax for interrupt handlers with error codes
New built-in symbol:
- `@UnwindVersion`: Returns the current x64 unwind version being used.
Error diagnostics:
- Prolog directives after `.endprolog` are diagnosed
- Epilog directives outside `.beginepilog`/`.endepilog` are diagnosed
- Nested `.beginepilog` is diagnosed
- Unwind v3 directives or using extended registers in directives without
unwind v3 are diagnosed
Commit: f2957d7a56372cf8bd2b48aec81ae7c0fb38813f
https://github.com/llvm/llvm-project/commit/f2957d7a56372cf8bd2b48aec81ae7c0fb38813f
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
Log Message:
-----------
[flang][OpenMP] Add missing check for empty argument list (#203592)
Commit: 5036a80a20a6749f95b77a2c08786f42fdd056ac
https://github.com/llvm/llvm-project/commit/5036a80a20a6749f95b77a2c08786f42fdd056ac
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
Log Message:
-----------
[HLSL][NFC] Remove unused location argument (#203467)
The location argument was just passed around but never used.
Commit: 2a72cd87a5bb9db73708661e8760ff710460ae11
https://github.com/llvm/llvm-project/commit/2a72cd87a5bb9db73708661e8760ff710460ae11
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/unittests/Support/GlobPatternTest.cpp
Log Message:
-----------
[NFC][Support] Add test for inverted slash-agnostic matching (#203290)
Add a test case to GlobPatternTest to verify that inverted character
classes containing slashes (e.g. [^/] or [^\\]) behave correctly
under SlashAgnostic mode (i.e. they do not match either slash).
Assisted-by: Gemini
Commit: 64381998961b4b9324ab5a6f6015b285b59d6bb6
https://github.com/llvm/llvm-project/commit/64381998961b4b9324ab5a6f6015b285b59d6bb6
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
M llvm/test/Transforms/LoopVectorize/epilog-iv-select-cmp.ll
Log Message:
-----------
[VPlan] Introduce m_SelectLike and use to support 2-operand blends. (#194729)
We should be able to treat 2-operand blends like select by most VPlan
code. Add a new m_SelectLike matcher and use in places that only use the
matcher to extract operands.
Overall this leads to a small number of improvements in RISCV (~10 files
changed in a large IR corpus) and 2 loops changed on AArch64 with
tail-folding forced.
PR: https://github.com/llvm/llvm-project/pull/194729
Commit: fda7a72af7a76ac6b51a8a1b1222f878d76405ed
https://github.com/llvm/llvm-project/commit/fda7a72af7a76ac6b51a8a1b1222f878d76405ed
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1251_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
Log Message:
-----------
[AMGDPU] Add gfx1251 V_PK_MIN/MAX_NUM_F64 (#203596)
Also legalizes v2f64 fcanonicalize.
Commit: 2c1b71af78df9d7c22e225069971d3276d91d546
https://github.com/llvm/llvm-project/commit/2c1b71af78df9d7c22e225069971d3276d91d546
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Transforms/LoopVectorize/RISCV/i128-trip-count-evl.ll
Log Message:
-----------
[VPlan] Compute URem via APInt in materializeVectorTripCount (#203604)
materializeVectorTripCount has a shortcut for scalable steps: if the
constant trip count is divisible by the maximum possible runtime step,
the vector trip count equals the trip count directly. This called
APInt::getZExtValue unconditionally, which asserts when the constant
value needs more than 64 bits.
Compute the URem in APInt to fix the crash.
Commit: 1060a6be0a471106fd65a3f16937ee1c588dabed
https://github.com/llvm/llvm-project/commit/1060a6be0a471106fd65a3f16937ee1c588dabed
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
A llvm/test/CodeGen/DirectX/switch-to-lookup-table-i16-narrowing.ll
A llvm/test/CodeGen/DirectX/switch-to-lookup-table-no-i8-narrowing.ll
Log Message:
-----------
[SimplifyCFG][DirectX] Honor target minimum lookup table element width (#203103)
fixes #202481
This change adds a `TTI::getMinimumLookupTableEntryBitWidth()` (default
`8`) and fold it
into SimplifyCFG's `NeededBitWidth` computation so targets can prevent
unsupported
narrow lookup tables. DirectX returns 32 (or 16 with native 16-bit
types) so tables
never narrow to the unsupported i8 type.
> Assisted by Claude Opus 4.8
Commit: 10508afd0b14ffcf6819665e31d64d77ccd45d3f
https://github.com/llvm/llvm-project/commit/10508afd0b14ffcf6819665e31d64d77ccd45d3f
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowExtractor.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.h
M clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
Log Message:
-----------
Reland "[SSAF][Extractor] Make hard errors in PointerFlow and UnsafeBufferUsage Extractors quiet (#201953)" (#203602)
Reverted 7dcd1d2ad104c3f9748370a42dc775cd6e7e34dc and added '#ifndef
NDEBUG' guards for tests using 'llvm::setCurrentDebugType'.
Original message:
Hard errors were used in extractors during development to quickly
identify unsupported language constructs. This commit converts them to
DEBUG_WITH_TYPE so that these errors are silenced in release builds.
In addition, translating unsupported language constructs now silently
results in an empty EntityPointerLevelSet. The PointerFlowExtractor will
skip empty sets for either the source or the destination when building
edges to avoid an ill-formed edge set data structure.
rdar://178747892
Commit: 0b128394b9c796ebe4efd9e0dde38976fb291798
https://github.com/llvm/llvm-project/commit/0b128394b9c796ebe4efd9e0dde38976fb291798
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
A llvm/test/tools/llvm-diff/callsite-assumption-passing.ll
M llvm/tools/llvm-diff/lib/DifferenceEngine.cpp
Log Message:
-----------
[llvm-diff] Respect AllowAssumptions in diffCallSites (#203597)
diffCallSites always built an AssumptionContext, so call sites made
optimistic equivalence assumptions even when the caller disabled them.
This made matchForBlockDiff over-match, and the re-check in unify() then
hit the "structural differences second time around?" assertion.
Thread the caller's AssumptionContext into diffCallSites so call sites
honor the no-assumptions request like every other instruction kind.
Fixes #184133
Commit: 12d95c65fc99a3d5686f1d409572d1965fd653b1
https://github.com/llvm/llvm-project/commit/12d95c65fc99a3d5686f1d409572d1965fd653b1
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
R llvm/test/Transforms/LICM/vector-insert.ll
Log Message:
-----------
Revert "[LICM] Allow hoisting of InsertElementInst's past non-hoistable InsertElementInsts" (#203611)
Reverts llvm/llvm-project#200532
Commit: 0526807f89803b394fcebc87dfc234e57513986e
https://github.com/llvm/llvm-project/commit/0526807f89803b394fcebc87dfc234e57513986e
Author: Maryam Moghadas <maryammo at ca.ibm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
A clang/test/AST/tyloctype_alignment.cpp
Log Message:
-----------
[clang][z/OS] Add test for TypeLoc tail padding alignment (#202710)
This adds a test for the TypeLoc tail padding fix that was merged in
commit 89305c3.
Commit: 5f51294647b3c4c08dfd0e455b1a997074864d26
https://github.com/llvm/llvm-project/commit/5f51294647b3c4c08dfd0e455b1a997074864d26
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaOverload.cpp
A clang/test/Sema/atomic-conversions-to-int.cpp
Log Message:
-----------
Fix contextual implicit conversions to int: with _Atomic (#203522)
PerformContextualImplicitConversion was performing
default-lvalue-conversions, then basing decisions on viable conversion
functions on this type However, when we then went to add the candidates
we were using the 'old' value (pre-conversion) of the type, resulting in
us regaining the lost 'atomic' from the default Lvalue conversion.
This patch updates the 'from' variable to be the converted value so all
conversions are done post-conversion.
Fixes: #201770
Commit: ce09519f40a6d76ec231ef8e4630c0d85c8cdaa5
https://github.com/llvm/llvm-project/commit/ce09519f40a6d76ec231ef8e4630c0d85c8cdaa5
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/test/Transforms/ConstraintElimination/geps-unsigned-predicates.ll
Log Message:
-----------
[ConstraintElim] Add test with negative offset and NUW only GEP (NFC) (#203614)
Add test currently mis-compiled with NUW only GEP.
https://alive2.llvm.org/ce/z/7G8uE3
Commit: 327ce1bb0cd56e74bfd79f51463e6c0a81905a25
https://github.com/llvm/llvm-project/commit/327ce1bb0cd56e74bfd79f51463e6c0a81905a25
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M compiler-rt/test/fuzzer/lit.cfg.py
Log Message:
-----------
[Fuzzer] Use the internal shell by default (#203450)
The external shell is going away soon and the internal shell is superior
in most ways (platform compatibility, performance, debugging). This now
causes no test failures and is blocking deprecation of the external
shell, so switch over.
Commit: b312ae01043b75637f4fd4dbaf66a09907f63c22
https://github.com/llvm/llvm-project/commit/b312ae01043b75637f4fd4dbaf66a09907f63c22
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
A llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1251_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
Log Message:
-----------
[AMDGPU] Add gfx1251 V_PK_ADD/SUB_NC_U64 (#203607)
Commit: 87d29e3f438c9c02390a4260e9a1bc7712f882c2
https://github.com/llvm/llvm-project/commit/87d29e3f438c9c02390a4260e9a1bc7712f882c2
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
Log Message:
-----------
[AMDGPU] NFC: Drop constexpr from getFlavor*Name functions (#203603)
It seems specifying these as constexpr was causing some buildbot
failures due to llvm_unreachable --
```
[1/123] Building CXX object lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o
FAILED: lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o
/usr/bin/c++ -DLLVM_EXPORTS -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GLIBCXX_USE_CXX11_ABI=1 -D_GNU_SOURCE -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_EXTENSIVE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/path/to/build.AArch64.Release.main/lib/Target/AMDGPU -I/path/to/llvm-project/llvm/lib/Target/AMDGPU -I/path/to/build.AArch64.Release.main/include -I/path/to/llvm-project/llvm/include -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror=date-time -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wno-uninitialized -Wno-nonnull -Wno-class-memaccess -Wno-array-bounds -Wno-noexcept-type -Wdelete-non-virtual-dtor -Wno-comment -Wno-misleading-indentation -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -std=c++17 -fvisibility=hidden -UNDEBUG -fno-exceptions -funwind-tables -fno-rtti -MD -MT lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o -MF lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o.d -o lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o -c /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
In file included from /path/to/llvm-project/llvm/include/llvm/ADT/Hashing.h:49,
from /path/to/llvm-project/llvm/include/llvm/ADT/ArrayRef.h:12,
from /path/to/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNSubtarget.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNRegPressure.h:20,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h:16,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp:14:
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getFlavorName(llvm::AMDGPU::InstructionFlavor)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:67: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown InstructionFlavor");
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getFlavorShortName(llvm::AMDGPU::InstructionFlavor)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:95: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown InstructionFlavor");
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getReasonName(llvm::AMDGPU::AMDGPUSchedReason)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:142: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown AMDGPUSchedReason");
[2/123] Building CXX object lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o
FAILED: lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o
/usr/bin/c++ -DLLVM_EXPORTS -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GLIBCXX_USE_CXX11_ABI=1 -D_GNU_SOURCE -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_EXTENSIVE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/path/to/build.AArch64.Release.main/lib/Target/AMDGPU -I/path/to/llvm-project/llvm/lib/Target/AMDGPU -I/path/to/build.AArch64.Release.main/include -I/path/to/llvm-project/llvm/include -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror=date-time -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wno-uninitialized -Wno-nonnull -Wno-class-memaccess -Wno-array-bounds -Wno-noexcept-type -Wdelete-non-virtual-dtor -Wno-comment -Wno-misleading-indentation -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -std=c++17 -fvisibility=hidden -UNDEBUG -fno-exceptions -funwind-tables -fno-rtti -MD -MT lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o -MF lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o.d -o lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o -c /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
In file included from /path/to/llvm-project/llvm/include/llvm/ADT/Hashing.h:49,
from /path/to/llvm-project/llvm/include/llvm/ADT/ArrayRef.h:12,
from /path/to/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNSubtarget.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp:17:
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getFlavorName(llvm::AMDGPU::InstructionFlavor)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:67: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown InstructionFlavor");
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getFlavorShortName(llvm::AMDGPU::InstructionFlavor)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:95: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown InstructionFlavor");
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getReasonName(llvm::AMDGPU::AMDGPUSchedReason)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:142: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown AMDGPUSchedReason");
ninja: build stopped: subcommand failed.
```
See alo
(https://github.com/llvm/llvm-project/pull/192322#issuecomment-4672427400)
Commit: 3abb8d8a05a215f719cd5ebc962e5f07ffbaeaa1
https://github.com/llvm/llvm-project/commit/3abb8d8a05a215f719cd5ebc962e5f07ffbaeaa1
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
M mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
M mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp
A mlir/test/Conversion/XeGPUToXeVM/extf_truncf.mlir
M mlir/test/Conversion/XeVMToLLVM/xevm_mx-to-llvm.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/xevm.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_raw.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_bf16.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_fp4.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_fp4_bf16.mlir
Log Message:
-----------
[MLIR][XeVM] Add xevm.extf op as the inverse of xevm.truncf (#203124)
Add a new xevm.extf operation that extends f8/bf8/f4 values to f16/bf16,
mirroring the existing xevm.truncf op, together with its lowering in
XeVMToLLVM.
Lowering details (XeVMToLLVM):
- bf8/f8 -> f16 via __builtin_IB_bf8tohf_16 / __builtin_IB_hf8tohf_16.
- bf8/f8 -> bf16 via f16 -> f32 (convert_float16) -> bf16
(__builtin_IB_ftobf_16).
- e2m1 (fp4) -> f16/bf16 via __builtin_IB_shfl_idx4_lut and
__builtin_IB_shfl_idx4_to_fp16_8_packed (LUT 7 for f16, 5 for bf16).
Adds the op definition and verifier, conversion/roundtrip/invalid unit
tests, and f8 and fp4 GPU round-trip integration tests.
Adds arith.extf to xevm.extf lowering and arith.truncf to xevm.truncf
lowering in XeGPU to XeVM conversion and unit tests.
Commit: c4c30cebec281eb52e9742cfb1f892fa3c1d9624
https://github.com/llvm/llvm-project/commit/c4c30cebec281eb52e9742cfb1f892fa3c1d9624
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
M llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll
Log Message:
-----------
[SLP] Vectorize full insertvalue buildvector sequences
Treat a complete chain of insertvalue instructions building a homogeneous
literal struct from scalars as a buildvector, like insertelement sequences.
The scalars are vectorized into one vector; the aggregate is rebuilt from it
via a stack store + load, or stored directly when its only user is a store.
insertvalue is routed through the existing insertelement buildvector paths
(type/index helpers, reordering, tree build, cost model, min-bitwidth, and
codegen). Only single-index, non-vector inserts building from an undef
aggregate are handled.
Fixes #43353
Reviewers: hiraditya, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/200274
Commit: ae026a59dad1a0a59209418f7a39e16a889c8ac1
https://github.com/llvm/llvm-project/commit/ae026a59dad1a0a59209418f7a39e16a889c8ac1
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
Log Message:
-----------
[AMDGPU] Enable S_ADD_PC_I64 on gfx1251 (#203613)
Commit: 2f8a39d73394b9a50a32fed5430896afa32a06f5
https://github.com/llvm/llvm-project/commit/2f8a39d73394b9a50a32fed5430896afa32a06f5
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/test/Transforms/LoopInterchange/lcssa-incoming-value-is-not-instr.ll
Log Message:
-----------
[LoopInterchange] Fix crash when followLCSSA returns constant (#203515)
Similar as the case in ##201069, `followLCSSA` may return a constant
value, but it was cast to Instruction unconditionally. We need to
explicitly check whether the returned value is an Instruction or not.
Fix #203375.
Commit: d0cd530bf4e28732368244476c4f504a4920e6c4
https://github.com/llvm/llvm-project/commit/d0cd530bf4e28732368244476c4f504a4920e6c4
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
Log Message:
-----------
[LoopInterchange] Mark getAddRecCoefficient with static (#203624)
As this function is a file-scope non-member function, it's better to
mark it with static.
Commit: e882286f4bb9095558e9783aa79cc6ca90487bcf
https://github.com/llvm/llvm-project/commit/e882286f4bb9095558e9783aa79cc6ca90487bcf
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M bolt/lib/Profile/DataAggregator.cpp
Log Message:
-----------
[BOLT] Fix perf data return identification (#203628)
If perf data doesn't have branch type recorded, missing value would
incorrectly be interpreted as not-a-return. Only populate Returns map if
the branch type is available.
Fixes bug introduced in #202813.
Commit: 8fb9963fd4da8bc5b3b7e186cd369102f42d3640
https://github.com/llvm/llvm-project/commit/8fb9963fd4da8bc5b3b7e186cd369102f42d3640
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
A llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
A llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1251_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
Log Message:
-----------
[AMDGPU] Add gfx1251 V_PK_LSHL_ADD_U64 (#203612)
Commit: 181d8084770935e4e3cd1877d317e95b73fe8368
https://github.com/llvm/llvm-project/commit/181d8084770935e4e3cd1877d317e95b73fe8368
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/test/CodeGen/AArch64/arm64e-tail-call-autib.ll
M llvm/test/CodeGen/AArch64/pauth-lr-tail-call-fpdiff.ll
A llvm/test/CodeGen/AArch64/swifttail-ptrauth.ll
Log Message:
-----------
[AArch64][PAuth] Fix return-address auth for swifttailcc with FPDiff > 0 (#203340)
When a swifttailcc tail call has FPDiff > 0 (the caller received more
stack argument space than the callee pops), the epilogue contains an SP
adjustment to discard the leftover argument space. The existing code
treated both FPDiff < 0 and FPDiff > 0 uniformly in a single 'FPDiff !=
0' block, using AUTI[AB]1716 with a reconstructed entry-SP in x16 for
both cases.
For FPDiff < 0 (callee pops more) that reconstruction is necessary and
correct. For FPDiff > 0 it is wrong: by the time we enter the block the
post-index LDP has already adjusted SP back to the frame base, but the
'add sp, sp, #N' argument pop has not yet run. Entry SP equals the
current SP at that point, so AUTI[AB]SP would work directly, but instead
the combined block bumped SP via StackOffset::getFixed(-FPDiff) which
overshoots, and then emits AUTIA1716 with a wrong discriminator. Worse
yet, the SP restore had already been emitted *before* the auth, leaving
the live argument stack below SP and outside the red-zone during the
authentication window.
Fix by splitting the block on the sign of ArgumentStackToRestore:
* `< 0`: reconstruct entry SP in x16, save LR in x17, authenticate with
AUTI[AB]1716 (or AUTI[AB]171615 / PACM+AUTI[AB]1716 for PAuthLR).
* `> 0`: temporarily remove the 'add sp, sp, #N' SP-modifying
instructions from before the auth instruction (SPMods shuffle),
authenticate with AUTI[AB]SP (SP == entry SP at this point), then
re-insert the SP adjustment afterward.
Commit: 4c057feb7835680c39c78e826c033307bec74295
https://github.com/llvm/llvm-project/commit/4c057feb7835680c39c78e826c033307bec74295
Author: Guo Chen <guochen2 at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
A llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll
Log Message:
-----------
[AMDGPU][true16] extract 16bit for scratch_load_ubyte_st when spilling (#203589)
In sramecc mode scratch_load_ubyte_st is selected for 16bit spilling.
Need a tmp vgpr32 and extract lo16 from it
Commit: 0a6e0210df5596f4aa35b6d01d0dcedc9414dab9
https://github.com/llvm/llvm-project/commit/0a6e0210df5596f4aa35b6d01d0dcedc9414dab9
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_poison_freeze/freeze-aggregate.ll
A llvm/test/CodeGen/SPIRV/freeze-aggregate.ll
Log Message:
-----------
[SPIR-V] Lower freeze instructions with aggregate operands (#203584)
An aggregate freeze takes its result type from its operand, like a PHI
or select, but was handled by neither the up-front value-id mutation nor
replaceMemInstrUses, so the pass aborted with "illegal aggregate
intrinsic user". Mutate aggregate freezes to the i32 value-id type and
replace their operands alongside PHIs and selects.
Commit: d2163f7c0c21390190e1ccb91e61958ad6ecc9f9
https://github.com/llvm/llvm-project/commit/d2163f7c0c21390190e1ccb91e61958ad6ecc9f9
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Semantics/check-cuda.cpp
M flang/test/Semantics/cuf09.cuf
Log Message:
-----------
[flang][cuda] Error out if pause statement is used in device code (#203642)
Commit: 81a81d7fae4a16e0edfdb0273f5c376547e15841
https://github.com/llvm/llvm-project/commit/81a81d7fae4a16e0edfdb0273f5c376547e15841
Author: dpalermo <dan.palermo at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
Log Message:
-----------
Revert "[AMDGPU] In `LowerDYNAMIC_STACKALLOC`, hoist the `readfirstlane` up one instruction" (#203645)
Reverts llvm/llvm-project#201528
Reverting due to change causing "illegal VGPR to SGPR copy"
Commit: c9b25a6437fd97fdb1e55ab6661c0cccce98913e
https://github.com/llvm/llvm-project/commit/c9b25a6437fd97fdb1e55ab6661c0cccce98913e
Author: Hardik Chona <iamhardikchona at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/stdlib.yaml
M libc/src/stdlib/CMakeLists.txt
A libc/src/stdlib/mkstemp.cpp
A libc/src/stdlib/mkstemp.h
M libc/test/src/stdlib/CMakeLists.txt
A libc/test/src/stdlib/mkstemp_test.cpp
Log Message:
-----------
[libc] implement mkstemp (#199220)
Fixes #191266
Implements `mkstemp` as specified in POSIX
Currently Linux-only since it relies on the Linux syscall wrappers for
`getrandom` and `open`
Commit: 92d7a7fbbd7238222d8a0ef7b85b9300f832a4d5
https://github.com/llvm/llvm-project/commit/92d7a7fbbd7238222d8a0ef7b85b9300f832a4d5
Author: vsimion26 <vlad.simion at intel.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/Quant/IR/Quant.h
M mlir/include/mlir/Dialect/Quant/IR/QuantBase.td
M mlir/include/mlir/Dialect/Quant/IR/QuantDialectBytecode.td
M mlir/lib/Dialect/Quant/IR/QuantDialectBytecode.cpp
M mlir/test/Dialect/Quant/Bytecode/types.mlir
Log Message:
-----------
QuantileType bytecode patch (#203495)
Since the merge of this
PR(https://github.com/llvm/llvm-project/pull/190321) there were some
issues identified, such as QuantileType not being added in the ByteCode
files. This PR focuses on fixing these missing pieces which should make
QuantileType a complete and functional type.
Commit: a8e3c083db160e2dc6f04b660b22b459e5167199
https://github.com/llvm/llvm-project/commit/a8e3c083db160e2dc6f04b660b22b459e5167199
Author: Schrodinger ZHU Yifan <yfzhu at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M libc/src/__support/threads/linux/futex_utils.h
M libc/src/__support/threads/raw_mutex.h
M libc/src/__support/threads/raw_rwlock.h
M libc/test/integration/src/__support/threads/futex_requeue_test.cpp
Log Message:
-----------
[libc] fix EAGAIN being treated as timeout in mutex and rwlock (#203574)
fix #203411.
This PR addresses the problem that `EAGAIN` may be treated as timeout in
mutex and rwlock. Two changes are applied:
1. timeout sites always explicitly check for timeout now to make the
logic more robust;
2. the futex wait now discards the error of `EAGAIN/EWOULDBLOCK` and
returns 0;
We don't distinguish waking up from signal and waking up from mismatch
for the following 3 reasons:
- We have userspace guard to avoid futex syscall if we already know
value would match, it seems awkward to make that check returns error, as
we may wake up and loop back to the check, where signal is consumed but
we still return error....;
- futex syscall can spuriously wake up anyway, there is no way to tell
whether the signal is "indeed" consumed;
- other platforms like darwin does not distinguish these states either.
Assisted-by: Gemini powered automation tools (human-in-the-loop).
Commit: baf76a838f3da5fcbb5acbdc12f57b0ed79cc3ce
https://github.com/llvm/llvm-project/commit/baf76a838f3da5fcbb5acbdc12f57b0ed79cc3ce
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/perf2bolt/perf_test.test
Log Message:
-----------
[BOLT] Change DataAggregator error types (#203651)
1. In `filterBinaryMMapInfo`, replace `incovertibleErrorCode` with errc
code as `parseMainEvents` converts returned Error to std::error_code.
2. In `parsePerfData`, pass through Error returned by `prepareToParse`
for memory events.
Test Plan: updated perf_test.test
Commit: 6b82a0485dbd6a6a5006329f2fa5f4e8bc977488
https://github.com/llvm/llvm-project/commit/6b82a0485dbd6a6a5006329f2fa5f4e8bc977488
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/test/Fir/CUDA/cuda-global-addr.mlir
Log Message:
-----------
[flang][cuda] Fix host loads from CUDA constant globals (#203064)
This fixes CUDA Fortran lowering for scalar module variables with the
constant attribute that are read from host code, such as launch
configuration expressions or CUF kernel loop bounds.
Previously, host-side declarations for these globals could be rewritten
to device constant-memory addresses, causing host loads to dereference
the result of _FortranACUFGetDeviceAddress. The fix preserves host reads
from the host-visible global while still using the device address for
host-to-device assignment updates.
A FIR regression test covers host reads and assignment updates for
scalar CUDA constant globals.
Commit: af60d56719aa770dda70d19f37b0451b222e89e4
https://github.com/llvm/llvm-project/commit/af60d56719aa770dda70d19f37b0451b222e89e4
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Semantics/expression.cpp
A flang/test/Semantics/cuf-generic-literal-host.cuf
A flang/test/Semantics/cuf28.cuf
Log Message:
-----------
[flang][CUDA] Keep host literals from using unified-memory generic distance (#201257)
Fix CUDA generic resolution under `-gpu=mem:unified` so unattributed
literals and expression temporaries are not treated as unified-memory
actuals.
Previously, a host scalar literal such as `1.0` could score as
compatible with a `DEVICE` dummy and incorrectly select the
device-scalar overload. This could pass a host stack address to a device
helper and fail at runtime. The fix applies the unified/managed memory
distance columns only to symbol-backed actuals.
Commit: 7670d88e7ea753095f753e6616b66f5e74da42ef
https://github.com/llvm/llvm-project/commit/7670d88e7ea753095f753e6616b66f5e74da42ef
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp
M flang/test/Fir/CUDA/cuda-device-func-transform.mlir
Log Message:
-----------
[flang][cuda] Set kernel intent(in) as const __restrict__ (#203652)
Set attributes on `intent(in)` so `ld.global.nc` is generated by the
backend.
Commit: 0579490edf0599cc01e10885c2149d4cce8ec399
https://github.com/llvm/llvm-project/commit/0579490edf0599cc01e10885c2149d4cce8ec399
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/IR/Intrinsics.cpp
A llvm/test/TableGen/intrinsic-overload-index-oor.td
M llvm/test/TableGen/intrinsic-struct.td
M llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
Log Message:
-----------
[NFC][LLVM] Refactor IIT_ANY payload for vector/element constraint (#203506)
Change `IIT_ANY` payload from a single packed OverloadIndex + AnyKind
byte to 2 bytes:
- An 8 bit OverloadIndex
- An 8 pit packed vector + element type constraint.
This will enable `IIT_ANY` to express constraints on the overload type
is a more general fashion compared to a flat `AnyKind` enum.
Also fixed a latent bug in fixed encodings generated by the intrinsic
emitter (exposed by this change). Existing `encodePacked` packs the
type-signature as 8 nibbles into a 32-bit word and then checks if the
MSB bit position (i.e., bit 15) is 0 (to allow it's use in fixed
encoding). This effectively drop any 0 valued bytes in the encoding in
the upper 4 nibbles. Fix this by changing `encodePacked` to use the
actual fixed encoding type and its size.
Commit: b8e34c5adc38b5406d175e7e94c95f6399da096a
https://github.com/llvm/llvm-project/commit/b8e34c5adc38b5406d175e7e94c95f6399da096a
Author: Utkarsh Saxena <usx at google.com>
Date: 2026-06-13 (Sat, 13 Jun 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/test/Sema/LifetimeSafety/annotation-suggestions.cpp
M clang/test/Sema/LifetimeSafety/invalidations.cpp
M clang/test/Sema/LifetimeSafety/nocfg.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
Log Message:
-----------
[LifetimeSafety] Improve diagnostic messages for invalidations (#203577)
Commit: 3956031018beda0ccb9f295de4ba162e80c3f8a2
https://github.com/llvm/llvm-project/commit/3956031018beda0ccb9f295de4ba162e80c3f8a2
Author: Alex Richardson <alexrichardson at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M .git-blame-ignore-revs
M .github/new-prs-labeler.yml
M .github/workflows/ids-check.yml
M bolt/docs/profiles.md
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/include/bolt/Profile/DataReader.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/lib/Profile/Heatmap.cpp
M bolt/test/X86/heatmap-preagg.test
M bolt/test/X86/pre-aggregated-perf.test
M bolt/test/X86/pre-aggregated-records.s
M bolt/test/perf2bolt/perf_brstack.test
M bolt/test/perf2bolt/perf_test.test
M bolt/unittests/Profile/DataAggregator.cpp
M clang/docs/ClangSYCLLinker.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Origins.h
R clang/include/clang/Basic/AtomicLineLogger.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/BuiltinsRISCV.td
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Frontend/FrontendOptions.h
M clang/include/clang/Options/Options.td
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpHelpers.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp
M clang/lib/Analysis/LifetimeSafety/Origins.cpp
R clang/lib/Basic/AtomicLineLogger.cpp
M clang/lib/Basic/CMakeLists.txt
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/LoweringHelpers.cpp
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/lib/CodeGen/Targets/SystemZ.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.h
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowExtractor.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.h
M clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
M clang/lib/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendAction.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/StaticAnalyzer/Checkers/PthreadLockChecker.cpp
M clang/test/AST/ByteCode/cxx20.cpp
A clang/test/AST/tyloctype_alignment.cpp
M clang/test/Analysis/Scalable/PointerFlow/external-inline-function-in-multi-tu.test
M clang/test/Analysis/Scalable/call-graph.cpp
A clang/test/Analysis/Scalable/cli-errors-compilation-unit-id.cpp
M clang/test/Analysis/Scalable/command-line-interface.cpp
M clang/test/Analysis/Scalable/downgradable-errors.cpp
M clang/test/Analysis/Scalable/extraction-works-alongside-compilation.cpp
M clang/test/Analysis/Scalable/help.cpp
A clang/test/Analysis/pthreadlock-notes.c
M clang/test/CIR/CodeGen/bind-temporary-lvalue.cpp
A clang/test/CIR/CodeGen/cxx-construct-lvalue.cpp
A clang/test/CIR/CodeGen/string-literal-high-bytes.c
M clang/test/CIR/CodeGen/ternary-throw.cpp
A clang/test/CIR/Transforms/abi-lowering/indirect-return-sret.cir
M clang/test/CodeGen/AArch64/neon-intrinsics.c
A clang/test/CodeGen/AArch64/neon/add.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
R clang/test/CodeGen/AArch64/poly-add.c
A clang/test/CodeGen/AArch64/sme2p3-intrinsics/acle_sme2p3_luti6.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6_lane_x2.c
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M clang/test/CodeGen/X86/avx512f-builtins-constrained-cmp.c
M clang/test/CodeGenHIP/offload-pgo-sections.hip
M clang/test/CodeGenHLSL/ArrayAssignable.hlsl
M clang/test/CodeGenHLSL/ArrayAssignable.logicalptr.hlsl
M clang/test/CodeGenHLSL/cbuffer-matrix-layout-keyword.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer-empty-struct-array.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_and_namespaces.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_with_packoffset.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_with_static_global_and_function.hlsl
M clang/test/CodeGenHLSL/resources/default_cbuffer.hlsl
M clang/test/CodeGenHLSL/resources/default_cbuffer_with_layout.hlsl
M clang/test/Driver/hip-profile-rocm-runtime.hip
M clang/test/Driver/hip-toolchain-no-rdc.hip
A clang/test/Driver/offload-darwin-host.hip
A clang/test/Driver/openmp-Xopenmp-target-forward-args.c
M clang/test/Format/lit.local.cfg
A clang/test/OffloadTools/clang-sycl-linker/archive-extras.ll
M clang/test/OffloadTools/clang-sycl-linker/basic.ll
M clang/test/OffloadTools/clang-sycl-linker/link.ll
M clang/test/OffloadTools/clang-sycl-linker/split-mode.ll
M clang/test/OffloadTools/clang-sycl-linker/triple.ll
A clang/test/OffloadTools/clang-sycl-linker/weak-symbols.ll
A clang/test/ParserHLSL/hlsl_is_array_attr.hlsl
A clang/test/ParserHLSL/hlsl_is_array_attr_error.hlsl
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2p3.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2p3___sme_AND_LP_sve2p3_OR_sme2p3_RP.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve2p3.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme2p3.c
R clang/test/Sema/Inputs/lifetime-analysis.h
A clang/test/Sema/LifetimeSafety/Inputs/lifetime-analysis.h
A clang/test/Sema/LifetimeSafety/annotation-suggestions-fixits.cpp
A clang/test/Sema/LifetimeSafety/annotation-suggestions.cpp
A clang/test/Sema/LifetimeSafety/attr-lifetimebound-no-crash.cpp
A clang/test/Sema/LifetimeSafety/attr-lifetimebound.c
A clang/test/Sema/LifetimeSafety/capture-by.cpp
A clang/test/Sema/LifetimeSafety/cfg-bailout.cpp
A clang/test/Sema/LifetimeSafety/dangling-field.cpp
A clang/test/Sema/LifetimeSafety/dangling-global.cpp
A clang/test/Sema/LifetimeSafety/inapplicable-lifetimebound.cpp
A clang/test/Sema/LifetimeSafety/invalidations.cpp
A clang/test/Sema/LifetimeSafety/lifetime-facts.cpp
A clang/test/Sema/LifetimeSafety/lifetimebound-violation.cpp
A clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-cross-tu.cpp
A clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-intra-tu.cpp
A clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-macro.cpp
A clang/test/Sema/LifetimeSafety/missing-origin-stats.cpp
A clang/test/Sema/LifetimeSafety/nocfg-disabled.cpp
A clang/test/Sema/LifetimeSafety/nocfg.cpp
A clang/test/Sema/LifetimeSafety/noescape-violation.cpp
A clang/test/Sema/LifetimeSafety/safety.cpp
A clang/test/Sema/aarch64-sme2p3-intrinsics/acle_sme2p3_imm.c
M clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_imm.cpp
A clang/test/Sema/atomic-conversions-to-int.cpp
R clang/test/Sema/attr-lifetimebound-no-crash.cpp
R clang/test/Sema/attr-lifetimebound.c
R clang/test/Sema/warn-lifetime-analysis-capture-by.cpp
R clang/test/Sema/warn-lifetime-analysis-nocfg-disabled.cpp
R clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
R clang/test/Sema/warn-lifetime-safety-cfg-bailout.cpp
R clang/test/Sema/warn-lifetime-safety-dangling-field.cpp
R clang/test/Sema/warn-lifetime-safety-dangling-global.cpp
R clang/test/Sema/warn-lifetime-safety-dataflow.cpp
R clang/test/Sema/warn-lifetime-safety-fixits.cpp
R clang/test/Sema/warn-lifetime-safety-invalidations.cpp
R clang/test/Sema/warn-lifetime-safety-lifetimebound.cpp
R clang/test/Sema/warn-lifetime-safety-misplaced-lifetimebound-cross-tu.cpp
R clang/test/Sema/warn-lifetime-safety-misplaced-lifetimebound-intra-tu.cpp
R clang/test/Sema/warn-lifetime-safety-misplaced-lifetimebound-macro.cpp
R clang/test/Sema/warn-lifetime-safety-missing-origin-stats.cpp
R clang/test/Sema/warn-lifetime-safety-noescape.cpp
R clang/test/Sema/warn-lifetime-safety-suggestions.cpp
R clang/test/Sema/warn-lifetime-safety.cpp
M clang/tools/clang-sycl-linker/CMakeLists.txt
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
M clang/tools/clang-sycl-linker/SYCLLinkOpts.td
R clang/unittests/Basic/AtomicLineLoggerTest.cpp
M clang/unittests/Basic/CMakeLists.txt
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendActionTest.cpp
M compiler-rt/lib/builtins/cpu_model/riscv/hwprobe.inc
M compiler-rt/lib/profile/InstrProfilingFile.c
M compiler-rt/lib/profile/InstrProfilingPlatformROCm.cpp
M compiler-rt/test/fuzzer/features_dir.test
M compiler-rt/test/fuzzer/fork-sigusr.test
M compiler-rt/test/fuzzer/lit.cfg.py
M compiler-rt/test/fuzzer/merge-posix.test
M compiler-rt/test/fuzzer/merge-sigusr.test
M compiler-rt/test/fuzzer/sigint.test
M compiler-rt/test/fuzzer/sigusr.test
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M flang-rt/lib/runtime/__fortran_builtins.f90
M flang/CMakeLists.txt
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/lib/Parser/Fortran-parsers.cpp
M flang/lib/Semantics/check-cuda.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/expression.cpp
M flang/test/Fir/CUDA/cuda-device-func-transform.mlir
M flang/test/Fir/CUDA/cuda-global-addr.mlir
M flang/test/Fir/mem2reg.mlir
A flang/test/Lower/OpenACC/Todo/acc-unstructured-combined-construct.f90
A flang/test/Lower/OpenACC/Todo/acc-unstructured-loop-construct.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
M flang/test/Lower/OpenMP/Todo/error.f90
A flang/test/Lower/OpenMP/nothing.f90
A flang/test/Parser/recovery09.f90
M flang/test/Semantics/OpenMP/linear-clause01.f90
A flang/test/Semantics/cuf-generic-literal-host.cuf
M flang/test/Semantics/cuf09.cuf
A flang/test/Semantics/cuf28.cuf
M libc/config/baremetal/config.json
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
M libc/include/llvm-libc-types/struct_tm.h
A libc/include/llvm-libc-types/tm_gmtoff_t.h
M libc/include/stdlib.yaml
M libc/include/time.yaml
M libc/src/__support/str_to_integer.h
M libc/src/__support/threads/linux/futex_utils.h
M libc/src/__support/threads/raw_mutex.h
M libc/src/__support/threads/raw_rwlock.h
M libc/src/stdlib/CMakeLists.txt
A libc/src/stdlib/mkstemp.cpp
A libc/src/stdlib/mkstemp.h
M libc/src/time/CMakeLists.txt
M libc/src/time/asctime.cpp
M libc/src/time/asctime_r.cpp
M libc/src/time/ctime.cpp
M libc/src/time/ctime_r.cpp
M libc/src/time/gmtime.cpp
M libc/src/time/gmtime_r.cpp
M libc/src/time/localtime.cpp
M libc/src/time/localtime_r.cpp
M libc/src/time/mktime.cpp
M libc/src/time/strftime.cpp
M libc/src/time/strftime_core/CMakeLists.txt
M libc/src/time/strftime_core/composite_converter.h
M libc/src/time/strftime_core/converter.h
M libc/src/time/strftime_core/num_converter.h
M libc/src/time/strftime_core/str_converter.h
M libc/src/time/strftime_l.cpp
M libc/src/time/time_utils.cpp
M libc/src/time/time_utils.h
M libc/test/integration/src/__support/threads/futex_requeue_test.cpp
M libc/test/src/__support/str_to_integer_test.cpp
M libc/test/src/math/RoundToIntegerTest.h
M libc/test/src/stdlib/CMakeLists.txt
M libc/test/src/stdlib/StrtolTest.h
A libc/test/src/stdlib/mkstemp_test.cpp
M libc/test/src/time/asctime_r_test.cpp
M libc/test/src/time/asctime_test.cpp
M libc/test/src/time/ctime_r_test.cpp
M libc/test/src/time/ctime_test.cpp
M libc/test/src/time/gmtime_r_test.cpp
M libc/test/src/time/gmtime_test.cpp
M libc/test/src/time/localtime_r_test.cpp
M libc/test/src/time/localtime_test.cpp
M libc/test/src/time/mktime_test.cpp
M libc/test/src/time/strftime_test.cpp
M libc/test/src/wchar/WcstolTest.h
M libcxx/include/optional
M libcxx/test/std/utilities/optional/optional.syn/optional_in_place_t.verify.cpp
M libcxx/test/std/utilities/optional/optional.syn/optional_nullopt_t.verify.cpp
M lld/MachO/BPSectionOrderer.cpp
M lld/MachO/Driver.cpp
M lld/MachO/ICF.cpp
M lld/MachO/InputFiles.cpp
M lld/MachO/InputSection.h
M lld/MachO/SectionPriorities.cpp
M lld/MachO/SymbolTable.cpp
M lld/MachO/SymbolTable.h
M lld/MachO/Symbols.cpp
M lld/MachO/Symbols.h
M lld/MachO/SyntheticSections.cpp
M lld/MachO/Writer.cpp
A lld/test/MachO/bp-section-orderer-cold.s
A lld/test/MachO/cold-func-weak-merge.s
A lld/test/MachO/cold-func.s
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
M lldb/source/Plugins/Process/Windows/Common/CMakeLists.txt
A lldb/source/Plugins/Process/Windows/Common/ExceptionRecord.cpp
M lldb/source/Plugins/Process/Windows/Common/ExceptionRecord.h
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.h
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.h
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/invalid-vector/TestDataFormatterLibcxxInvalidVectorSimulator.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/invalid-vector/main.cpp
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/vector/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/vector/TestDataFormatterLibcxxVectorSimulator.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/vector/main.cpp
M lldb/test/API/macosx/simulator/TestSimulatorPlatform.py
M llvm/docs/CommandGuide/lit.rst
M llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl07.rst
M llvm/examples/Kaleidoscope/Chapter7/toy.cpp
M llvm/include/llvm/ADT/Bitset.h
M llvm/include/llvm/ADT/StringExtras.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/IR/BundleAttributes.h
M llvm/include/llvm/IR/Intrinsics.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/include/llvm/IR/Value.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MIRPrintingPass.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/VirtRegMap.cpp
M llvm/lib/DTLTO/DTLTO.cpp
M llvm/lib/Frontend/HLSL/CBuffer.cpp
M llvm/lib/IR/BundleAttributes.cpp
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCParser/COFFMasmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MC/MCWin64EH.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Support/KnownFPClass.cpp
M llvm/lib/Support/Win64EH.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.h
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/DirectX/DXILCBufferAccess.cpp
M llvm/lib/Target/DirectX/DirectXIRPasses/DXILDebugInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/SPIRV/SPIRVCBufferAccess.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Scalar/MergeICmps.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-fadd.ll
M llvm/test/Analysis/ScalarEvolution/shift-op.ll
A llvm/test/Analysis/ValueTracking/known-non-zero-shr-add.ll
A llvm/test/Bitcode/byte-constants.ll
M llvm/test/CodeGen/AArch64/arm64e-tail-call-autib.ll
M llvm/test/CodeGen/AArch64/ext-narrow-index.ll
M llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
M llvm/test/CodeGen/AArch64/pauth-lr-tail-call-fpdiff.ll
A llvm/test/CodeGen/AArch64/shuffle-slide-to-shift.ll
M llvm/test/CodeGen/AArch64/sme-intrinsics-mova-insert.ll
A llvm/test/CodeGen/AArch64/sme2p3-intrinsics-luti6.ll
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics-luti6.ll
A llvm/test/CodeGen/AArch64/swifttail-ptrauth.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.subdword.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-max-pregfx12.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
A llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.fmt-error.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
A llvm/test/CodeGen/AMDGPU/packed-fp64.ll
A llvm/test/CodeGen/AMDGPU/packed-u64.ll
A llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
R llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
A llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
A llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll
M llvm/test/CodeGen/AMDGPU/wmma-coexecution-valu-hazards.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
A llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1251-w32.mir
A llvm/test/CodeGen/DirectX/DebugInfo/dbg-assign.ll
A llvm/test/CodeGen/DirectX/DebugInfo/dbg-value-arglist.ll
A llvm/test/CodeGen/DirectX/DebugInfo/di-commonblock.ll
A llvm/test/CodeGen/DirectX/cbuffer_global_elim.ll
A llvm/test/CodeGen/DirectX/switch-to-lookup-table-i16-narrowing.ll
A llvm/test/CodeGen/DirectX/switch-to-lookup-table-no-i8-narrowing.ll
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-phys.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-split.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-self-split.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash.mir
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
M llvm/test/CodeGen/SPIRV/FCmpFalse_Vec.ll
A llvm/test/CodeGen/SPIRV/cbuffer_global_elim.ll
A llvm/test/CodeGen/SPIRV/constant/local-zero-constants.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-vector-skipped.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-vector.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_poison_freeze/freeze-aggregate.ll
A llvm/test/CodeGen/SPIRV/freeze-aggregate.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/is_fpclass.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/signed_arithmetic_overflow.ll
M llvm/test/CodeGen/X86/stack-coloring-setjmp.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_err.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_wmma_w32.s
M llvm/test/MC/AMDGPU/gfx1250_asm_wmma_w32_err.s
A llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1251_err.s
M llvm/test/MC/COFF/seh-unwindv3-error.s
M llvm/test/MC/COFF/seh-unwindv3-inheritance.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_wmma_w32.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
A llvm/test/TableGen/intrinsic-overload-index-oor.td
M llvm/test/TableGen/intrinsic-struct.td
M llvm/test/ThinLTO/X86/dtlto/timetrace.ll
M llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll
M llvm/test/Transforms/ConstraintElimination/geps-unsigned-predicates.ll
M llvm/test/Transforms/InstCombine/assume.ll
M llvm/test/Transforms/InstCombine/modular-format.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-canonicalize.ll
M llvm/test/Transforms/InstSimplify/fold-intrinsics.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll
R llvm/test/Transforms/LICM/vector-insert.ll
M llvm/test/Transforms/LoopInterchange/lcssa-incoming-value-is-not-instr.ll
A llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions-min-max.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
M llvm/test/Transforms/LoopVectorize/RISCV/gather-scatter-cost.ll
A llvm/test/Transforms/LoopVectorize/RISCV/i128-trip-count-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
A llvm/test/Transforms/LoopVectorize/RISCV/stepvector-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-gather-scatter.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/cast-costs.ll
M llvm/test/Transforms/LoopVectorize/epilog-iv-select-cmp.ll
A llvm/test/Transforms/LoopVectorize/induction-cost.ll
M llvm/test/Transforms/LoopVectorize/vscale-cost.ll
M llvm/test/Transforms/MergeICmps/X86/no-gep-other-work.ll
M llvm/test/Transforms/MergeICmps/X86/opaque-ptr.ll
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
M llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll
M llvm/test/Verifier/modular-format.ll
A llvm/test/tools/dxil-dis/dbg-assign.ll
A llvm/test/tools/dxil-dis/dbg-value-arglist.ll
A llvm/test/tools/dxil-dis/di-commonblock.ll
A llvm/test/tools/llvm-diff/callsite-assumption-passing.ll
A llvm/test/tools/llvm-ml/beginepilog_error.asm
M llvm/test/tools/llvm-ml/builtin_symbols.asm
A llvm/test/tools/llvm-ml/epilog_directive_errors.asm
A llvm/test/tools/llvm-ml/epilog_directives.asm
A llvm/test/tools/llvm-ml/proc_frame_v3.asm
A llvm/test/tools/llvm-ml/prolog_directive_errors.asm
A llvm/test/tools/llvm-ml/unwindv3_required_errors.asm
M llvm/test/tools/llvm-objdump/COFF/win64-unwindv3-multi-epilog.yaml
M llvm/test/tools/llvm-readobj/COFF/unwind-x86_64-v3-multi-epilog.yaml
M llvm/tools/llvm-diff/lib/DifferenceEngine.cpp
M llvm/tools/llvm-ml/Opts.td
M llvm/tools/llvm-ml/llvm-ml.cpp
M llvm/tools/llvm-objdump/COFFDump.cpp
M llvm/tools/llvm-readobj/Win64EHDumper.cpp
M llvm/unittests/ADT/BitsetTest.cpp
M llvm/unittests/Support/GlobPatternTest.cpp
M llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/readability/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/ObjectFile/Mach-O/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Windows/Common/BUILD.gn
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/MC/BUILD.gn
M llvm/utils/lit/lit/TestRunner.py
M llvm/utils/lit/tests/substitutions.py
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosa.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLAttrs.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLEnums.td
M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
M mlir/include/mlir/Dialect/Quant/IR/Quant.h
M mlir/include/mlir/Dialect/Quant/IR/QuantBase.td
M mlir/include/mlir/Dialect/Quant/IR/QuantDialectBytecode.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/Vector/Utils/VectorUtils.h
M mlir/include/mlir/Dialect/XeGPU/Transforms/Transforms.h
M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/lib/Conversion/TosaToSPIRVTosa/CMakeLists.txt
A mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaCustom.cpp
M mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaPass.cpp
M mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
M mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
M mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp
M mlir/lib/Dialect/Arith/IR/ArithDialect.cpp
M mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp
M mlir/lib/Dialect/Quant/IR/QuantDialectBytecode.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/LowerVectorContract.cpp
M mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Dialect/XeGPU/Utils/CMakeLists.txt
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
A mlir/test/Conversion/TosaToSPIRVTosa/custom-op-domain-to-opcode-invalid.mlir
A mlir/test/Conversion/TosaToSPIRVTosa/custom-op-domain-to-opcode.mlir
A mlir/test/Conversion/XeGPUToXeVM/extf_truncf.mlir
M mlir/test/Conversion/XeVMToLLVM/xevm_mx-to-llvm.mlir
M mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir
M mlir/test/Dialect/GPU/module-to-binary-rocdl.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/module-roundtrip.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Dialect/LLVMIR/xevm.mlir
M mlir/test/Dialect/Quant/Bytecode/types.mlir
M mlir/test/Dialect/SPIRV/IR/gl-ops.mlir
M mlir/test/Dialect/SPIRV/Transforms/canonicalize.mlir
M mlir/test/Dialect/Vector/vector-contract-to-parallel-arith-transforms.mlir
M mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute-unit.mlir
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
A mlir/test/IR/test-func-erase-arg-error.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_raw.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_bf16.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_fp4.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_fp4_bf16.mlir
M mlir/test/Target/LLVMIR/nvvm/barrier.mlir
M mlir/test/Target/LLVMIR/nvvm/tensormap_replace_invalid.mlir
A mlir/test/Target/LLVMIR/rocdl-module-flags.mlir
M mlir/test/Target/SPIRV/gl-ops.mlir
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
M mlir/test/lib/IR/TestFunc.cpp
M openmp/runtime/cmake/LibompExports.cmake
M orc-rt/include/orc-rt-c/ExternC.h
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.8-beta.1
[skip ci]
Commit: 81877c8b8caf330a647db82309c8b80597de7541
https://github.com/llvm/llvm-project/commit/81877c8b8caf330a647db82309c8b80597de7541
Author: Alex Richardson <alexrichardson at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M .git-blame-ignore-revs
M .github/new-prs-labeler.yml
M .github/workflows/ids-check.yml
M bolt/docs/profiles.md
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/include/bolt/Profile/DataReader.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/lib/Profile/Heatmap.cpp
M bolt/test/X86/heatmap-preagg.test
M bolt/test/X86/pre-aggregated-perf.test
M bolt/test/X86/pre-aggregated-records.s
M bolt/test/perf2bolt/perf_brstack.test
M bolt/test/perf2bolt/perf_test.test
M bolt/unittests/Profile/DataAggregator.cpp
M clang/docs/ClangSYCLLinker.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Origins.h
R clang/include/clang/Basic/AtomicLineLogger.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/BuiltinsRISCV.td
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Frontend/FrontendOptions.h
M clang/include/clang/Options/Options.td
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpHelpers.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp
M clang/lib/Analysis/LifetimeSafety/Origins.cpp
R clang/lib/Basic/AtomicLineLogger.cpp
M clang/lib/Basic/CMakeLists.txt
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/LoweringHelpers.cpp
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/lib/CodeGen/Targets/SystemZ.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.h
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowExtractor.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.h
M clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
M clang/lib/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendAction.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/StaticAnalyzer/Checkers/PthreadLockChecker.cpp
M clang/test/AST/ByteCode/cxx20.cpp
A clang/test/AST/tyloctype_alignment.cpp
M clang/test/Analysis/Scalable/PointerFlow/external-inline-function-in-multi-tu.test
M clang/test/Analysis/Scalable/call-graph.cpp
A clang/test/Analysis/Scalable/cli-errors-compilation-unit-id.cpp
M clang/test/Analysis/Scalable/command-line-interface.cpp
M clang/test/Analysis/Scalable/downgradable-errors.cpp
M clang/test/Analysis/Scalable/extraction-works-alongside-compilation.cpp
M clang/test/Analysis/Scalable/help.cpp
A clang/test/Analysis/pthreadlock-notes.c
M clang/test/CIR/CodeGen/bind-temporary-lvalue.cpp
A clang/test/CIR/CodeGen/cxx-construct-lvalue.cpp
A clang/test/CIR/CodeGen/string-literal-high-bytes.c
M clang/test/CIR/CodeGen/ternary-throw.cpp
A clang/test/CIR/Transforms/abi-lowering/indirect-return-sret.cir
M clang/test/CodeGen/AArch64/neon-intrinsics.c
A clang/test/CodeGen/AArch64/neon/add.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
R clang/test/CodeGen/AArch64/poly-add.c
A clang/test/CodeGen/AArch64/sme2p3-intrinsics/acle_sme2p3_luti6.c
M clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6_lane_x2.c
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M clang/test/CodeGen/X86/avx512f-builtins-constrained-cmp.c
M clang/test/CodeGenHIP/offload-pgo-sections.hip
M clang/test/CodeGenHLSL/ArrayAssignable.hlsl
M clang/test/CodeGenHLSL/ArrayAssignable.logicalptr.hlsl
M clang/test/CodeGenHLSL/cbuffer-matrix-layout-keyword.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer-empty-struct-array.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_and_namespaces.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_with_packoffset.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_with_static_global_and_function.hlsl
M clang/test/CodeGenHLSL/resources/default_cbuffer.hlsl
M clang/test/CodeGenHLSL/resources/default_cbuffer_with_layout.hlsl
M clang/test/Driver/hip-profile-rocm-runtime.hip
M clang/test/Driver/hip-toolchain-no-rdc.hip
A clang/test/Driver/offload-darwin-host.hip
A clang/test/Driver/openmp-Xopenmp-target-forward-args.c
M clang/test/Format/lit.local.cfg
A clang/test/OffloadTools/clang-sycl-linker/archive-extras.ll
M clang/test/OffloadTools/clang-sycl-linker/basic.ll
M clang/test/OffloadTools/clang-sycl-linker/link.ll
M clang/test/OffloadTools/clang-sycl-linker/split-mode.ll
M clang/test/OffloadTools/clang-sycl-linker/triple.ll
A clang/test/OffloadTools/clang-sycl-linker/weak-symbols.ll
A clang/test/ParserHLSL/hlsl_is_array_attr.hlsl
A clang/test/ParserHLSL/hlsl_is_array_attr_error.hlsl
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2p3.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2p3___sme_AND_LP_sve2p3_OR_sme2p3_RP.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve2p3.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme2p3.c
R clang/test/Sema/Inputs/lifetime-analysis.h
A clang/test/Sema/LifetimeSafety/Inputs/lifetime-analysis.h
A clang/test/Sema/LifetimeSafety/annotation-suggestions-fixits.cpp
A clang/test/Sema/LifetimeSafety/annotation-suggestions.cpp
A clang/test/Sema/LifetimeSafety/attr-lifetimebound-no-crash.cpp
A clang/test/Sema/LifetimeSafety/attr-lifetimebound.c
A clang/test/Sema/LifetimeSafety/capture-by.cpp
A clang/test/Sema/LifetimeSafety/cfg-bailout.cpp
A clang/test/Sema/LifetimeSafety/dangling-field.cpp
A clang/test/Sema/LifetimeSafety/dangling-global.cpp
A clang/test/Sema/LifetimeSafety/inapplicable-lifetimebound.cpp
A clang/test/Sema/LifetimeSafety/invalidations.cpp
A clang/test/Sema/LifetimeSafety/lifetime-facts.cpp
A clang/test/Sema/LifetimeSafety/lifetimebound-violation.cpp
A clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-cross-tu.cpp
A clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-intra-tu.cpp
A clang/test/Sema/LifetimeSafety/misplaced-lifetimebound-macro.cpp
A clang/test/Sema/LifetimeSafety/missing-origin-stats.cpp
A clang/test/Sema/LifetimeSafety/nocfg-disabled.cpp
A clang/test/Sema/LifetimeSafety/nocfg.cpp
A clang/test/Sema/LifetimeSafety/noescape-violation.cpp
A clang/test/Sema/LifetimeSafety/safety.cpp
A clang/test/Sema/aarch64-sme2p3-intrinsics/acle_sme2p3_imm.c
M clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_imm.cpp
A clang/test/Sema/atomic-conversions-to-int.cpp
R clang/test/Sema/attr-lifetimebound-no-crash.cpp
R clang/test/Sema/attr-lifetimebound.c
R clang/test/Sema/warn-lifetime-analysis-capture-by.cpp
R clang/test/Sema/warn-lifetime-analysis-nocfg-disabled.cpp
R clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
R clang/test/Sema/warn-lifetime-safety-cfg-bailout.cpp
R clang/test/Sema/warn-lifetime-safety-dangling-field.cpp
R clang/test/Sema/warn-lifetime-safety-dangling-global.cpp
R clang/test/Sema/warn-lifetime-safety-dataflow.cpp
R clang/test/Sema/warn-lifetime-safety-fixits.cpp
R clang/test/Sema/warn-lifetime-safety-invalidations.cpp
R clang/test/Sema/warn-lifetime-safety-lifetimebound.cpp
R clang/test/Sema/warn-lifetime-safety-misplaced-lifetimebound-cross-tu.cpp
R clang/test/Sema/warn-lifetime-safety-misplaced-lifetimebound-intra-tu.cpp
R clang/test/Sema/warn-lifetime-safety-misplaced-lifetimebound-macro.cpp
R clang/test/Sema/warn-lifetime-safety-missing-origin-stats.cpp
R clang/test/Sema/warn-lifetime-safety-noescape.cpp
R clang/test/Sema/warn-lifetime-safety-suggestions.cpp
R clang/test/Sema/warn-lifetime-safety.cpp
M clang/tools/clang-sycl-linker/CMakeLists.txt
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
M clang/tools/clang-sycl-linker/SYCLLinkOpts.td
R clang/unittests/Basic/AtomicLineLoggerTest.cpp
M clang/unittests/Basic/CMakeLists.txt
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendActionTest.cpp
M compiler-rt/lib/builtins/cpu_model/riscv/hwprobe.inc
M compiler-rt/lib/profile/InstrProfilingFile.c
M compiler-rt/lib/profile/InstrProfilingPlatformROCm.cpp
M compiler-rt/test/fuzzer/features_dir.test
M compiler-rt/test/fuzzer/fork-sigusr.test
M compiler-rt/test/fuzzer/lit.cfg.py
M compiler-rt/test/fuzzer/merge-posix.test
M compiler-rt/test/fuzzer/merge-sigusr.test
M compiler-rt/test/fuzzer/sigint.test
M compiler-rt/test/fuzzer/sigusr.test
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M flang-rt/lib/runtime/__fortran_builtins.f90
M flang/CMakeLists.txt
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/lib/Parser/Fortran-parsers.cpp
M flang/lib/Semantics/check-cuda.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/expression.cpp
M flang/test/Fir/CUDA/cuda-device-func-transform.mlir
M flang/test/Fir/CUDA/cuda-global-addr.mlir
M flang/test/Fir/mem2reg.mlir
A flang/test/Lower/OpenACC/Todo/acc-unstructured-combined-construct.f90
A flang/test/Lower/OpenACC/Todo/acc-unstructured-loop-construct.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
M flang/test/Lower/OpenMP/Todo/error.f90
A flang/test/Lower/OpenMP/nothing.f90
A flang/test/Parser/recovery09.f90
M flang/test/Semantics/OpenMP/linear-clause01.f90
A flang/test/Semantics/cuf-generic-literal-host.cuf
M flang/test/Semantics/cuf09.cuf
A flang/test/Semantics/cuf28.cuf
M libc/config/baremetal/config.json
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
M libc/include/llvm-libc-types/struct_tm.h
A libc/include/llvm-libc-types/tm_gmtoff_t.h
M libc/include/stdlib.yaml
M libc/include/time.yaml
M libc/src/__support/str_to_integer.h
M libc/src/__support/threads/linux/futex_utils.h
M libc/src/__support/threads/raw_mutex.h
M libc/src/__support/threads/raw_rwlock.h
M libc/src/stdlib/CMakeLists.txt
A libc/src/stdlib/mkstemp.cpp
A libc/src/stdlib/mkstemp.h
M libc/src/time/CMakeLists.txt
M libc/src/time/asctime.cpp
M libc/src/time/asctime_r.cpp
M libc/src/time/ctime.cpp
M libc/src/time/ctime_r.cpp
M libc/src/time/gmtime.cpp
M libc/src/time/gmtime_r.cpp
M libc/src/time/localtime.cpp
M libc/src/time/localtime_r.cpp
M libc/src/time/mktime.cpp
M libc/src/time/strftime.cpp
M libc/src/time/strftime_core/CMakeLists.txt
M libc/src/time/strftime_core/composite_converter.h
M libc/src/time/strftime_core/converter.h
M libc/src/time/strftime_core/num_converter.h
M libc/src/time/strftime_core/str_converter.h
M libc/src/time/strftime_l.cpp
M libc/src/time/time_utils.cpp
M libc/src/time/time_utils.h
M libc/test/integration/src/__support/threads/futex_requeue_test.cpp
M libc/test/src/__support/str_to_integer_test.cpp
M libc/test/src/math/RoundToIntegerTest.h
M libc/test/src/stdlib/CMakeLists.txt
M libc/test/src/stdlib/StrtolTest.h
A libc/test/src/stdlib/mkstemp_test.cpp
M libc/test/src/time/asctime_r_test.cpp
M libc/test/src/time/asctime_test.cpp
M libc/test/src/time/ctime_r_test.cpp
M libc/test/src/time/ctime_test.cpp
M libc/test/src/time/gmtime_r_test.cpp
M libc/test/src/time/gmtime_test.cpp
M libc/test/src/time/localtime_r_test.cpp
M libc/test/src/time/localtime_test.cpp
M libc/test/src/time/mktime_test.cpp
M libc/test/src/time/strftime_test.cpp
M libc/test/src/wchar/WcstolTest.h
M libcxx/include/optional
M libcxx/test/std/utilities/optional/optional.syn/optional_in_place_t.verify.cpp
M libcxx/test/std/utilities/optional/optional.syn/optional_nullopt_t.verify.cpp
M lld/MachO/BPSectionOrderer.cpp
M lld/MachO/Driver.cpp
M lld/MachO/ICF.cpp
M lld/MachO/InputFiles.cpp
M lld/MachO/InputSection.h
M lld/MachO/SectionPriorities.cpp
M lld/MachO/SymbolTable.cpp
M lld/MachO/SymbolTable.h
M lld/MachO/Symbols.cpp
M lld/MachO/Symbols.h
M lld/MachO/SyntheticSections.cpp
M lld/MachO/Writer.cpp
A lld/test/MachO/bp-section-orderer-cold.s
A lld/test/MachO/cold-func-weak-merge.s
A lld/test/MachO/cold-func.s
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
M lldb/source/Plugins/Process/Windows/Common/CMakeLists.txt
A lldb/source/Plugins/Process/Windows/Common/ExceptionRecord.cpp
M lldb/source/Plugins/Process/Windows/Common/ExceptionRecord.h
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.h
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.h
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/invalid-vector/TestDataFormatterLibcxxInvalidVectorSimulator.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/invalid-vector/main.cpp
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/vector/Makefile
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/vector/TestDataFormatterLibcxxVectorSimulator.py
A lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx-simulators/vector/main.cpp
M lldb/test/API/macosx/simulator/TestSimulatorPlatform.py
M llvm/docs/CommandGuide/lit.rst
M llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl07.rst
M llvm/examples/Kaleidoscope/Chapter7/toy.cpp
M llvm/include/llvm/ADT/Bitset.h
M llvm/include/llvm/ADT/StringExtras.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/IR/BundleAttributes.h
M llvm/include/llvm/IR/Intrinsics.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/include/llvm/IR/Value.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MIRPrintingPass.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/VirtRegMap.cpp
M llvm/lib/DTLTO/DTLTO.cpp
M llvm/lib/Frontend/HLSL/CBuffer.cpp
M llvm/lib/IR/BundleAttributes.cpp
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCParser/COFFMasmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MC/MCWin64EH.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Support/KnownFPClass.cpp
M llvm/lib/Support/Win64EH.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.h
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/DirectX/DXILCBufferAccess.cpp
M llvm/lib/Target/DirectX/DirectXIRPasses/DXILDebugInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/SPIRV/SPIRVCBufferAccess.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Scalar/MergeICmps.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Analysis/CostModel/AArch64/arith-fp.ll
M llvm/test/Analysis/CostModel/AArch64/reduce-fadd.ll
M llvm/test/Analysis/ScalarEvolution/shift-op.ll
A llvm/test/Analysis/ValueTracking/known-non-zero-shr-add.ll
A llvm/test/Bitcode/byte-constants.ll
M llvm/test/CodeGen/AArch64/arm64e-tail-call-autib.ll
M llvm/test/CodeGen/AArch64/ext-narrow-index.ll
M llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
M llvm/test/CodeGen/AArch64/pauth-lr-tail-call-fpdiff.ll
A llvm/test/CodeGen/AArch64/shuffle-slide-to-shift.ll
M llvm/test/CodeGen/AArch64/sme-intrinsics-mova-insert.ll
A llvm/test/CodeGen/AArch64/sme2p3-intrinsics-luti6.ll
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics-luti6.ll
A llvm/test/CodeGen/AArch64/swifttail-ptrauth.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.subdword.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-max-pregfx12.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-pregfx12.ll
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
A llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.fmt-error.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.prefetch.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
A llvm/test/CodeGen/AMDGPU/packed-fp64.ll
A llvm/test/CodeGen/AMDGPU/packed-u64.ll
A llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
R llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll
M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
A llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
A llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll
M llvm/test/CodeGen/AMDGPU/wmma-coexecution-valu-hazards.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
A llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1251-w32.mir
A llvm/test/CodeGen/DirectX/DebugInfo/dbg-assign.ll
A llvm/test/CodeGen/DirectX/DebugInfo/dbg-value-arglist.ll
A llvm/test/CodeGen/DirectX/DebugInfo/di-commonblock.ll
A llvm/test/CodeGen/DirectX/cbuffer_global_elim.ll
A llvm/test/CodeGen/DirectX/switch-to-lookup-table-i16-narrowing.ll
A llvm/test/CodeGen/DirectX/switch-to-lookup-table-no-i8-narrowing.ll
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-phys.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-split.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-self-split.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash.mir
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
M llvm/test/CodeGen/SPIRV/FCmpFalse_Vec.ll
A llvm/test/CodeGen/SPIRV/cbuffer_global_elim.ll
A llvm/test/CodeGen/SPIRV/constant/local-zero-constants.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-vector-skipped.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-type-vector.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_poison_freeze/freeze-aggregate.ll
A llvm/test/CodeGen/SPIRV/freeze-aggregate.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/is_fpclass.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/signed_arithmetic_overflow.ll
M llvm/test/CodeGen/X86/stack-coloring-setjmp.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1_err.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_wmma_w32.s
M llvm/test/MC/AMDGPU/gfx1250_asm_wmma_w32_err.s
A llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1251_err.s
M llvm/test/MC/COFF/seh-unwindv3-error.s
M llvm/test/MC/COFF/seh-unwindv3-inheritance.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_wmma_w32.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
A llvm/test/TableGen/intrinsic-overload-index-oor.td
M llvm/test/TableGen/intrinsic-struct.td
M llvm/test/ThinLTO/X86/dtlto/timetrace.ll
M llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll
M llvm/test/Transforms/ConstraintElimination/geps-unsigned-predicates.ll
M llvm/test/Transforms/InstCombine/assume.ll
M llvm/test/Transforms/InstCombine/modular-format.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-canonicalize.ll
M llvm/test/Transforms/InstSimplify/fold-intrinsics.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll
R llvm/test/Transforms/LICM/vector-insert.ll
M llvm/test/Transforms/LoopInterchange/lcssa-incoming-value-is-not-instr.ll
A llvm/test/Transforms/LoopUnroll/runtime-unroll-reductions-min-max.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
M llvm/test/Transforms/LoopVectorize/RISCV/gather-scatter-cost.ll
A llvm/test/Transforms/LoopVectorize/RISCV/i128-trip-count-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
A llvm/test/Transforms/LoopVectorize/RISCV/stepvector-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-gather-scatter.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/cast-costs.ll
M llvm/test/Transforms/LoopVectorize/epilog-iv-select-cmp.ll
A llvm/test/Transforms/LoopVectorize/induction-cost.ll
M llvm/test/Transforms/LoopVectorize/vscale-cost.ll
M llvm/test/Transforms/MergeICmps/X86/no-gep-other-work.ll
M llvm/test/Transforms/MergeICmps/X86/opaque-ptr.ll
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
M llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll
M llvm/test/Verifier/modular-format.ll
A llvm/test/tools/dxil-dis/dbg-assign.ll
A llvm/test/tools/dxil-dis/dbg-value-arglist.ll
A llvm/test/tools/dxil-dis/di-commonblock.ll
A llvm/test/tools/llvm-diff/callsite-assumption-passing.ll
A llvm/test/tools/llvm-ml/beginepilog_error.asm
M llvm/test/tools/llvm-ml/builtin_symbols.asm
A llvm/test/tools/llvm-ml/epilog_directive_errors.asm
A llvm/test/tools/llvm-ml/epilog_directives.asm
A llvm/test/tools/llvm-ml/proc_frame_v3.asm
A llvm/test/tools/llvm-ml/prolog_directive_errors.asm
A llvm/test/tools/llvm-ml/unwindv3_required_errors.asm
M llvm/test/tools/llvm-objdump/COFF/win64-unwindv3-multi-epilog.yaml
M llvm/test/tools/llvm-readobj/COFF/unwind-x86_64-v3-multi-epilog.yaml
M llvm/tools/llvm-diff/lib/DifferenceEngine.cpp
M llvm/tools/llvm-ml/Opts.td
M llvm/tools/llvm-ml/llvm-ml.cpp
M llvm/tools/llvm-objdump/COFFDump.cpp
M llvm/tools/llvm-readobj/Win64EHDumper.cpp
M llvm/unittests/ADT/BitsetTest.cpp
M llvm/unittests/Support/GlobPatternTest.cpp
M llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
M llvm/utils/TableGen/Common/CodeGenHwModes.cpp
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/readability/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/ObjectFile/Mach-O/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Windows/Common/BUILD.gn
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/MC/BUILD.gn
M llvm/utils/lit/lit/TestRunner.py
M llvm/utils/lit/tests/substitutions.py
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosa.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLAttrs.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLEnums.td
M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
M mlir/include/mlir/Dialect/Quant/IR/Quant.h
M mlir/include/mlir/Dialect/Quant/IR/QuantBase.td
M mlir/include/mlir/Dialect/Quant/IR/QuantDialectBytecode.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/Vector/Utils/VectorUtils.h
M mlir/include/mlir/Dialect/XeGPU/Transforms/Transforms.h
M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/lib/Conversion/TosaToSPIRVTosa/CMakeLists.txt
A mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaCustom.cpp
M mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaPass.cpp
M mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
M mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
M mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp
M mlir/lib/Dialect/Arith/IR/ArithDialect.cpp
M mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp
M mlir/lib/Dialect/Quant/IR/QuantDialectBytecode.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/LowerVectorContract.cpp
M mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Dialect/XeGPU/Utils/CMakeLists.txt
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
A mlir/test/Conversion/TosaToSPIRVTosa/custom-op-domain-to-opcode-invalid.mlir
A mlir/test/Conversion/TosaToSPIRVTosa/custom-op-domain-to-opcode.mlir
A mlir/test/Conversion/XeGPUToXeVM/extf_truncf.mlir
M mlir/test/Conversion/XeVMToLLVM/xevm_mx-to-llvm.mlir
M mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir
M mlir/test/Dialect/GPU/module-to-binary-rocdl.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/module-roundtrip.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Dialect/LLVMIR/xevm.mlir
M mlir/test/Dialect/Quant/Bytecode/types.mlir
M mlir/test/Dialect/SPIRV/IR/gl-ops.mlir
M mlir/test/Dialect/SPIRV/Transforms/canonicalize.mlir
M mlir/test/Dialect/Vector/vector-contract-to-parallel-arith-transforms.mlir
M mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute-unit.mlir
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
A mlir/test/IR/test-func-erase-arg-error.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_raw.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_bf16.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_fp4.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_fp4_bf16.mlir
M mlir/test/Target/LLVMIR/nvvm/barrier.mlir
M mlir/test/Target/LLVMIR/nvvm/tensormap_replace_invalid.mlir
A mlir/test/Target/LLVMIR/rocdl-module-flags.mlir
M mlir/test/Target/SPIRV/gl-ops.mlir
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
M mlir/test/lib/IR/TestFunc.cpp
M openmp/runtime/cmake/LibompExports.cmake
M orc-rt/include/orc-rt-c/ExternC.h
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
minor simplification
Created using spr 1.3.8-beta.1
Compare: https://github.com/llvm/llvm-project/compare/4d5862c26a76...81877c8b8caf
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