[all-commits] [llvm/llvm-project] c3a146: AMDGPU/GlobalISel: RegBankLegalize rules for sched...
Stanislav Mekhanoshin via All-commits
all-commits at lists.llvm.org
Fri Jun 12 16:09:04 PDT 2026
Branch: refs/heads/users/petar-avramovic/pk-f64
Home: https://github.com/llvm/llvm-project
Commit: c3a146a4e8fab800c621acc401dbdf1d0c960be8
https://github.com/llvm/llvm-project/commit/c3a146a4e8fab800c621acc401dbdf1d0c960be8
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for sched barriers intrinsics (#203425)
Add rules for sched barrier intrinsics. Note, there are regressions due
to AGPR results being copied back to VGPR un-necessarily. That will be
addressed in a future follow-up patch.
Commit: 8d2661b2d54e9dec96cba72ff5089c6fa7482bf3
https://github.com/llvm/llvm-project/commit/8d2661b2d54e9dec96cba72ff5089c6fa7482bf3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
Log Message:
-----------
[X86] combineConcatVectorOps - concat(rotate(x,a),rotate(y,b)) -> rotate(concat(x,y),concat(a,b)) (#203553)
128/256-bit rotates are widened in tablegen, we don't need to limit
these to VLX targets - any AVX512 target can perform these
We already have test coverage to ensure 128-bit XOP rotates don't get
concatenated to 256-bit
Commit: bdc06892cdd37c0a52717373ad7774136ca72b63
https://github.com/llvm/llvm-project/commit/bdc06892cdd37c0a52717373ad7774136ca72b63
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/test/Fir/mem2reg.mlir
Log Message:
-----------
[flang] Avoid invalid declare_value for promoted dummy-scope variables (#202498)
This fixes a verifier failure in mem2reg after inlining a CUDA device
procedure. When a promoted FIR alloca had an associated fir.declare with
a dummy_scope, mem2reg could create a fir.declare_value at a loop header
where the original dummy scope did not dominate.
Skip creating block-argument fir.declare_value ops for such
declarations, matching the existing replaced-value handling. Add a FIR
mem2reg regression test for the loop-header block argument case.
Commit: bbeb2d519171b57bbabb25ca07223c286cdecea2
https://github.com/llvm/llvm-project/commit/bbeb2d519171b57bbabb25ca07223c286cdecea2
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
A flang/test/Lower/OpenACC/Todo/acc-unstructured-combined-construct.f90
A flang/test/Lower/OpenACC/Todo/acc-unstructured-loop-construct.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
Log Message:
-----------
[OpenACC][flang] Emit NYI when unstructured loops are associated with OpenACC directives (#202948)
Commit: 168666950ea9cd85471053319e216399e9750028
https://github.com/llvm/llvm-project/commit/168666950ea9cd85471053319e216399e9750028
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/IR/Value.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
Log Message:
-----------
[IR] Make CanBeFreed calculation optional (NFC) (#203490)
Make the CanBeFreed argument of getPointerDereferenceableBytes() a
pointer, so that nullptr can be passed if we're not interested in
whether frees are possible or not.
Nearly all places don't actually care about frees, including BasicAA,
which is the hottest caller of this API. This improves compile-time when
deref-at-point semantics are enabled.
I've kept the argument required so that callers still have to make an
explicit choice to ignore frees. (I'd be open to making it optional
though, given that only a single caller actually cares...)
Commit: c5654d53c008522d2da165f05b682aafa36d7189
https://github.com/llvm/llvm-project/commit/c5654d53c008522d2da165f05b682aafa36d7189
Author: Yuan Suo <suoyuan666 at s5n.xyz>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/test/Sema/LifetimeSafety/annotation-suggestions.cpp
M clang/test/Sema/LifetimeSafety/nocfg.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
Log Message:
-----------
[LifetimeSafety] Introduce buildOriginFlowChain for use-after-scope (#199345)
After adding `buildOriginFlowChain`, we need to choose a diagnostic type
that is as simple as possible to verify its feasibility during `Sema`
diagnostics.
I did not choose the annotation suggestions described in
https://github.com/llvm/llvm-project/pull/188467/#issuecomment-4359071778
as the first target to implement, because it does not seem to occur
within a single CFG block. The `IssueFact` always resides in the block
preceding the `OriginEscapesFact`, which causes me to always get an
empty `OriginFlowChain`.
Since we use `buildOriginFlowChain`, we can directly trace distinct
assignment steps that occur within a single source-level expression. For
example:
```cpp
#include <vector>
#include <string>
template<class... T> void use(T... arg);
void operator_star_arrow_of_iterators_false_positive_no_cfg_analysis() {
std::vector<std::pair<int, std::string>> v;
const char* p = v.begin()->second.data();
const char* q = (*v.begin()).second.data();
const std::string& r = (*v.begin()).second;
auto temporary = []() { return std::vector<std::pair<int, std::string>>{{1, "1"}}; };
const char* x = temporary().begin()->second.data();
const char* y = (*temporary().begin()).second.data();
const std::string& z = (*temporary().begin()).second;
use(p, q, r, x, y, z);
}
```
The code above produces the following diagnostic output:
```txt
pr.cpp:13:19: warning: local temporary object does not live long enough [-Wlifetime-safety-use-after-scope]
13 | const char* x = temporary().begin()->second.data();
| ^~~~~~~~~~~
pr.cpp:13:52: note: destroyed here
13 | const char* x = temporary().begin()->second.data();
| ^
pr.cpp:13:19: note: expression aliases the storage of local temporary object
13 | const char* x = temporary().begin()->second.data();
| ^~~~~~~~~~~~~~~~~~~
pr.cpp:13:19: note: expression aliases the storage of local temporary object
13 | const char* x = temporary().begin()->second.data();
| ^~~~~~~~~~~~~~~~~~~~~
pr.cpp:13:19: note: expression aliases the storage of local temporary object
13 | const char* x = temporary().begin()->second.data();
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
pr.cpp:16:16: note: later used here
16 | use(p, q, r, x, y, z);
| ^
pr.cpp:15:28: warning: local temporary object does not live long enough [-Wlifetime-safety-use-after-scope]
15 | const std::string& z = (*temporary().begin()).second;
| ^~~~~~~~~~~
pr.cpp:15:49: note: destroyed here
15 | const std::string& z = (*temporary().begin()).second;
| ^
pr.cpp:15:28: note: expression aliases the storage of local temporary object
15 | const std::string& z = (*temporary().begin()).second;
| ^~~~~~~~~~~~~~~~~~~
pr.cpp:15:27: note: expression aliases the storage of local temporary object
15 | const std::string& z = (*temporary().begin()).second;
| ^~~~~~~~~~~~~~~~~~~~
pr.cpp:16:22: note: later used here
16 | use(p, q, r, x, y, z);
| ^
pr.cpp:14:21: warning: local temporary object does not live long enough [-Wlifetime-safety-use-after-scope]
14 | const char* y = (*temporary().begin()).second.data();
| ^~~~~~~~~~~
pr.cpp:14:54: note: destroyed here
14 | const char* y = (*temporary().begin()).second.data();
| ^
pr.cpp:14:21: note: expression aliases the storage of local temporary object
14 | const char* y = (*temporary().begin()).second.data();
| ^~~~~~~~~~~~~~~~~~~
pr.cpp:14:20: note: expression aliases the storage of local temporary object
14 | const char* y = (*temporary().begin()).second.data();
| ^~~~~~~~~~~~~~~~~~~~
pr.cpp:14:19: note: expression aliases the storage of local temporary object
14 | const char* y = (*temporary().begin()).second.data();
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
pr.cpp:16:19: note: later used here
16 | use(p, q, r, x, y, z);
| ^
3 warnings generated.
```
---------
Signed-off-by: Yuan Suo <suoyuan666 at s5n.xyz>
Commit: 422af7cca672a717bd9505a486e287fa2734bbc9
https://github.com/llvm/llvm-project/commit/422af7cca672a717bd9505a486e287fa2734bbc9
Author: Quentin Colombet <quentin.colombet at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MIRPrintingPass.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/VirtRegMap.cpp
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-phys.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-split.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-self-split.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash.mir
Log Message:
-----------
[MIR] Save internal VirtRegMap state in MIR (#197361)
Adds two optional fields to the per-vreg YAML record so MIR tests can
express VirtRegMap state that previously had no representation:
registers:
- { id: 1, class: vgpr_32, split-from: '%0', assigned-phys: '$vgpr5' }
Testing passes that consume sibling-register information (e.g.
InlineSpiller) requires constructing a VirtRegMap with split
relationships from a MIR test, which implies triggering live-range
splitting at minimum and make reproducers unnecessarily complicated.
So this change introduces a mechanism to serialize/deserialize the state
of the VirtRegMap pass.
Mechanism:
- For serialization:
- MIRPrinter emits the new fields only when the VirtRegMap is available.
- For deserialization:
- MIRParser stashes parsed entries in the MachineRegisterInfo object
- VirtRegMap::init() drains the stash via assignVirt2Phys and
setIsSplitFromReg, then clears it.
Validation at parse time:
- 'assigned-phys' must be a physical register.
- 'split-from' must reference a different vreg than 'id'.
- 'split-from' physregs / named-vreg references already rejected
by parseStandaloneVirtualRegister.
I'm not super happy about stashing the VRM info in the MRI, but that's
a small price to pay.
Commit: 1b774ab021698428374815fb8d4d88855c3b2a48
https://github.com/llvm/llvm-project/commit/1b774ab021698428374815fb8d4d88855c3b2a48
Author: Mikołaj Piróg <mikolaj.maciej.pirog at intel.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/test/CodeGen/X86/stack-coloring-setjmp.ll
Log Message:
-----------
[StackColoring] Cleanup stack-coloring test (NFC) (#203551)
This simply applies postcommit suggestions made here:
https://github.com/llvm/llvm-project/pull/199959
Commit: 7814cc9454cf454acdc7385fc41809a6bdf5d7f8
https://github.com/llvm/llvm-project/commit/7814cc9454cf454acdc7385fc41809a6bdf5d7f8
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/Basic/arm_sve.td
A clang/test/CodeGen/AArch64/sme2p3-intrinsics/acle_sme2p3_luti6.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6_lane_x2.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2p3.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2p3___sme_AND_LP_sve2p3_OR_sme2p3_RP.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve2p3.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme2p3.c
A clang/test/Sema/aarch64-sme2p3-intrinsics/acle_sme2p3_imm.c
M clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_imm.cpp
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/sme2p3-intrinsics-luti6.ll
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics-luti6.ll
Log Message:
-----------
[AArch64][clang][llvm] Add ACLE Armv9.7 lookup table intrinsics (#187046)
Add support for the following Armv9.7-A Lookup Table (lut)
instruction intrinsics, as defined in the ACLE[1]:
SVE2.3:
```c
// Variants are also available for: _u8 _mf8
svint8_t svluti6[_s8](svint8x2_t table, svuint8_t indices);
```
SVE2.3 and SME2.3:
``` c
// Variants are also available for _u16_x2 and _f16_x2.
svint16_t svluti6_lane[_s16_x2](svint16x2_t table, svuint8_t indices, uint64_t imm_idx);
```
SME2.3:
```c
// Variants are also available for: _u16, _f16 and _bf16.
svint16x4_t svluti6_lane_s16_x4[_s16_x2](svint16x2_t table, svuint8x2_t indices, uint64_t imm_idx);
// Variants are also available for: _u8 and _mf8.
svint8x4_t svluti6_zt_s8_x4(uint64_t zt0, svuint8x3_t zn) __arm_streaming __arm_in("zt0");
// Variants are also available for: _u8 and _mf8.
svint8_t svluti6_zt_s8(uint64_t zt0, svuint8_t zn) __arm_streaming __arm_in("zt0");
```
[1] https://github.com/ARM-software/acle/pull/428/
Commit: 5906827e155cc5fca10cd505b88a4e21b861d65b
https://github.com/llvm/llvm-project/commit/5906827e155cc5fca10cd505b88a4e21b861d65b
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.h
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.h
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h
Log Message:
-----------
[lldb][Windows] Forward OUTPUT_DEBUG_STRING_EVENT through lldb-server (#203546)
Hoist `ReadDebugString` into `ProcessDebugger` so both plugins share it,
then add
`NativeProcessWindows::OnDebugString` that reads the string, converts
UTF-16 to
UTF-8 when needed, and delivers via `NativeDelegate::NewProcessOutput`.
Fixes `Process/Windows/output_debug_string.cpp` on Windows under
`LLDB_USE_LLDB_SERVER=1`.
Commit: 9f3ac763bd8c4be2db1a97cec13bb59c87a9595f
https://github.com/llvm/llvm-project/commit/9f3ac763bd8c4be2db1a97cec13bb59c87a9595f
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
Log Message:
-----------
[MLIR][XeGPU] Fix issue with expandDim (#203299)
In case, sgData is replicated or
bool sgDataReplicated = hasSgData && origSgDataDim ==
computeProduct(targetShape);
sgDataReplicate is evaluated to "true"
dimSizeCap and perSgShape shouldn't be divided by expSgLayout
Add a regression test (shape_cast_collapse_replicated) covering the
replicated sg_data collapse.
Commit: 9bbed741e260753de029fcf7b22844fe23362a39
https://github.com/llvm/llvm-project/commit/9bbed741e260753de029fcf7b22844fe23362a39
Author: dibrinsofor <64705019+dibrinsofor at users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/ext-narrow-index.ll
M llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
A llvm/test/CodeGen/AArch64/shuffle-slide-to-shift.ll
Log Message:
-----------
[AArch64] Optimize vector slide shuffles with zeros to use shift instructions (#185170)
We currently emit `movi`+`ext` instructions when generating code for
shuffle slides of a 64-bit vector left/right and fill it with zeros.
This patch optimizes these patterns to use a single `ushr`/`shl`
instruction instead.
Example:
```llvm
define <8 x i8> @slide_left(<8 x i8> %v) {
%r = shufflevector <8 x i8> %v, <8 x i8> zeroinitializer,
<8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
ret <8 x i8> %r
}
```
Before, we generate:
```
movi v1.2d, #0
ext v0.8b, v0.8b, v1.8b, #1
```
Now:
```
ushr d0, d0, #8
```
Fixes: #183398
Alive2 proof: https://alive2.llvm.org/ce/z/QaW5CQ
---------
Signed-off-by: Dibri Nsofor <dibrinsofor at gmail.com>
Commit: c9938eb76ca653abff8d0b7c99bd74aec57c4758
https://github.com/llvm/llvm-project/commit/c9938eb76ca653abff8d0b7c99bd74aec57c4758
Author: nirhersh <77844231+nirhersh at users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/lib/Dialect/Arith/IR/ArithDialect.cpp
M mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp
M mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir
Log Message:
-----------
[mlir][arith] Implement ValueBoundsOpInterface for min/max ops (#203269)
Add ValueBoundsOpInterface external models for the arith integer min/max operations: arith.minsi and arith.maxsi.
---------
Co-authored-by: Nir Herscovici <nir.herscovici at mobileye.com>
Commit: c62768b10e5e16c494eef8289452a7d7d97798bf
https://github.com/llvm/llvm-project/commit/c62768b10e5e16c494eef8289452a7d7d97798bf
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/test/Target/LLVMIR/nvvm/tensormap_replace_invalid.mlir
Log Message:
-----------
[MLIR][NVVM] Fix valid range of ord in tensormap.replace op (#202853)
Fixes the valid range of the `ord` attribute in the NVVM dialect
`tensormap.replace` op to be `0-4` as indicated in the PTX ISA.
PTX ISA Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-tensormap-replace
Commit: 2d1fb738d6f9eb109a2f1e0405397565f25fece4
https://github.com/llvm/llvm-project/commit/2d1fb738d6f9eb109a2f1e0405397565f25fece4
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLAttrs.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLEnums.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/test/Dialect/GPU/module-to-binary-rocdl.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/module-roundtrip.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
A mlir/test/Target/LLVMIR/rocdl-module-flags.mlir
Log Message:
-----------
[mlir][LLVM][ROCDL] Add buffer oob mode module flags, flag interfaces (#202729)
Now that the out-of-bounds mode for buffer accesses will be controlled
by a module flag and is no longer a function of the subtarget triple (as
of #160922) and since `ptr addrpace(7)` lowering will start respecting
this mode soon, add MLIR-level support for setting this flag.
After a few iterations, I think adding this module flag to
`llvm.module.flags` but adding interfaces for module flag attributes (so
that those wishing to set this flag don't need to know it has `max`
combining semantics or look up the enum values) is a
minimally-disruptive way to get a more ergonomic wrapper around this
functionality.
AI note: AI generated the code hehe, I reviewed it. The documentation
update to ModuleFlagsOp is mine.
(The LLVM PR that would want people to start explicitly setting
`relaxed` is #134329)
Co-authored-by: Codex <codex at openai.com>
Commit: 484b955581d976f97a47ef621c441e21c231aa23
https://github.com/llvm/llvm-project/commit/484b955581d976f97a47ef621c441e21c231aa23
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/test/CIR/CodeGen/ternary-throw.cpp
Log Message:
-----------
[CIR] Implement throw within an aggregate expression (#203404)
This implements CIR support for throwing an exception from within a
branch of a ternary expression that represents an aggregate prvalue. We
previously had support for throwing an exception within a ternary
aggregate expression, but when the expression uses a prvalue, it goes
through a different code path. The new implementation is just calling an
existing function from a different place. The bulk of what's being added
here is the testing.
Commit: 99a37aedebd7c69680e74ac83769a11eaefef1e7
https://github.com/llvm/llvm-project/commit/99a37aedebd7c69680e74ac83769a11eaefef1e7
Author: Quentin <qcoelho at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/ADT/StringExtras.h
Log Message:
-----------
[ADT][NFC] Fix documentation for arrayRefFromStringRef (#203430)
The documentation was describing the opposite behavior of what it does.
Commit: 17207c8feb9fc6c576ce820ff4583e337dc0452e
https://github.com/llvm/llvm-project/commit/17207c8feb9fc6c576ce820ff4583e337dc0452e
Author: Utkarsh Saxena <usx at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/test/Sema/LifetimeSafety/annotation-suggestions.cpp
M clang/test/Sema/LifetimeSafety/nocfg.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
Log Message:
-----------
[LifetimeSafety] Change "local temporary object" to "temporary object" in diagnostics (#203573)
Commit: 878bbacfb0e6ced7c0313d5f7c097d7c94a1c4da
https://github.com/llvm/llvm-project/commit/878bbacfb0e6ced7c0313d5f7c097d7c94a1c4da
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/MC/MCWin64EH.cpp
M llvm/lib/Support/Win64EH.cpp
M llvm/test/MC/COFF/seh-unwindv3-inheritance.s
M llvm/test/tools/llvm-objdump/COFF/win64-unwindv3-multi-epilog.yaml
M llvm/test/tools/llvm-readobj/COFF/unwind-x86_64-v3-multi-epilog.yaml
M llvm/tools/llvm-objdump/COFFDump.cpp
M llvm/tools/llvm-readobj/Win64EHDumper.cpp
Log Message:
-----------
[win][x64] Windows x64 unwind v3: Update epilog inheritance per spec clarification (#202778)
The Windows x64 unwind v3 spec was clarified
(MicrosoftDocs/cpp-docs#5936) to state that an EPILOG_INFO_V3 record
with `NumberOfOps == 0` inherits its effective fields from the first
*preceding* descriptor with `NumberOfOps != 0` (the "base"), not the
immediately preceding one. Additionally, Flags bits 0 and 1 are no
longer inherited; the producer must replicate them so they match the
base descriptor.
- Encoder (MCWin64EH.cpp): compare each epilog against the tracked base
descriptor, and emit EPILOG_INFO_LARGE in inherited descriptors' own
flags byte.
- Decoder (Win64EH.cpp): track the base index and inherit from it; keep
the record's own flags byte instead of copying the previous record's.
- Dumpers (llvm-readobj, llvm-objdump): reword "previous epilog" to
"base epilog".
- Tests: update multi-epilog expectations and add a LARGE
inherited-epilog case to seh-unwindv3-inheritance.s.
Commit: 528e6f9a030c4b3bf760807c22c98f17fb582f5f
https://github.com/llvm/llvm-project/commit/528e6f9a030c4b3bf760807c22c98f17fb582f5f
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/test/CodeGen/AArch64/sme-intrinsics-mova-insert.ll
Log Message:
-----------
[AArch64] Avoid creating a new generic constant in SelectSMETileSlice (#203344)
This was creating a new ISD::Constant node during instruction selection,
which may also need lowering (e.g., to a `mov gpr, wzr`). The issue with
this is the new constant node will not end up on the instruction
selection worklist, as the complex pattern executes after the worklist
has been prepared. This means the constant will lower directly to an
immediate. This issue was hidden in some cases by `getConstant()`
returning a pre-existing `ISD::Constant` node already within the
instruction selection worklist.
This patch works around this by directly emitting a `CopyFromReg WZR`
within SelectSMETileSlice, which does not need further instruction
selection.
Fixes #203295
Commit: 9240c64f4528064cec31e8875fb891b473f8ca7c
https://github.com/llvm/llvm-project/commit/9240c64f4528064cec31e8875fb891b473f8ca7c
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/IR/BundleAttributes.h
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/IR/BundleAttributes.cpp
Log Message:
-----------
[LVI][ValueTracking] Merge checking whether assumes imply nonnull (#203523)
Commit: eaef650f57900b36751dea4e0383de1e73cdff29
https://github.com/llvm/llvm-project/commit/eaef650f57900b36751dea4e0383de1e73cdff29
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
A clang/test/CIR/CodeGen/cxx-construct-lvalue.cpp
Log Message:
-----------
[CIR] Implement handling for CXXConstructLValue expressions (#203402)
This implements the handling to emit an l-value for CXXConstructExpr and
CXXTemporaryObjectExpr expressions. This is a simple copy from the
equivalent code in classic codegen and uses existing CIR code for most
of the actual work.
A multi-argument constructor call written with explicit type syntax
produces a CXXTemporaryObjectExpr. Using it as the base of a member
access reaches emitLValue with that expression class. A single-argument
constructor call performs a constructor conversion, so the base of the
member access is a CXXFunctionalCastExpr whose subexpression is a
CXXConstructExpr. emitCastLValue forwards to the subexpression, reaching
emitLValue with the CXXConstructExpr class.
Commit: e476b23c5facd1705f06ee60f1e62869c638f395
https://github.com/llvm/llvm-project/commit/e476b23c5facd1705f06ee60f1e62869c638f395
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M compiler-rt/test/fuzzer/fork-sigusr.test
M compiler-rt/test/fuzzer/merge-sigusr.test
M compiler-rt/test/fuzzer/sigint.test
M compiler-rt/test/fuzzer/sigusr.test
Log Message:
-----------
[Fuzzer] Make signal tests work with internal shell (#203445)
Wrap some commands in bash as it seemed like the least bad option. The
alternative is to use setsid and run the other commands in the internal
shell, but them it's impossible to use wait and we run into reliability
issues because of that.
Commit: 473ca91cdb03d01394eea440ea4f3a14cdc04b6e
https://github.com/llvm/llvm-project/commit/473ca91cdb03d01394eea440ea4f3a14cdc04b6e
Author: Jan Korous <jkorous at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Frontend/FrontendOptions.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendAction.cpp
M clang/test/Analysis/Scalable/PointerFlow/external-inline-function-in-multi-tu.test
M clang/test/Analysis/Scalable/call-graph.cpp
A clang/test/Analysis/Scalable/cli-errors-compilation-unit-id.cpp
M clang/test/Analysis/Scalable/command-line-interface.cpp
M clang/test/Analysis/Scalable/downgradable-errors.cpp
M clang/test/Analysis/Scalable/extraction-works-alongside-compilation.cpp
M clang/test/Analysis/Scalable/help.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendActionTest.cpp
Log Message:
-----------
[clang][ssaf] Add --ssaf-compilation-unit-id= flag (#203345)
The TU summary extractor previously sourced the CompilationUnit
namespace name from clang's `InFile` argument, which made the identity
of a TU summary depend on the file path the build system passed to
clang. Have the build system pass the identifier directly:
- New driver/cc1 option `--ssaf-compilation-unit-id=<id>`, marshalled
into `FrontendOptions::SSAFCompilationUnitId`.
- `TUSummaryRunner` builds its `BuildNamespace(CompilationUnit, ...)`
from the new option's value; `InFile` is no longer threaded into the
runner.
- New diagnostic `warn_ssaf_tu_summary_requires_compilation_unit_id`
(under `-Wscalable-static-analysis-framework`, `DefaultError`) fires
when `--ssaf-tu-summary-file=` is set without a non-empty
`--ssaf-compilation-unit-id=`. The runner falls back to the wrapped
consumer alone in that case, matching the existing setup-time SSAF
diagnostics.
Assisted-By: Claude Opus 4.7
Commit: fdd939dce1eb145e386dc3242661c3a73b759e4f
https://github.com/llvm/llvm-project/commit/fdd939dce1eb145e386dc3242661c3a73b759e4f
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/Transforms/Transforms.h
M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Dialect/XeGPU/Utils/CMakeLists.txt
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute-unit.mlir
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
Log Message:
-----------
[MLIR][XeGPU] Use context-aware type converter in WgToSgDistribute and Blocking pass (#194685)
This PR replaces the TypeConverter in xegpu-wg-to-sg-distribute and
xegpu-blocking with a context-aware converter that picks each value's
converted type from the layout attached to its defining op/use, removing
the need for the UnrealizedConversionCastOpPattern workaround for scf
ops.
Commit: 6dbe068edef96c13930471d602fd5fb876e9da04
https://github.com/llvm/llvm-project/commit/6dbe068edef96c13930471d602fd5fb876e9da04
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/MC/MCWin64EH.cpp
Log Message:
-----------
[Win][x64] Fix -Wunused-variable (#203591)
BaseEpiFlags is only used in assertions, so mark it maybe_unused to
avoid the warning in release builds.
Commit: 0a9cf8c6c3038f1a02fa2051d12c9e9d7ddb4aad
https://github.com/llvm/llvm-project/commit/0a9cf8c6c3038f1a02fa2051d12c9e9d7ddb4aad
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes fdd939d (#203593)
This fixes fdd939dce1eb145e386dc3242661c3a73b759e4f.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: e4a63425ba266f6027e7d257c9a79141c26aa8d8
https://github.com/llvm/llvm-project/commit/e4a63425ba266f6027e7d257c9a79141c26aa8d8
Author: Jiaqi He <heturing at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/riscv/hwprobe.inc
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/TargetParser/Host.cpp
Log Message:
-----------
[RISC-V] Add newer Linux hwprobe extensions detection (#192761)
Commit: 660771d4359b14fe56a5eef19c33f93475aee39e
https://github.com/llvm/llvm-project/commit/660771d4359b14fe56a5eef19c33f93475aee39e
Author: Jiachen Yuan <jiacheny at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/ADT/Bitset.h
M llvm/unittests/ADT/BitsetTest.cpp
Log Message:
-----------
Reapply "[ADT] Bitset: add shift operators, word accessors, and etc" (#195874)
Reapplies #193400, which was reverted in #195848 because it broke
buildbots with:
```
Bitset.h:271: error: static assertion failed: Unsupported word size
```
Root cause: a `static_assert(BitwordBits == 32, ...)` inside the
discarded `else` branch of `if constexpr (BitwordBits == 64)` in
`getWord64()`. The assert's condition is non-template-dependent
(`BitwordBits` derives from `sizeof(uintptr_t)`, not from `NumBits`), so
it is checked even though the branch is discarded, and fires on 64-bit
hosts. Related:
https://stackoverflow.com/questions/38304847/how-does-a-failed-static-assert-work-in-an-if-constexpr-false-block
Fix: drop the redundant inner `static_assert`. The class-level
`static_assert(BitwordBits == 64 || BitwordBits == 32, ...)` already
enforces the same invariant.
No functional change beyond the original PR.
---------
Co-authored-by: Rahul Joshi <rjoshi at nvidia.com>
Commit: 5a52d68d6b030b155580ff03f5f8ad0cc9dc2fd9
https://github.com/llvm/llvm-project/commit/5a52d68d6b030b155580ff03f5f8ad0cc9dc2fd9
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/MC/MCParser/COFFMasmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/test/MC/COFF/seh-unwindv3-error.s
A llvm/test/tools/llvm-ml/beginepilog_error.asm
M llvm/test/tools/llvm-ml/builtin_symbols.asm
A llvm/test/tools/llvm-ml/epilog_directive_errors.asm
A llvm/test/tools/llvm-ml/epilog_directives.asm
A llvm/test/tools/llvm-ml/proc_frame_v3.asm
A llvm/test/tools/llvm-ml/prolog_directive_errors.asm
A llvm/test/tools/llvm-ml/unwindv3_required_errors.asm
M llvm/tools/llvm-ml/Opts.td
M llvm/tools/llvm-ml/llvm-ml.cpp
Log Message:
-----------
[llvm-ml] Add MASM unwind v3 support for x64 exception handling and improve MSVC compat (#202809)
New command-line options:
- `/unwindv3`: Enable V3 unwind information format
New MASM directives:
- `.push2reg` / `.pop2reg`: Push/pop register pairs (PUSH2/POP2)
- `.beginepilog` / `.endepilog`: Delimit epilog unwind regions
- `.popreg`, `.freestack`, `.restorereg`, `.restorexmm128`,
`.unsetframe`: Epilog counterparts of existing prolog directives
- `.pushframe code`: MASM syntax for interrupt handlers with error codes
New built-in symbol:
- `@UnwindVersion`: Returns the current x64 unwind version being used.
Error diagnostics:
- Prolog directives after `.endprolog` are diagnosed
- Epilog directives outside `.beginepilog`/`.endepilog` are diagnosed
- Nested `.beginepilog` is diagnosed
- Unwind v3 directives or using extended registers in directives without
unwind v3 are diagnosed
Commit: f2957d7a56372cf8bd2b48aec81ae7c0fb38813f
https://github.com/llvm/llvm-project/commit/f2957d7a56372cf8bd2b48aec81ae7c0fb38813f
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
Log Message:
-----------
[flang][OpenMP] Add missing check for empty argument list (#203592)
Commit: 5036a80a20a6749f95b77a2c08786f42fdd056ac
https://github.com/llvm/llvm-project/commit/5036a80a20a6749f95b77a2c08786f42fdd056ac
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
Log Message:
-----------
[HLSL][NFC] Remove unused location argument (#203467)
The location argument was just passed around but never used.
Commit: 2a72cd87a5bb9db73708661e8760ff710460ae11
https://github.com/llvm/llvm-project/commit/2a72cd87a5bb9db73708661e8760ff710460ae11
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/unittests/Support/GlobPatternTest.cpp
Log Message:
-----------
[NFC][Support] Add test for inverted slash-agnostic matching (#203290)
Add a test case to GlobPatternTest to verify that inverted character
classes containing slashes (e.g. [^/] or [^\\]) behave correctly
under SlashAgnostic mode (i.e. they do not match either slash).
Assisted-by: Gemini
Commit: 64381998961b4b9324ab5a6f6015b285b59d6bb6
https://github.com/llvm/llvm-project/commit/64381998961b4b9324ab5a6f6015b285b59d6bb6
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
M llvm/test/Transforms/LoopVectorize/epilog-iv-select-cmp.ll
Log Message:
-----------
[VPlan] Introduce m_SelectLike and use to support 2-operand blends. (#194729)
We should be able to treat 2-operand blends like select by most VPlan
code. Add a new m_SelectLike matcher and use in places that only use the
matcher to extract operands.
Overall this leads to a small number of improvements in RISCV (~10 files
changed in a large IR corpus) and 2 loops changed on AArch64 with
tail-folding forced.
PR: https://github.com/llvm/llvm-project/pull/194729
Commit: fda7a72af7a76ac6b51a8a1b1222f878d76405ed
https://github.com/llvm/llvm-project/commit/fda7a72af7a76ac6b51a8a1b1222f878d76405ed
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1251_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
Log Message:
-----------
[AMGDPU] Add gfx1251 V_PK_MIN/MAX_NUM_F64 (#203596)
Also legalizes v2f64 fcanonicalize.
Commit: 2c1b71af78df9d7c22e225069971d3276d91d546
https://github.com/llvm/llvm-project/commit/2c1b71af78df9d7c22e225069971d3276d91d546
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Transforms/LoopVectorize/RISCV/i128-trip-count-evl.ll
Log Message:
-----------
[VPlan] Compute URem via APInt in materializeVectorTripCount (#203604)
materializeVectorTripCount has a shortcut for scalable steps: if the
constant trip count is divisible by the maximum possible runtime step,
the vector trip count equals the trip count directly. This called
APInt::getZExtValue unconditionally, which asserts when the constant
value needs more than 64 bits.
Compute the URem in APInt to fix the crash.
Commit: 1060a6be0a471106fd65a3f16937ee1c588dabed
https://github.com/llvm/llvm-project/commit/1060a6be0a471106fd65a3f16937ee1c588dabed
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
A llvm/test/CodeGen/DirectX/switch-to-lookup-table-i16-narrowing.ll
A llvm/test/CodeGen/DirectX/switch-to-lookup-table-no-i8-narrowing.ll
Log Message:
-----------
[SimplifyCFG][DirectX] Honor target minimum lookup table element width (#203103)
fixes #202481
This change adds a `TTI::getMinimumLookupTableEntryBitWidth()` (default
`8`) and fold it
into SimplifyCFG's `NeededBitWidth` computation so targets can prevent
unsupported
narrow lookup tables. DirectX returns 32 (or 16 with native 16-bit
types) so tables
never narrow to the unsupported i8 type.
> Assisted by Claude Opus 4.8
Commit: 10508afd0b14ffcf6819665e31d64d77ccd45d3f
https://github.com/llvm/llvm-project/commit/10508afd0b14ffcf6819665e31d64d77ccd45d3f
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowExtractor.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.h
M clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
Log Message:
-----------
Reland "[SSAF][Extractor] Make hard errors in PointerFlow and UnsafeBufferUsage Extractors quiet (#201953)" (#203602)
Reverted 7dcd1d2ad104c3f9748370a42dc775cd6e7e34dc and added '#ifndef
NDEBUG' guards for tests using 'llvm::setCurrentDebugType'.
Original message:
Hard errors were used in extractors during development to quickly
identify unsupported language constructs. This commit converts them to
DEBUG_WITH_TYPE so that these errors are silenced in release builds.
In addition, translating unsupported language constructs now silently
results in an empty EntityPointerLevelSet. The PointerFlowExtractor will
skip empty sets for either the source or the destination when building
edges to avoid an ill-formed edge set data structure.
rdar://178747892
Commit: 0b128394b9c796ebe4efd9e0dde38976fb291798
https://github.com/llvm/llvm-project/commit/0b128394b9c796ebe4efd9e0dde38976fb291798
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
A llvm/test/tools/llvm-diff/callsite-assumption-passing.ll
M llvm/tools/llvm-diff/lib/DifferenceEngine.cpp
Log Message:
-----------
[llvm-diff] Respect AllowAssumptions in diffCallSites (#203597)
diffCallSites always built an AssumptionContext, so call sites made
optimistic equivalence assumptions even when the caller disabled them.
This made matchForBlockDiff over-match, and the re-check in unify() then
hit the "structural differences second time around?" assertion.
Thread the caller's AssumptionContext into diffCallSites so call sites
honor the no-assumptions request like every other instruction kind.
Fixes #184133
Commit: 12d95c65fc99a3d5686f1d409572d1965fd653b1
https://github.com/llvm/llvm-project/commit/12d95c65fc99a3d5686f1d409572d1965fd653b1
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
R llvm/test/Transforms/LICM/vector-insert.ll
Log Message:
-----------
Revert "[LICM] Allow hoisting of InsertElementInst's past non-hoistable InsertElementInsts" (#203611)
Reverts llvm/llvm-project#200532
Commit: 0526807f89803b394fcebc87dfc234e57513986e
https://github.com/llvm/llvm-project/commit/0526807f89803b394fcebc87dfc234e57513986e
Author: Maryam Moghadas <maryammo at ca.ibm.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
A clang/test/AST/tyloctype_alignment.cpp
Log Message:
-----------
[clang][z/OS] Add test for TypeLoc tail padding alignment (#202710)
This adds a test for the TypeLoc tail padding fix that was merged in
commit 89305c3.
Commit: 5f51294647b3c4c08dfd0e455b1a997074864d26
https://github.com/llvm/llvm-project/commit/5f51294647b3c4c08dfd0e455b1a997074864d26
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaOverload.cpp
A clang/test/Sema/atomic-conversions-to-int.cpp
Log Message:
-----------
Fix contextual implicit conversions to int: with _Atomic (#203522)
PerformContextualImplicitConversion was performing
default-lvalue-conversions, then basing decisions on viable conversion
functions on this type However, when we then went to add the candidates
we were using the 'old' value (pre-conversion) of the type, resulting in
us regaining the lost 'atomic' from the default Lvalue conversion.
This patch updates the 'from' variable to be the converted value so all
conversions are done post-conversion.
Fixes: #201770
Commit: ce09519f40a6d76ec231ef8e4630c0d85c8cdaa5
https://github.com/llvm/llvm-project/commit/ce09519f40a6d76ec231ef8e4630c0d85c8cdaa5
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/test/Transforms/ConstraintElimination/geps-unsigned-predicates.ll
Log Message:
-----------
[ConstraintElim] Add test with negative offset and NUW only GEP (NFC) (#203614)
Add test currently mis-compiled with NUW only GEP.
https://alive2.llvm.org/ce/z/7G8uE3
Commit: 327ce1bb0cd56e74bfd79f51463e6c0a81905a25
https://github.com/llvm/llvm-project/commit/327ce1bb0cd56e74bfd79f51463e6c0a81905a25
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M compiler-rt/test/fuzzer/lit.cfg.py
Log Message:
-----------
[Fuzzer] Use the internal shell by default (#203450)
The external shell is going away soon and the internal shell is superior
in most ways (platform compatibility, performance, debugging). This now
causes no test failures and is blocking deprecation of the external
shell, so switch over.
Commit: b312ae01043b75637f4fd4dbaf66a09907f63c22
https://github.com/llvm/llvm-project/commit/b312ae01043b75637f4fd4dbaf66a09907f63c22
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
A llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1251_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
Log Message:
-----------
[AMDGPU] Add gfx1251 V_PK_ADD/SUB_NC_U64 (#203607)
Commit: 87d29e3f438c9c02390a4260e9a1bc7712f882c2
https://github.com/llvm/llvm-project/commit/87d29e3f438c9c02390a4260e9a1bc7712f882c2
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
Log Message:
-----------
[AMDGPU] NFC: Drop constexpr from getFlavor*Name functions (#203603)
It seems specifying these as constexpr was causing some buildbot
failures due to llvm_unreachable --
```
[1/123] Building CXX object lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o
FAILED: lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o
/usr/bin/c++ -DLLVM_EXPORTS -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GLIBCXX_USE_CXX11_ABI=1 -D_GNU_SOURCE -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_EXTENSIVE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/path/to/build.AArch64.Release.main/lib/Target/AMDGPU -I/path/to/llvm-project/llvm/lib/Target/AMDGPU -I/path/to/build.AArch64.Release.main/include -I/path/to/llvm-project/llvm/include -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror=date-time -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wno-uninitialized -Wno-nonnull -Wno-class-memaccess -Wno-array-bounds -Wno-noexcept-type -Wdelete-non-virtual-dtor -Wno-comment -Wno-misleading-indentation -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -std=c++17 -fvisibility=hidden -UNDEBUG -fno-exceptions -funwind-tables -fno-rtti -MD -MT lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o -MF lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o.d -o lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUCoExecSchedStrategy.cpp.o -c /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
In file included from /path/to/llvm-project/llvm/include/llvm/ADT/Hashing.h:49,
from /path/to/llvm-project/llvm/include/llvm/ADT/ArrayRef.h:12,
from /path/to/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNSubtarget.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNRegPressure.h:20,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h:16,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp:14:
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getFlavorName(llvm::AMDGPU::InstructionFlavor)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:67: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown InstructionFlavor");
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getFlavorShortName(llvm::AMDGPU::InstructionFlavor)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:95: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown InstructionFlavor");
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getReasonName(llvm::AMDGPU::AMDGPUSchedReason)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:142: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown AMDGPUSchedReason");
[2/123] Building CXX object lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o
FAILED: lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o
/usr/bin/c++ -DLLVM_EXPORTS -D_DEBUG -D_GLIBCXX_ASSERTIONS -D_GLIBCXX_USE_CXX11_ABI=1 -D_GNU_SOURCE -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_EXTENSIVE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/path/to/build.AArch64.Release.main/lib/Target/AMDGPU -I/path/to/llvm-project/llvm/lib/Target/AMDGPU -I/path/to/build.AArch64.Release.main/include -I/path/to/llvm-project/llvm/include -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror=date-time -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wno-uninitialized -Wno-nonnull -Wno-class-memaccess -Wno-array-bounds -Wno-noexcept-type -Wdelete-non-virtual-dtor -Wno-comment -Wno-misleading-indentation -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -std=c++17 -fvisibility=hidden -UNDEBUG -fno-exceptions -funwind-tables -fno-rtti -MD -MT lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o -MF lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o.d -o lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/AMDGPUTargetMachine.cpp.o -c /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
In file included from /path/to/llvm-project/llvm/include/llvm/ADT/Hashing.h:49,
from /path/to/llvm-project/llvm/include/llvm/ADT/ArrayRef.h:12,
from /path/to/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/GCNSubtarget.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h:17,
from /path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp:17:
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getFlavorName(llvm::AMDGPU::InstructionFlavor)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:67: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown InstructionFlavor");
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getFlavorShortName(llvm::AMDGPU::InstructionFlavor)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:95: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown InstructionFlavor");
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h: In function 'constexpr llvm::StringRef llvm::AMDGPU::getReasonName(llvm::AMDGPU::AMDGPUSchedReason)':
/path/to/llvm-project/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-'constexpr' function 'void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)'
::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/path/to/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h:142: note: in expansion of macro 'llvm_unreachable'
llvm_unreachable("Unknown AMDGPUSchedReason");
ninja: build stopped: subcommand failed.
```
See alo
(https://github.com/llvm/llvm-project/pull/192322#issuecomment-4672427400)
Commit: 3abb8d8a05a215f719cd5ebc962e5f07ffbaeaa1
https://github.com/llvm/llvm-project/commit/3abb8d8a05a215f719cd5ebc962e5f07ffbaeaa1
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
M mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
M mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp
A mlir/test/Conversion/XeGPUToXeVM/extf_truncf.mlir
M mlir/test/Conversion/XeVMToLLVM/xevm_mx-to-llvm.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/xevm.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_raw.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_bf16.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_fp4.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_fp4_bf16.mlir
Log Message:
-----------
[MLIR][XeVM] Add xevm.extf op as the inverse of xevm.truncf (#203124)
Add a new xevm.extf operation that extends f8/bf8/f4 values to f16/bf16,
mirroring the existing xevm.truncf op, together with its lowering in
XeVMToLLVM.
Lowering details (XeVMToLLVM):
- bf8/f8 -> f16 via __builtin_IB_bf8tohf_16 / __builtin_IB_hf8tohf_16.
- bf8/f8 -> bf16 via f16 -> f32 (convert_float16) -> bf16
(__builtin_IB_ftobf_16).
- e2m1 (fp4) -> f16/bf16 via __builtin_IB_shfl_idx4_lut and
__builtin_IB_shfl_idx4_to_fp16_8_packed (LUT 7 for f16, 5 for bf16).
Adds the op definition and verifier, conversion/roundtrip/invalid unit
tests, and f8 and fp4 GPU round-trip integration tests.
Adds arith.extf to xevm.extf lowering and arith.truncf to xevm.truncf
lowering in XeGPU to XeVM conversion and unit tests.
Commit: c4c30cebec281eb52e9742cfb1f892fa3c1d9624
https://github.com/llvm/llvm-project/commit/c4c30cebec281eb52e9742cfb1f892fa3c1d9624
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
M llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll
Log Message:
-----------
[SLP] Vectorize full insertvalue buildvector sequences
Treat a complete chain of insertvalue instructions building a homogeneous
literal struct from scalars as a buildvector, like insertelement sequences.
The scalars are vectorized into one vector; the aggregate is rebuilt from it
via a stack store + load, or stored directly when its only user is a store.
insertvalue is routed through the existing insertelement buildvector paths
(type/index helpers, reordering, tree build, cost model, min-bitwidth, and
codegen). Only single-index, non-vector inserts building from an undef
aggregate are handled.
Fixes #43353
Reviewers: hiraditya, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/200274
Commit: ae026a59dad1a0a59209418f7a39e16a889c8ac1
https://github.com/llvm/llvm-project/commit/ae026a59dad1a0a59209418f7a39e16a889c8ac1
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
Log Message:
-----------
[AMDGPU] Enable S_ADD_PC_I64 on gfx1251 (#203613)
Commit: 2f8a39d73394b9a50a32fed5430896afa32a06f5
https://github.com/llvm/llvm-project/commit/2f8a39d73394b9a50a32fed5430896afa32a06f5
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/test/Transforms/LoopInterchange/lcssa-incoming-value-is-not-instr.ll
Log Message:
-----------
[LoopInterchange] Fix crash when followLCSSA returns constant (#203515)
Similar as the case in ##201069, `followLCSSA` may return a constant
value, but it was cast to Instruction unconditionally. We need to
explicitly check whether the returned value is an Instruction or not.
Fix #203375.
Commit: d0cd530bf4e28732368244476c4f504a4920e6c4
https://github.com/llvm/llvm-project/commit/d0cd530bf4e28732368244476c4f504a4920e6c4
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
Log Message:
-----------
[LoopInterchange] Mark getAddRecCoefficient with static (#203624)
As this function is a file-scope non-member function, it's better to
mark it with static.
Commit: e882286f4bb9095558e9783aa79cc6ca90487bcf
https://github.com/llvm/llvm-project/commit/e882286f4bb9095558e9783aa79cc6ca90487bcf
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M bolt/lib/Profile/DataAggregator.cpp
Log Message:
-----------
[BOLT] Fix perf data return identification (#203628)
If perf data doesn't have branch type recorded, missing value would
incorrectly be interpreted as not-a-return. Only populate Returns map if
the branch type is available.
Fixes bug introduced in #202813.
Commit: 8fb9963fd4da8bc5b3b7e186cd369102f42d3640
https://github.com/llvm/llvm-project/commit/8fb9963fd4da8bc5b3b7e186cd369102f42d3640
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
A llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
A llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1251_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
Log Message:
-----------
[AMDGPU] Add gfx1251 V_PK_LSHL_ADD_U64 (#203612)
Commit: 181d8084770935e4e3cd1877d317e95b73fe8368
https://github.com/llvm/llvm-project/commit/181d8084770935e4e3cd1877d317e95b73fe8368
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/test/CodeGen/AArch64/arm64e-tail-call-autib.ll
M llvm/test/CodeGen/AArch64/pauth-lr-tail-call-fpdiff.ll
A llvm/test/CodeGen/AArch64/swifttail-ptrauth.ll
Log Message:
-----------
[AArch64][PAuth] Fix return-address auth for swifttailcc with FPDiff > 0 (#203340)
When a swifttailcc tail call has FPDiff > 0 (the caller received more
stack argument space than the callee pops), the epilogue contains an SP
adjustment to discard the leftover argument space. The existing code
treated both FPDiff < 0 and FPDiff > 0 uniformly in a single 'FPDiff !=
0' block, using AUTI[AB]1716 with a reconstructed entry-SP in x16 for
both cases.
For FPDiff < 0 (callee pops more) that reconstruction is necessary and
correct. For FPDiff > 0 it is wrong: by the time we enter the block the
post-index LDP has already adjusted SP back to the frame base, but the
'add sp, sp, #N' argument pop has not yet run. Entry SP equals the
current SP at that point, so AUTI[AB]SP would work directly, but instead
the combined block bumped SP via StackOffset::getFixed(-FPDiff) which
overshoots, and then emits AUTIA1716 with a wrong discriminator. Worse
yet, the SP restore had already been emitted *before* the auth, leaving
the live argument stack below SP and outside the red-zone during the
authentication window.
Fix by splitting the block on the sign of ArgumentStackToRestore:
* `< 0`: reconstruct entry SP in x16, save LR in x17, authenticate with
AUTI[AB]1716 (or AUTI[AB]171615 / PACM+AUTI[AB]1716 for PAuthLR).
* `> 0`: temporarily remove the 'add sp, sp, #N' SP-modifying
instructions from before the auth instruction (SPMods shuffle),
authenticate with AUTI[AB]SP (SP == entry SP at this point), then
re-insert the SP adjustment afterward.
Commit: 4c057feb7835680c39c78e826c033307bec74295
https://github.com/llvm/llvm-project/commit/4c057feb7835680c39c78e826c033307bec74295
Author: Guo Chen <guochen2 at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
A llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll
Log Message:
-----------
[AMDGPU][true16] extract 16bit for scratch_load_ubyte_st when spilling (#203589)
In sramecc mode scratch_load_ubyte_st is selected for 16bit spilling.
Need a tmp vgpr32 and extract lo16 from it
Commit: 0a6e0210df5596f4aa35b6d01d0dcedc9414dab9
https://github.com/llvm/llvm-project/commit/0a6e0210df5596f4aa35b6d01d0dcedc9414dab9
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_poison_freeze/freeze-aggregate.ll
A llvm/test/CodeGen/SPIRV/freeze-aggregate.ll
Log Message:
-----------
[SPIR-V] Lower freeze instructions with aggregate operands (#203584)
An aggregate freeze takes its result type from its operand, like a PHI
or select, but was handled by neither the up-front value-id mutation nor
replaceMemInstrUses, so the pass aborted with "illegal aggregate
intrinsic user". Mutate aggregate freezes to the i32 value-id type and
replace their operands alongside PHIs and selects.
Commit: d2163f7c0c21390190e1ccb91e61958ad6ecc9f9
https://github.com/llvm/llvm-project/commit/d2163f7c0c21390190e1ccb91e61958ad6ecc9f9
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M flang/lib/Semantics/check-cuda.cpp
M flang/test/Semantics/cuf09.cuf
Log Message:
-----------
[flang][cuda] Error out if pause statement is used in device code (#203642)
Commit: 81a81d7fae4a16e0edfdb0273f5c376547e15841
https://github.com/llvm/llvm-project/commit/81a81d7fae4a16e0edfdb0273f5c376547e15841
Author: dpalermo <dan.palermo at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
Log Message:
-----------
Revert "[AMDGPU] In `LowerDYNAMIC_STACKALLOC`, hoist the `readfirstlane` up one instruction" (#203645)
Reverts llvm/llvm-project#201528
Reverting due to change causing "illegal VGPR to SGPR copy"
Commit: c9b25a6437fd97fdb1e55ab6661c0cccce98913e
https://github.com/llvm/llvm-project/commit/c9b25a6437fd97fdb1e55ab6661c0cccce98913e
Author: Hardik Chona <iamhardikchona at gmail.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/stdlib.yaml
M libc/src/stdlib/CMakeLists.txt
A libc/src/stdlib/mkstemp.cpp
A libc/src/stdlib/mkstemp.h
M libc/test/src/stdlib/CMakeLists.txt
A libc/test/src/stdlib/mkstemp_test.cpp
Log Message:
-----------
[libc] implement mkstemp (#199220)
Fixes #191266
Implements `mkstemp` as specified in POSIX
Currently Linux-only since it relies on the Linux syscall wrappers for
`getrandom` and `open`
Commit: 92d7a7fbbd7238222d8a0ef7b85b9300f832a4d5
https://github.com/llvm/llvm-project/commit/92d7a7fbbd7238222d8a0ef7b85b9300f832a4d5
Author: vsimion26 <vlad.simion at intel.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/Quant/IR/Quant.h
M mlir/include/mlir/Dialect/Quant/IR/QuantBase.td
M mlir/include/mlir/Dialect/Quant/IR/QuantDialectBytecode.td
M mlir/lib/Dialect/Quant/IR/QuantDialectBytecode.cpp
M mlir/test/Dialect/Quant/Bytecode/types.mlir
Log Message:
-----------
QuantileType bytecode patch (#203495)
Since the merge of this
PR(https://github.com/llvm/llvm-project/pull/190321) there were some
issues identified, such as QuantileType not being added in the ByteCode
files. This PR focuses on fixing these missing pieces which should make
QuantileType a complete and functional type.
Commit: a8e3c083db160e2dc6f04b660b22b459e5167199
https://github.com/llvm/llvm-project/commit/a8e3c083db160e2dc6f04b660b22b459e5167199
Author: Schrodinger ZHU Yifan <yfzhu at google.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M libc/src/__support/threads/linux/futex_utils.h
M libc/src/__support/threads/raw_mutex.h
M libc/src/__support/threads/raw_rwlock.h
M libc/test/integration/src/__support/threads/futex_requeue_test.cpp
Log Message:
-----------
[libc] fix EAGAIN being treated as timeout in mutex and rwlock (#203574)
fix #203411.
This PR addresses the problem that `EAGAIN` may be treated as timeout in
mutex and rwlock. Two changes are applied:
1. timeout sites always explicitly check for timeout now to make the
logic more robust;
2. the futex wait now discards the error of `EAGAIN/EWOULDBLOCK` and
returns 0;
We don't distinguish waking up from signal and waking up from mismatch
for the following 3 reasons:
- We have userspace guard to avoid futex syscall if we already know
value would match, it seems awkward to make that check returns error, as
we may wake up and loop back to the check, where signal is consumed but
we still return error....;
- futex syscall can spuriously wake up anyway, there is no way to tell
whether the signal is "indeed" consumed;
- other platforms like darwin does not distinguish these states either.
Assisted-by: Gemini powered automation tools (human-in-the-loop).
Commit: baf76a838f3da5fcbb5acbdc12f57b0ed79cc3ce
https://github.com/llvm/llvm-project/commit/baf76a838f3da5fcbb5acbdc12f57b0ed79cc3ce
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/perf2bolt/perf_test.test
Log Message:
-----------
[BOLT] Change DataAggregator error types (#203651)
1. In `filterBinaryMMapInfo`, replace `incovertibleErrorCode` with errc
code as `parseMainEvents` converts returned Error to std::error_code.
2. In `parsePerfData`, pass through Error returned by `prepareToParse`
for memory events.
Test Plan: updated perf_test.test
Commit: 0a713dbb3ae777cc2260930650f96a33960a9e31
https://github.com/llvm/llvm-project/commit/0a713dbb3ae777cc2260930650f96a33960a9e31
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-06-12 (Fri, 12 Jun 2026)
Changed paths:
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/perf2bolt/perf_test.test
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Frontend/FrontendOptions.h
M clang/include/clang/Options/Options.td
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowExtractor.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/SSAFAnalysesCommon.h
M clang/lib/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageExtractor.cpp
M clang/lib/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendAction.cpp
M clang/lib/Sema/SemaLifetimeSafety.h
M clang/lib/Sema/SemaOverload.cpp
A clang/test/AST/tyloctype_alignment.cpp
M clang/test/Analysis/Scalable/PointerFlow/external-inline-function-in-multi-tu.test
M clang/test/Analysis/Scalable/call-graph.cpp
A clang/test/Analysis/Scalable/cli-errors-compilation-unit-id.cpp
M clang/test/Analysis/Scalable/command-line-interface.cpp
M clang/test/Analysis/Scalable/downgradable-errors.cpp
M clang/test/Analysis/Scalable/extraction-works-alongside-compilation.cpp
M clang/test/Analysis/Scalable/help.cpp
A clang/test/CIR/CodeGen/cxx-construct-lvalue.cpp
M clang/test/CIR/CodeGen/ternary-throw.cpp
A clang/test/CodeGen/AArch64/sme2p3-intrinsics/acle_sme2p3_luti6.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_luti6_lane_x2.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2p3.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2p3___sme_AND_LP_sve2p3_OR_sme2p3_RP.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve2p3.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme2p3.c
M clang/test/Sema/LifetimeSafety/annotation-suggestions.cpp
M clang/test/Sema/LifetimeSafety/nocfg.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
A clang/test/Sema/aarch64-sme2p3-intrinsics/acle_sme2p3_imm.c
M clang/test/Sema/aarch64-sve2p3-intrinsics/acle_sve2p3_imm.cpp
A clang/test/Sema/atomic-conversions-to-int.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Frontend/TUSummaryExtractorFrontendActionTest.cpp
M compiler-rt/lib/builtins/cpu_model/riscv/hwprobe.inc
M compiler-rt/test/fuzzer/fork-sigusr.test
M compiler-rt/test/fuzzer/lit.cfg.py
M compiler-rt/test/fuzzer/merge-sigusr.test
M compiler-rt/test/fuzzer/sigint.test
M compiler-rt/test/fuzzer/sigusr.test
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Semantics/check-cuda.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Fir/mem2reg.mlir
A flang/test/Lower/OpenACC/Todo/acc-unstructured-combined-construct.f90
A flang/test/Lower/OpenACC/Todo/acc-unstructured-loop-construct.f90
M flang/test/Lower/OpenACC/acc-unstructured.f90
M flang/test/Semantics/cuf09.cuf
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/stdlib.yaml
M libc/src/__support/threads/linux/futex_utils.h
M libc/src/__support/threads/raw_mutex.h
M libc/src/__support/threads/raw_rwlock.h
M libc/src/stdlib/CMakeLists.txt
A libc/src/stdlib/mkstemp.cpp
A libc/src/stdlib/mkstemp.h
M libc/test/integration/src/__support/threads/futex_requeue_test.cpp
M libc/test/src/stdlib/CMakeLists.txt
A libc/test/src/stdlib/mkstemp_test.cpp
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.h
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.h
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/ADT/Bitset.h
M llvm/include/llvm/ADT/StringExtras.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/IR/BundleAttributes.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/Value.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MIRPrintingPass.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/VirtRegMap.cpp
M llvm/lib/IR/BundleAttributes.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/MC/MCParser/COFFMasmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MC/MCWin64EH.cpp
M llvm/lib/Support/Win64EH.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/CodeGen/AArch64/arm64e-tail-call-autib.ll
M llvm/test/CodeGen/AArch64/ext-narrow-index.ll
M llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
M llvm/test/CodeGen/AArch64/pauth-lr-tail-call-fpdiff.ll
A llvm/test/CodeGen/AArch64/shuffle-slide-to-shift.ll
M llvm/test/CodeGen/AArch64/sme-intrinsics-mova-insert.ll
A llvm/test/CodeGen/AArch64/sme2p3-intrinsics-luti6.ll
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics-luti6.ll
A llvm/test/CodeGen/AArch64/swifttail-ptrauth.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
A llvm/test/CodeGen/AMDGPU/packed-u64.ll
A llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll
A llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
A llvm/test/CodeGen/AMDGPU/spillv16Kernel.ll
A llvm/test/CodeGen/DirectX/switch-to-lookup-table-i16-narrowing.ll
A llvm/test/CodeGen/DirectX/switch-to-lookup-table-no-i8-narrowing.ll
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-phys.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-bad-split.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash-self-split.mir
A llvm/test/CodeGen/MIR/AMDGPU/virtregmap-stash.mir
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_poison_freeze/freeze-aggregate.ll
A llvm/test/CodeGen/SPIRV/freeze-aggregate.ll
M llvm/test/CodeGen/X86/stack-coloring-setjmp.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
M llvm/test/MC/AMDGPU/gfx1251_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx1251_err.s
M llvm/test/MC/COFF/seh-unwindv3-error.s
M llvm/test/MC/COFF/seh-unwindv3-inheritance.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop3p.txt
M llvm/test/Transforms/ConstraintElimination/geps-unsigned-predicates.ll
R llvm/test/Transforms/LICM/vector-insert.ll
M llvm/test/Transforms/LoopInterchange/lcssa-incoming-value-is-not-instr.ll
A llvm/test/Transforms/LoopVectorize/RISCV/i128-trip-count-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
M llvm/test/Transforms/LoopVectorize/epilog-iv-select-cmp.ll
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
M llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
M llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll
A llvm/test/tools/llvm-diff/callsite-assumption-passing.ll
A llvm/test/tools/llvm-ml/beginepilog_error.asm
M llvm/test/tools/llvm-ml/builtin_symbols.asm
A llvm/test/tools/llvm-ml/epilog_directive_errors.asm
A llvm/test/tools/llvm-ml/epilog_directives.asm
A llvm/test/tools/llvm-ml/proc_frame_v3.asm
A llvm/test/tools/llvm-ml/prolog_directive_errors.asm
A llvm/test/tools/llvm-ml/unwindv3_required_errors.asm
M llvm/test/tools/llvm-objdump/COFF/win64-unwindv3-multi-epilog.yaml
M llvm/test/tools/llvm-readobj/COFF/unwind-x86_64-v3-multi-epilog.yaml
M llvm/tools/llvm-diff/lib/DifferenceEngine.cpp
M llvm/tools/llvm-ml/Opts.td
M llvm/tools/llvm-ml/llvm-ml.cpp
M llvm/tools/llvm-objdump/COFFDump.cpp
M llvm/tools/llvm-readobj/Win64EHDumper.cpp
M llvm/unittests/ADT/BitsetTest.cpp
M llvm/unittests/Support/GlobPatternTest.cpp
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLAttrs.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLEnums.td
M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
M mlir/include/mlir/Dialect/Quant/IR/Quant.h
M mlir/include/mlir/Dialect/Quant/IR/QuantBase.td
M mlir/include/mlir/Dialect/Quant/IR/QuantDialectBytecode.td
M mlir/include/mlir/Dialect/XeGPU/Transforms/Transforms.h
M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
M mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
M mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
M mlir/lib/Dialect/Arith/IR/ArithDialect.cpp
M mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp
M mlir/lib/Dialect/Quant/IR/QuantDialectBytecode.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Dialect/XeGPU/Utils/CMakeLists.txt
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
A mlir/test/Conversion/XeGPUToXeVM/extf_truncf.mlir
M mlir/test/Conversion/XeVMToLLVM/xevm_mx-to-llvm.mlir
M mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir
M mlir/test/Dialect/GPU/module-to-binary-rocdl.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/module-roundtrip.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Dialect/LLVMIR/xevm.mlir
M mlir/test/Dialect/Quant/Bytecode/types.mlir
M mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute-unit.mlir
M mlir/test/Dialect/XeGPU/sg-to-lane-distribute.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_raw.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_bf16.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_fp4.mlir
A mlir/test/Integration/Dialect/XeVM/GPU/xevm_truncf_extf_roundtrip_fp4_bf16.mlir
M mlir/test/Target/LLVMIR/nvvm/tensormap_replace_invalid.mlir
A mlir/test/Target/LLVMIR/rocdl-module-flags.mlir
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/petar-avramovic/pk-f64
Compare: https://github.com/llvm/llvm-project/compare/329b4840b293...0a713dbb3ae7
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