[all-commits] [llvm/llvm-project] 9196bd: [𝘀𝗽𝗿] initial version

[Alexander Richardson via All-commits]

  Branch: refs/heads/users/arichardson/spr/tablegen-support-hwmode-registers-in-compressinstemitter
  Home:   https://github.com/llvm/llvm-project
  Commit: 9196bd668372cbcb37a50ddef3389e9779b8f576
      https://github.com/llvm/llvm-project/commit/9196bd668372cbcb37a50ddef3389e9779b8f576
  Author: Alex Richardson <alexrichardson at google.com>
  Date:   2026-06-12 (Fri, 12 Jun 2026)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M clang/test/Driver/riscv-arch.c
    M clang/test/Driver/riscv-profiles.c
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoY.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td
    M llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/lib/Target/RISCV/RISCVSchedule.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/lib/TargetParser/RISCVISAInfo.cpp
    M llvm/test/CodeGen/RISCV/features-info.ll
    M llvm/test/MC/RISCV/invalid-attribute.s
    M llvm/test/MC/RISCV/rv32c-invalid.s
    M llvm/test/MC/RISCV/rv64c-invalid.s
    M llvm/test/MC/RISCV/rvc-hints-invalid.s
    A llvm/test/MC/RISCV/rvy-build-attributes.s
    A llvm/test/MC/RISCV/rvy-invalid-attributes.s
    A llvm/test/MC/RISCV/rvy/rvy-invalid-load-store.s
    A llvm/test/MC/RISCV/rvy/rvy-valid-load-store-64.s
    A llvm/test/MC/RISCV/rvy/rvy-valid-load-store.s
    A llvm/test/MC/RISCV/rvy/rvyc-invalid-load-store.s
    A llvm/test/MC/RISCV/rvy/rvyc-valid-addi.s
    A llvm/test/MC/RISCV/rvy/rvyc-valid-load-store-64.s
    A llvm/test/MC/RISCV/rvy/rvyc-valid-load-store.s
    M llvm/test/MC/RISCV/xqcibm-invalid.s
    M llvm/test/TableGen/RegClassByHwModeCompressPat.td
    A llvm/test/TableGen/RegClassByHwModeCompressPat4Modes.td
    A llvm/test/TableGen/RegClassByHwModeCompressPatError.td
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
    M llvm/utils/TableGen/Common/CodeGenHwModes.cpp
    M llvm/utils/TableGen/Common/CodeGenHwModes.h
    M llvm/utils/TableGen/Common/SubtargetFeatureInfo.cpp
    M llvm/utils/TableGen/Common/SubtargetFeatureInfo.h
    M llvm/utils/TableGen/CompressInstEmitter.cpp

  Log Message:
  -----------
  [𝘀𝗽𝗿] initial version

Created using spr 1.3.8-beta.1



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