[all-commits] [llvm/llvm-project] 9090e1: [RFC][AMDGPU] Add BARRIER address space

[Pierre van Houtryve via All-commits]

  Branch: refs/heads/users/pierre-vh/barrier-as-impl
  Home:   https://github.com/llvm/llvm-project
  Commit: 9090e13a2fead57e373c7d8158a6e22fbb5a34ee
      https://github.com/llvm/llvm-project/commit/9090e13a2fead57e373c7d8158a6e22fbb5a34ee
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2026-06-12 (Fri, 12 Jun 2026)

  Changed paths:
    M clang/lib/CodeGen/Targets/AMDGPU.cpp
    M clang/test/CodeGen/target-data.c
    M clang/test/CodeGenHIP/amdgpu-barrier-type.hip
    M clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl
    M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
    M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
    M lld/test/ELF/lto/amdgcn-oses.ll
    M lld/test/ELF/lto/amdgcn.ll
    M llvm/docs/AMDGPUUsage.rst
    M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
    M llvm/include/llvm/Support/AMDGPUAddrSpace.h
    M llvm/lib/Target/AMDGPU/AMDGPU.h
    M llvm/lib/Target/AMDGPU/AMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.h
    M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
    M llvm/lib/Target/AMDGPU/SIDefines.h
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/lib/TargetParser/TargetDataLayout.cpp
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll
    A llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-module-lds.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-sw-lds.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync.ll
    M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
    M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
    M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
    M llvm/test/CodeGen/AMDGPU/attributor-noalias-addrspace.ll
    A llvm/test/CodeGen/AMDGPU/barrier-addrspace-dereference.ll
    M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-named-barrier.ll
    M llvm/test/CodeGen/AMDGPU/lds-link-time-named-barrier.ll
    A llvm/test/CodeGen/AMDGPU/null-named-barrier-gv.ll
    A llvm/test/CodeGen/AMDGPU/s-barrier-lowering-bad-absolute-symbol.ll
    A llvm/test/CodeGen/AMDGPU/s-barrier-lowering-wrong-gv-signature.ll
    M llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
    M llvm/test/CodeGen/AMDGPU/s-barrier.ll
    M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
    M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
    M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
    M mlir/test/Dialect/LLVMIR/rocdl.mlir
    M mlir/test/Target/LLVMIR/rocdl.mlir

  Log Message:
  -----------
  [RFC][AMDGPU] Add BARRIER address space

Add a new BARRIER address space that is used for global variables that are used to represent the barrier IDs in GFX12.5.

These barrier addresses just have values corresponding 1-1 to barrier IDs. They are still implemented on top of LDS, but the offsetting happens during an addrspacecast to generic, not whenever the barrier GV is used.

The motivation for this is to make the relation between LDS and barrier GVs explicit in the compiler. It does add a bit more complexity, but that complexity was already there, just hidden by pretending barrier GVs were actual LDS.


  Commit: 3999e13756e3ccd1c00e3cbfb22f50a16e8fcac6
      https://github.com/llvm/llvm-project/commit/3999e13756e3ccd1c00e3cbfb22f50a16e8fcac6
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2026-06-12 (Fri, 12 Jun 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/s-barrier-id-allocation.ll
    M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
    M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
    M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
    M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-barriers-gfx12.mlir

  Log Message:
  -----------
  Fix MLIR


  Commit: 67aa8fa2f74d499b8410a7256f5e9e62b3f51d50
      https://github.com/llvm/llvm-project/commit/67aa8fa2f74d499b8410a7256f5e9e62b3f51d50
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2026-06-12 (Fri, 12 Jun 2026)

  Changed paths:
    M llvm/docs/AMDGPUUsage.rst
    M llvm/include/llvm/Support/AMDGPUAddrSpace.h

  Log Message:
  -----------
  Fix docs


  Commit: 85c8d8e7f7a14d9b84b7b373d5a887170817a320
      https://github.com/llvm/llvm-project/commit/85c8d8e7f7a14d9b84b7b373d5a887170817a320
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2026-06-12 (Fri, 12 Jun 2026)

  Changed paths:
    M llvm/docs/AMDGPUUsage.rst
    M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td

  Log Message:
  -----------
  Address comments, fix rebase


  Commit: a782830dcf363519fdbe525b4a88f6c644e52479
      https://github.com/llvm/llvm-project/commit/a782830dcf363519fdbe525b4a88f6c644e52479
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2026-06-12 (Fri, 12 Jun 2026)

  Changed paths:
    M llvm/docs/AMDGPUUsage.rst

  Log Message:
  -----------
  Clean-up docs


Compare: https://github.com/llvm/llvm-project/compare/b942ed2aa194...a782830dcf36

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