[all-commits] [llvm/llvm-project] 62a2af: [MLIR][NVVM] Preserve PTX special registers in inl...

[Bastian Hagedorn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 62a2af17a33394ac6f286dc110633013cb01ed7d
      https://github.com/llvm/llvm-project/commit/62a2af17a33394ac6f286dc110633013cb01ed7d
  Author: Bastian Hagedorn <bhagedorn at nvidia.com>
  Date:   2026-06-12 (Fri, 12 Jun 2026)

  Changed paths:
    M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
    M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir

  Log Message:
  -----------
  [MLIR][NVVM] Preserve PTX special registers in inline_ptx lowering (#203251)

`PtxBuilder::build()` converted operand placeholders (written as %0, %1,
and the predicate as @%N, since TableGen string attributes cannot
contain '$') to the inline-asm operand form with a blanket `replace(ptx,
'%', '$')`. That also rewrote literal PTX special-register names such as
%tid.x, %laneid and %dynamic_smem_size into $tid.x etc., producing
invalid PTX for any `nvvm.inline_ptx` whose body reads a special
register.

Convert only a '%' that is immediately followed by a digit (operand
placeholders and the @%N predicate); leave %<name> special registers
intact. PTX special registers always begin with a letter after '%', so
the digit test unambiguously distinguishes them from operand
placeholders.

Add an NVVMToLLVM regression test that reads %laneid through
nvvm.inline_ptx.

Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>



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