[all-commits] [llvm/llvm-project] 74abe8: [RISCV][CHERIoT] Define ABI_CHERIOT. (#192929)

[Owen Anderson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 74abe832e849c73798589a1eb1ed0f8ae576f07e
      https://github.com/llvm/llvm-project/commit/74abe832e849c73798589a1eb1ed0f8ae576f07e
  Author: Owen Anderson <resistor at mac.com>
  Date:   2026-06-11 (Thu, 11 Jun 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
    M llvm/test/MC/RISCV/target-abi-invalid.s
    M llvm/test/MC/RISCV/target-abi-valid.s

  Log Message:
  -----------
  [RISCV][CHERIoT] Define ABI_CHERIOT. (#192929)

These correspond to the CHERIoT ABI, documented here:
https://github.com/CHERIoT-Platform/cheriot-sail/releases/download/v1.0/cheriot-architecture-v1.0.pdf
In particular, CHERIoT is an RV32E-based architecture extended with
CHERI support that is not binary compatible with the proposed RV Y base.
Amongst other changes, it has customized calling conventions, such as
passing f64 in capability registers.



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