[all-commits] [llvm/llvm-project] b65e7e: [Xtensa] Fix code generation for TLS variables. (#...
Ryotaro Kasuga via All-commits
all-commits at lists.llvm.org
Thu Jun 11 04:32:15 PDT 2026
Branch: refs/heads/users/kasuga-fj/loop-interchange-add-test-inner-inductions
Home: https://github.com/llvm/llvm-project
Commit: b65e7e4918341fc9007bdf48e3098046ff13078f
https://github.com/llvm/llvm-project/commit/b65e7e4918341fc9007bdf48e3098046ff13078f
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
A llvm/test/CodeGen/Xtensa/tls.ll
A llvm/test/MC/Xtensa/tls.s
Log Message:
-----------
[Xtensa] Fix code generation for TLS variables. (#202822)
This MR fixes https://github.com/llvm/llvm-project/issues/190202
Commit: 9347582fd312afe51b2ac3eb436d6d5d6bb6d2a3
https://github.com/llvm/llvm-project/commit/9347582fd312afe51b2ac3eb436d6d5d6bb6d2a3
Author: Igor Wodiany <igor.wodiany at amd.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/TableGen/GlobalISelEmitter/SkippedPatterns.td
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[GlobalISel] Remove `fp_to_[s/u]int_sat_gi` node (#202908)
Instead of having a separate node reuse `fp_to_[s/u]int_sat`
but drop the saturation width from it.
Assisted-by: Claude Code
Commit: 34a321a74fdf87c3e3f5e80d95d581629513441d
https://github.com/llvm/llvm-project/commit/34a321a74fdf87c3e3f5e80d95d581629513441d
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions-interleave.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-saddsatcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-selectandorcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/pointer_iv.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-fold-multiple-icmps.ll
Log Message:
-----------
[LV][NFC] Remove instcombine pass from RUN lines in ARM tests (#202913)
Following on from PR #197448 I've now removed the instcombine pass from
RUN lines in the ARM test directory, which exposes some potential
missing optimisations in vplan:
1. We could be folding IR into saturating math intrinsic calls to better
reflect the cost.
2. Masked load + select -> masked load with different passthru.
3. icmp + select -> smin/smax.
Some of these were already observed in #197448
Commit: 9ebbc1e089d64e717b3285ec463b92f94e7f55dc
https://github.com/llvm/llvm-project/commit/9ebbc1e089d64e717b3285ec463b92f94e7f55dc
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/ADT/APInt.h
M llvm/lib/Support/APInt.cpp
M llvm/unittests/ADT/APIntTest.cpp
Log Message:
-----------
[APInt] Provide sqrtFloor (floor of square root) instead of sqrt (rounded) (#197406)
This simplifies both the implementation and the only in-tree user.
I changed the name to avoid silently changing the behavour of an
existing function that might have out-of-tree users.
Commit: 7e6f2b798cb97d46f395dc79b9b27961dc546cca
https://github.com/llvm/llvm-project/commit/7e6f2b798cb97d46f395dc79b9b27961dc546cca
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for set_inactive intrinsics (#203047)
Commit: 123078c21cfbe4c6abe1052e53739f9e933e8c1d
https://github.com/llvm/llvm-project/commit/123078c21cfbe4c6abe1052e53739f9e933e8c1d
Author: Gil Rapaport <gil.rapaport at mobileye.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M mlir/include/mlir/Conversion/ConvertToEmitC/ConvertToEmitCPatternInterface.td
M mlir/include/mlir/Conversion/ConvertToEmitC/ToEmitCInterface.h
M mlir/include/mlir/Conversion/FuncToEmitC/FuncToEmitC.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/lib/Conversion/ArithToEmitC/ArithToEmitC.cpp
M mlir/lib/Conversion/ConvertToEmitC/ConvertToEmitCPass.cpp
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitCPass.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
M mlir/test/Conversion/FuncToEmitC/func-to-emitc-failed.mlir
M mlir/test/Conversion/FuncToEmitC/func-to-emitc.mlir
M mlir/test/Target/Cpp/func.mlir
Log Message:
-----------
Reland emitc lower multi return functions (#203026)
Reland #200659 reverted by #202911.
Fixed GCC 7 func-to-emitc build: Use the adaptor operand types
when creating the multi-return struct type instead of relying on an
implicit conversion from ValueRange to TypeRange.
Failed buildbot:
https://lab.llvm.org/buildbot/#/builders/116/builds/29302
Assisted-by: Copilot
Commit: 67d211a220e79636cdef7667b1c429cb4fbd7660
https://github.com/llvm/llvm-project/commit/67d211a220e79636cdef7667b1c429cb4fbd7660
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M mlir/lib/Conversion/ComplexToSPIRV/ComplexToSPIRV.cpp
M mlir/test/Conversion/ComplexToSPIRV/complex-to-spirv.mlir
Log Message:
-----------
[mlir][SPIR-V] Convert complex.neg and complex.conj in ComplexToSPIRV (#202898)
Commit: 5e7ec28c5e3a70588bbe9368d3816b009cf3670f
https://github.com/llvm/llvm-project/commit/5e7ec28c5e3a70588bbe9368d3816b009cf3670f
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon-misc.c
A clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
Log Message:
-----------
[clang][CIR][AArch64] Add lowering for conversion intrinsics (#199990)
This PR adds lowering for intrinsic from the following groups:
* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions
* https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions-2
It continues the work started in #190961 and #193273. This PR implements
conversions from FP to integer types where the bit-wdith does not
change:
* vcvt_s64_f64
* vcvt_u64_f64
* vcvt_s32_f32
* vcvtq_s32_f32
* vcvtq_s64_f64
* vcvt_u32_f32
* vcvtq_u32_f32
* vcvtq_u64_f64
* vcvt_s16_f16
* vcvtq_s16_f16
* vcvt_u16_f16
* vcvtq_u16_f16
The corresponding tests are moved from:
* clang/test/CodeGen/AArch64/
to:
* clang/test/CodeGen/AArch64/neon/
The lowering follows the existing implementation in
CodeGen/TargetBuiltins/ARM.cpp.
Commit: 046bd54d17a057fdf344889f8e4b1b8e6d850dd7
https://github.com/llvm/llvm-project/commit/046bd54d17a057fdf344889f8e4b1b8e6d850dd7
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/test/CodeGen/RISCV/add-before-shl.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
M llvm/test/CodeGen/RISCV/machine-pipeliner.ll
M llvm/test/CodeGen/RISCV/nontemporal.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
M llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/RISCV/select-cc.ll
M llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
Log Message:
-----------
[RISCV] Set CostPerUse to 1 only when optimizing for size (#201501)
We saw some regressions because of bad RAs as the cost of registers
beyond x8-x15 are bigger. This is why `DisableCostPerUse` was added
in https://github.com/llvm/llvm-project/issues/83320.
In this PR, we change it to set `CostPerUse=1` only when optimizing
for size.
Code size increases less than 0.1% in llvm-test-suite.
Commit: 700ff25b03ec747784f1e6a92e076ee009db37aa
https://github.com/llvm/llvm-project/commit/700ff25b03ec747784f1e6a92e076ee009db37aa
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M libcxx/include/thread
Log Message:
-----------
[libc++] Hoist <compare> outside the threads guard in <thread> (#202535)
The standard mandates [thread.syn] include <compare> as part of
<thread>'s synopsis. This is a standards-mandated dependency, not a
thread-feature dependency, so it should be visible regardless of
_LIBCPP_HAS_THREADS.
This matches how we handle standard-mandated includes elsewhere, see for
example #134877.
Commit: b836063bbf6f856c85801e40e31e8221f240653d
https://github.com/llvm/llvm-project/commit/b836063bbf6f856c85801e40e31e8221f240653d
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
Log Message:
-----------
[LoopFusion] Drop duplicate write-write dependence check (NFC) (#203173)
`dependencesAllowFusion()` re-tested every FC0-write vs FC1-write pair
in the second loop nest, duplicating the checks already done in the
first. Iterate only the remaining FC0-read vs FC1-write pairs; the set
of checked dependences (W0xW1, W0xR1, R0xW1) is unchanged.
Commit: 8210a58044d1e6d86473fdf810396d285c86ff36
https://github.com/llvm/llvm-project/commit/8210a58044d1e6d86473fdf810396d285c86ff36
Author: Fabrice de Gans <Steelskin at users.noreply.github.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M libcxxabi/src/demangle/Utility.h
M llvm/include/llvm/Demangle/DemangleConfig.h
M llvm/include/llvm/Demangle/Utility.h
Log Message:
-----------
[Demangle] Guard DEMANGLE_ABI and add missing annotation (#202920)
This updates the DEMANGLE_ABI annotation to only be defined if it is not
already defined. This is required to parse the Demangle headers with the
ids-check script.
In addition, this adds one missing DEMANGLE_ABI annotation.
This effort is tracked in #109483.
Commit: 0cce78251f4c534b0d0a5ad55dd470e101ea9b94
https://github.com/llvm/llvm-project/commit/0cce78251f4c534b0d0a5ad55dd470e101ea9b94
Author: Tim Besard <tim.besard at gmail.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/test/CodeGen/SPIRV/select-aggregate.ll
A llvm/test/CodeGen/SPIRV/select-composite-constant.ll
Log Message:
-----------
[SPIR-V] Lower `select` instructions with aggregate operands (#201417)
Context: `SPIRVEmitIntrinsics` represents aggregate (array/struct) SSA
values as i32 value-ids, keeping the real type on the side for SPIR-V
emission. `preprocessCompositeConstants()` rewrites composite constant
operands into those value-ids.
A `select` takes its result type from its operands, so rewriting one arm
leaves the select with an aggregate result type but an i32 operand,
which is invalid. The exact failure mode depends: a composite-constant
arm tripped the verifier ("Select values must have same type as select
instruction"), while a non-constant arm (say a load) only became a
value-id later, in the visitor pass, at which point
`replaceMemInstrUses()` found a `select` among its users and hit an
unreachable.
I pushed two commits fixing this, one limited to my use case, another
more general:
1. Constant arms only. The common case is a select between two composite
constants, such as two complex literals. Once both arms are value-ids,
mutate the select to i32 and record its real type in `AggrConstTypes`;
the existing visitor turns its `extractvalue` users into `spv_extractv`.
2. An arm can also be a load or `insertvalue` result, which only becomes
a value-id later, in the visitor pass. By then the select has already
been mutated to i32, so its operand has to be reconciled when the arm is
lowered. This commit makes `select` behave like `PHINode` (which already
handles this): mutate every aggregate select to i32 up front, and handle
`SelectInst` in `replaceMemInstrUses()` so the operand and its
`extractvalue` users get fixed up as each arm is lowered. Nested
aggregate selects fall out of the same up-front mutation.
Developed with the help of Claude 4.8.
Closes https://github.com/llvm/llvm-project/issues/151344
---------
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: 4b3deaeb0d85fda9f6eee73f65f0be16b0e00698
https://github.com/llvm/llvm-project/commit/4b3deaeb0d85fda9f6eee73f65f0be16b0e00698
Author: Sven van Haastregt <sven.vanhaastregt at arm.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/unittests/DebugInfo/PDB/CMakeLists.txt
Log Message:
-----------
Fix DebugInfo unittests shared library build (#202943)
Fixes: `PublicsStreamTest.cpp.o: undefined reference to symbol
'_ZN4llvm6object18GenericBinaryErrorC1ERKNS_5TwineENS0_12object_errorE'`
under `BUILD_SHARED_LIBS=1`.
Commit: 9673aae1fc67abcab756ed3f6e36dff846e8228c
https://github.com/llvm/llvm-project/commit/9673aae1fc67abcab756ed3f6e36dff846e8228c
Author: khaki3 <47756807+khaki3 at users.noreply.github.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M flang/lib/Lower/PFTBuilder.cpp
A flang/test/Lower/OpenACC/acc-declare-interface-body.f90
Log Message:
-----------
[flang][OpenACC] Don't hoist declare directive out of interface bodies (#202806)
Example:
```fortran
program main
real :: a(10, 60)
interface
subroutine compute(a)
real :: a(10, 60)
!$acc declare present(a)
end subroutine
end interface
call compute(a)
end program
```
In this code, the `!$acc declare` inside the interface body is hoisted
into the
host program unit and lowered there, where its operand (the interface
dummy)
has no IR value, so lowering aborts with "symbol is not mapped to any IR
value".
This happens because interface-body procedures are not function-like
units, so
the directive is appended to the enclosing unit's evaluation list.
Fix: track interface-body nesting in the PFT builder and do not add an
`OpenACCDeclarativeConstruct` to the enclosing unit's evaluation list
while
inside one. The directive is no longer hoisted out and is generated only
in its
proper scope (the procedure definition or a module-level declare).
Commit: 8acfc364e9f788367ff0beab5c76a3527a689a0b
https://github.com/llvm/llvm-project/commit/8acfc364e9f788367ff0beab5c76a3527a689a0b
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M libc/include/arpa/inet.yaml
A libc/include/htons-family.yaml
M libc/include/netinet/in.yaml
M libc/utils/docgen/netinet/in.yaml
Log Message:
-----------
[libc] Add the htons function family to netinet/in.h (#203028)
As required by POSIX.
I've used the merge_yaml_files functionality to avoid duplication.
Assisted by Gemini.
Commit: f5bf584afaaf0549fbf5d645298ff5a3bea31b96
https://github.com/llvm/llvm-project/commit/f5bf584afaaf0549fbf5d645298ff5a3bea31b96
Author: Konstantin Belochapka <konstantin.belochapka at sony.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/test/Driver/ps5-linker.c
Log Message:
-----------
[clang][PS5] Clang driver PS5 - pass the target CPU to lld. (#202924)
Forward the PS5 target CPU from the clang driver to lld as
`-plugin-opt=mcpu=znver2`, matching behavior of other platforms.
Most drivers call addLTOOptions to include LTO-related link options. That includes specifying mcpu. The PS5 driver doesn't yet call addLTOOptions. In time I hope we'll arrive at a point where we can refactor to use the same functionality. This is one step towards that.
---------
Co-authored-by: Edd Dawson <edd.dawson at sony.com>
Commit: b01d0342c129405c30947f459cf055bbe8846974
https://github.com/llvm/llvm-project/commit/b01d0342c129405c30947f459cf055bbe8846974
Author: jay0x <90309873+blazie2004 at users.noreply.github.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/check-call.h
M flang/lib/Semantics/expression.cpp
A flang/test/Semantics/call47.f90
Log Message:
-----------
[Flang] Reject keyword arguments in statement function calls (#198610)
**Problem**
Flang silently accepted keyword arguments in calls to statement
functions, violating F2018 C1535.
**Standard: F2018 §15.5.1 C1535**: In a reference to a procedure whose
interface is implicit at the point of the reference, the actual argument
shall not be a keyword argument.
Flang silently compiles the following code without giving error` Keyword
argument 'x' at (1) is invalid in a statement function
`
```
program test
integer :: f1, x, c
f1(x) = x / 2
c = f1(x=10) ! Should be an error
end program
```
**Summary**
Fixed an issue where statement functions were incorrectly treated as
having an explicit interface, causing argument checks to be skipped.
Now, statement functions are marked correctly so existing checks run and
proper errors are shown
**Fixes** : [198523](https://github.com/llvm/llvm-project/issues/198523)
---------
Co-authored-by: Jay Satish Kumar Patel <kumarpat at pe31.hpc.amslabs.hpecorp.net>
Commit: 076a0a3aacca9c01ca8b6602589752d28e5dbf38
https://github.com/llvm/llvm-project/commit/076a0a3aacca9c01ca8b6602589752d28e5dbf38
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
Log Message:
-----------
[flang][OpenMP] Move TargetOMPContext to shared FlangOMPContext (NFC) (#202677)
Moving the class to shared code makes it available for reuse by
forthcoming DECLARE VARIANT lowering without any functional change to
existing metadirective lowering.
Commit: ed29c68bbdf52f377120817b7a371f5ba641b0d0
https://github.com/llvm/llvm-project/commit/ed29c68bbdf52f377120817b7a371f5ba641b0d0
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M libc/fuzzing/CMakeLists.txt
A libc/fuzzing/arpa/CMakeLists.txt
A libc/fuzzing/arpa/inet/CMakeLists.txt
A libc/fuzzing/arpa/inet/inet_aton_differential_fuzz.cpp
Log Message:
-----------
[libc] Add a differential fuzzer for inet_aton (#200341)
Commit: 8bb9b2ec2274f607151b18cecefd09252110fe37
https://github.com/llvm/llvm-project/commit/8bb9b2ec2274f607151b18cecefd09252110fe37
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
A llvm/test/Analysis/CostModel/AArch64/sve-vector-reduce-fp.ll
Log Message:
-----------
[LLVM][CostModel][SVE] Return InvalidCost for bfloat scalable vector ordered arithmetic reductions. (#202569)
Commit: e95871719c41a8de96b438b962ed3b8f869b9e0c
https://github.com/llvm/llvm-project/commit/e95871719c41a8de96b438b962ed3b8f869b9e0c
Author: Luke Lau <luke at igalia.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Recalculate VPDT in handleUncountableExitsWithSideEffects (#203233)
In the loop before we're modifying the CFG, but this invalidates the
dominator tree. We need to recalculate since we query it later on. I
can't really think of a test case for this, if anything using the
stale dominator tree with the extra branch will make the dominance
queries more conservative. But it's probably something we should fix.
Commit: d6d808f4a28b53e96eb98a2dc2f539c1ae654670
https://github.com/llvm/llvm-project/commit/d6d808f4a28b53e96eb98a2dc2f539c1ae654670
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-11 (Thu, 11 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon-misc.c
A clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
M clang/test/Driver/ps5-linker.c
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/lib/Lower/PFTBuilder.cpp
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/check-call.h
M flang/lib/Semantics/expression.cpp
A flang/test/Lower/OpenACC/acc-declare-interface-body.f90
A flang/test/Semantics/call47.f90
M libc/fuzzing/CMakeLists.txt
A libc/fuzzing/arpa/CMakeLists.txt
A libc/fuzzing/arpa/inet/CMakeLists.txt
A libc/fuzzing/arpa/inet/inet_aton_differential_fuzz.cpp
M libc/include/arpa/inet.yaml
A libc/include/htons-family.yaml
M libc/include/netinet/in.yaml
M libc/utils/docgen/netinet/in.yaml
M libcxx/include/thread
M libcxxabi/src/demangle/Utility.h
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/ADT/APInt.h
M llvm/include/llvm/Demangle/DemangleConfig.h
M llvm/include/llvm/Demangle/Utility.h
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Support/APInt.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.cpp
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
A llvm/test/Analysis/CostModel/AArch64/sve-vector-reduce-fp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.chain.arg.ll
M llvm/test/CodeGen/RISCV/add-before-shl.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
M llvm/test/CodeGen/RISCV/machine-pipeliner.ll
M llvm/test/CodeGen/RISCV/nontemporal.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
M llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/RISCV/select-cc.ll
M llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
A llvm/test/CodeGen/SPIRV/select-aggregate.ll
A llvm/test/CodeGen/SPIRV/select-composite-constant.ll
A llvm/test/CodeGen/Xtensa/tls.ll
A llvm/test/MC/Xtensa/tls.s
M llvm/test/TableGen/GlobalISelEmitter/SkippedPatterns.td
M llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions-interleave.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-saddsatcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-selectandorcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/pointer_iv.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-fold-multiple-icmps.ll
M llvm/unittests/ADT/APIntTest.cpp
M llvm/unittests/DebugInfo/PDB/CMakeLists.txt
M llvm/utils/TableGen/GlobalISelEmitter.cpp
M mlir/include/mlir/Conversion/ConvertToEmitC/ConvertToEmitCPatternInterface.td
M mlir/include/mlir/Conversion/ConvertToEmitC/ToEmitCInterface.h
M mlir/include/mlir/Conversion/FuncToEmitC/FuncToEmitC.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/lib/Conversion/ArithToEmitC/ArithToEmitC.cpp
M mlir/lib/Conversion/ComplexToSPIRV/ComplexToSPIRV.cpp
M mlir/lib/Conversion/ConvertToEmitC/ConvertToEmitCPass.cpp
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitCPass.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
M mlir/test/Conversion/ComplexToSPIRV/complex-to-spirv.mlir
M mlir/test/Conversion/FuncToEmitC/func-to-emitc-failed.mlir
M mlir/test/Conversion/FuncToEmitC/func-to-emitc.mlir
M mlir/test/Target/Cpp/func.mlir
Log Message:
-----------
Merge branch 'main' into users/kasuga-fj/loop-interchange-add-test-inner-inductions
Compare: https://github.com/llvm/llvm-project/compare/c1e628a7eb3d...d6d808f4a28b
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