[all-commits] [llvm/llvm-project] 1f5aee: [DAG] Narrow vselect mask to vXi1 in foldToMaskedS...

[Feng Zou via All-commits]

  Branch: refs/heads/release/22.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 1f5aee55a3fc26c87fc689011053d8069dd3d849
      https://github.com/llvm/llvm-project/commit/1f5aee55a3fc26c87fc689011053d8069dd3d849
  Author: Feng Zou <feng.zou at intel.com>
  Date:   2026-06-10 (Wed, 10 Jun 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    A llvm/test/CodeGen/X86/avx512-maxnum-minnum-masked-store.ll

  Log Message:
  -----------
  [DAG] Narrow vselect mask to vXi1 in foldToMaskedStore (#201609)

foldToMaskedStore (added in
https://github.com/llvm/llvm-project/commit/1c0ac80d4a9ef6c21914f2317003979952c2a2c3)
rewrites
  store(vselect(cond, x, load(ptr)), ptr) -> masked_store(x, ptr, cond)
passing the vselect condition straight through as the store mask. A
masked
store follows the IR convention of a vXi1 mask, but the condition can be
a
wider boolean vector. On AVX512F targets without VLX, a maxnum/minnum
store-back lowers the NaN test with a legacy packed (CMPP) comparison
whose
result is a vXi32/vXi64 vector, so the masked store is created with a
wide
mask and LowerMSTORE asserts:

  Assertion `Mask.getSimpleValueType().getScalarType() == MVT::i1 &&
             "Unexpected mask type"' failed.

When the matching vXi1 type is legal, narrow the mask to it before
building
the masked store. Targets where vXi1 is illegal (e.g. AVX/AVX2) keep the
wide
mask and continue to lower it as a blend/vmaskmov, and targets whose
vselect
condition is already vXi1 (e.g. AArch64 SVE, RISC-V RVV) are unaffected.

This fixes the crash at the source and lets the X86 LowerMSTORE keep its
invariant of only ever seeing a vXi1 mask (no target-specific
workaround).

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
(cherry picked from commit e6bd7887070e92bba3615de04d3fdefde4beb2de)



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