[all-commits] [llvm/llvm-project] b6e563: [VPlan] Add LLVM_ABI_FOR_TEST to classes/structs u...
Krzysztof Parzyszek via All-commits
all-commits at lists.llvm.org
Wed Jun 10 05:23:07 PDT 2026
Branch: refs/heads/users/kparzysz/resolve-declare-target
Home: https://github.com/llvm/llvm-project
Commit: b6e563e628cf1a95a153b8632f0c4fbd4cd56760
https://github.com/llvm/llvm-project/commit/b6e563e628cf1a95a153b8632f0c4fbd4cd56760
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanValue.h
Log Message:
-----------
[VPlan] Add LLVM_ABI_FOR_TEST to classes/structs used by tests (NFC). (#202400)
Add LLVM_ABI_FOR_TEST to classes that are used in unittests, either
directly or by one of their subclasses.
Should hopefully fix visability issue in
https://lab.llvm.org/buildbot/#/builders/160/builds/39088
Commit: bd630c6390f631ba4d7adf0244340a2de253f189
https://github.com/llvm/llvm-project/commit/bd630c6390f631ba4d7adf0244340a2de253f189
Author: TPPPP <TPPPP72 at outlook.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/Expr.cpp
M clang/test/Sema/warn-alloc-size.c
Log Message:
-----------
[Clang] Fixed an assertion when ``__attribute__((alloc_size))`` is ued with an argument type wider than the target's pointer width (#202381)
Replace `zext()` with `extOrTrunc()` when normalizing the `APInt` value
to `BitsInSizeT`.
fixes #190445
Commit: 3136d62938e8cb8ac3ca735d7db741a0c0d11521
https://github.com/llvm/llvm-project/commit/3136d62938e8cb8ac3ca735d7db741a0c0d11521
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/tsd_shared.h
Log Message:
-----------
[scudo] Remove locks from getTSDAndLockSlow (#201960)
Change the name of getTSDAndLockSlow to getTSDLockSlow and remove all
locks in favor of using atomic variables. Continue to lock when changing
the number of shared TSDs.
This change will remove thread contention and avoid blocking between
threads when this function is called.
Commit: 68ce9d311c8557a22005f676b1fb93a1bf87aefd
https://github.com/llvm/llvm-project/commit/68ce9d311c8557a22005f676b1fb93a1bf87aefd
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
Log Message:
-----------
[AArch64][TTI] Allow mixed-extension partial reductions with +dotprod (#199762)
With the backend now lowering SUMLA via two udot products on targets
that have +dotprod (#199761), lower the cost on targets without +i8mm.
PR: https://github.com/llvm/llvm-project/pull/199762
Commit: 5d2cc4dc1742d7373f0c52a0a29dcc5ab97a4446
https://github.com/llvm/llvm-project/commit/5d2cc4dc1742d7373f0c52a0a29dcc5ab97a4446
Author: lntue <lntue at google.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M libc/src/__support/math/cos.h
M libc/src/__support/math/sin.h
Log Message:
-----------
[libc][math] Improve the performance of sin/cos for small inputs |x| < 2^-4. (#201748)
- Use a degree-9 polynomial for fast path for sin(x), generated by Sollya,
with errors bounded by `|x| * 2^-68 + 2* ulp(x^3 / 6)`.
- Use a degree-8 polynomial for fast path for cos(x), generated by Sollya,
with errors bounded by `2^-69 + ulp(x^2/ 2 )`.
Commit: 50088e227544f2e6fe54dae54c57e3fd51623111
https://github.com/llvm/llvm-project/commit/50088e227544f2e6fe54dae54c57e3fd51623111
Author: Jameson Nash <vtjnash at gmail.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M .github/workflows/release-doxygen.yml
M bolt/docs/CMakeLists.txt
M bolt/docs/doxygen.cfg.in
M clang-tools-extra/docs/CMakeLists.txt
M clang-tools-extra/docs/doxygen.cfg.in
M clang/docs/CMakeLists.txt
M clang/docs/doxygen.cfg.in
M cmake/Modules/HandleDoxygen.cmake
M flang/docs/CMakeLists.txt
M flang/docs/doxygen.cfg.in
M lldb/docs/CMakeLists.txt
M lldb/docs/doxygen.cfg.in
M llvm/docs/CMakeLists.txt
M llvm/docs/doxygen.cfg.in
M mlir/docs/CMakeLists.txt
M mlir/docs/doxygen.cfg.in
M openmp/docs/CMakeLists.txt
M openmp/docs/doxygen.cfg.in
M polly/docs/CMakeLists.txt
M polly/docs/doxygen.cfg.in
Log Message:
-----------
Revert "[docs] update CI to use latest release of doxygen" (#202412)
Reverts llvm/llvm-project#191501 as cmake CI is having an issue with it:
```
-- Doxygen enabled (1.14.0).
CMake Error at /work/as-worker-4/publish-doxygen-docs/llvm-project/cmake/Modules/HandleDoxygen.cmake:29 (add_custom_target):
add_custom_target cannot create target "doxygen" because another target
with the same name already exists. The existing target is a custom target
created in source directory
"/work/as-worker-4/publish-doxygen-docs/llvm-project/llvm". See
documentation for policy CMP0002 for more details.
Call Stack (most recent call first):
docs/CMakeLists.txt:59 (include)
```
Commit: 68f38db0720ce3f663a5856a8b64647c25b5d1bf
https://github.com/llvm/llvm-project/commit/68f38db0720ce3f663a5856a8b64647c25b5d1bf
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/test/TableGen/switch.td
Log Message:
-----------
[TableGen] Add list value test for switch(NFC) (#202327)
Commit: 2af629d7874007bef7f9ae03027bab4a8abfcde2
https://github.com/llvm/llvm-project/commit/2af629d7874007bef7f9ae03027bab4a8abfcde2
Author: Alex Langford <alangford at apple.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M lldb/tools/lldb-dap/JSONUtils.cpp
Log Message:
-----------
[lldb] Fixup address in JSONUtils::ValuePointsToCode (#201951)
On platforms with metadata in pointers (i.e. arm64e), the address must
be fixed up before requesting a load address.
This fixes TestDAP_evaluate.py for arm64e.
Commit: e7e5bb5e7bd81508b616c50ee9086f5646b2bc0f
https://github.com/llvm/llvm-project/commit/e7e5bb5e7bd81508b616c50ee9086f5646b2bc0f
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
A llvm/test/CodeGen/AArch64/misched-fusion-aes-post-ra.mir
M llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
Log Message:
-----------
[AArch64][MacroFusion] Fuse only tied AES pairs post-RA (#201610)
This patch adds an ad-hoc check to macro fusion to only fuse AES pairs
that are tied post-RA as a guardrail.
Currently, ISel captures every RAW dependent AESE/D+AES[I]MC pair (by
data-dependence DAG), and applies a constraint that the pair must write
to the same dest, i.e the second instruction is tied (a thing that
cannot be expressed in SSA IR). So this is effectively a NFC in that
perspective, as AES is not really being lowered through other paths.
Here we add an appropriate check to macro fusion, if registers are
physical, to avoid pre-RA regression (maintaining the current status
where pre-RA fusion hides theoretical better schedules even if the pari
is not tied). Otherwise the tests in
llvm/test/CodeGen/AArch64/misched-fusion-aes.ll may not catch an ISel
change that would happen to pass, satisfying the register allocation
being filechecked.
If it appears in the future that a subtarget can fuse untied pairs, we
should re-address and maybe distinguish 2 subtarget features for the 2
cases.
Plus adding a test runline for latest apple-m5.
First attempt: https://github.com/llvm/llvm-project/pull/196484
Commit: ad33f2dd52e755506852ac220be7f113e4f3b1a3
https://github.com/llvm/llvm-project/commit/ad33f2dd52e755506852ac220be7f113e4f3b1a3
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/assume-align.ll
M llvm/test/Transforms/InstCombine/assume.ll
Log Message:
-----------
[InstCombine] Drop non-power-of-two alignment assumptions (#202396)
These assumptions aren't actually used anywhere, so we might as well
drop them. We might want consider emitting an assumption that the value
is zero at some point, but we don't have the bundles for that currently
and it seems rather low priority.
Commit: fffc591d831ace2fb4da53c5bdb7c44dac810ccb
https://github.com/llvm/llvm-project/commit/fffc591d831ace2fb4da53c5bdb7c44dac810ccb
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilderClang.cpp
A lldb/test/Shell/SymbolFile/NativePDB/invalid-type-refs.yaml
Log Message:
-----------
[lldb][NativePDB] Handle invalid type references gracefully (#202371)
Incrementally linked PDBs can contain semantically incorrect references
to types from the symbol streams and the IPI stream.
I can't reproduce it reliably, but as mentioned in #200452, at some
point the references become incorrect.
We should not crash if we receive such PDBs as input. Here I noticed two
issues:
1. `CVTagRecord` requires the passed type to be a type record
(union/struct/class). We should check that this is the case with
`IsTagRecord`.
2. After casting the return of `GetOrCreateClangType`, check that it's
the expected type (not null).
I added a test for both cases.
Commit: 3ca5b7dc4f50f5e1af51f25c2575c8fa509c24b7
https://github.com/llvm/llvm-project/commit/3ca5b7dc4f50f5e1af51f25c2575c8fa509c24b7
Author: David Justo <david.justo.1996 at gmail.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
Log Message:
-----------
[ASan] add pattern 'cmp BYTE PTR [rdx], XX' to win instruction decoder (#202407)
**Context:** The ASan instruction decoder in `interception_win.cpp` has
a manual case-based list for each instruction pattern we expect to see
in function prologues.
Today, we have an instruction decoder for `cmp BYTE PTR [rcx], XX`, but
we do not have the equivalent for `cmp BYTE PTR [rdx], XX`. In recent
builds of Windows, that latter is now seen in `ucrtbase!strstr`.
**This PR** adds the missing case.
Commit: d15d95d3ce5b0d52ec0f19c5dfabb490211d06c3
https://github.com/llvm/llvm-project/commit/d15d95d3ce5b0d52ec0f19c5dfabb490211d06c3
Author: lntue <lntue at google.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M .github/workflows/libc-shared-tests.yml
Log Message:
-----------
[libc] Add gcc-12-arm-linux-gnueabihf to libc-shared-tests CI. (#202421)
To prevent regression for arm-linux-gnueabihf target. See
https://github.com/llvm/llvm-project/issues/201678
Commit: 6c6338b3438704cddc1cf3bc6676316856b64907
https://github.com/llvm/llvm-project/commit/6c6338b3438704cddc1cf3bc6676316856b64907
Author: Alexey Bader <alexey.bader at intel.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
M llvm/lib/Frontend/Offloading/ArchiveLinker.cpp
Log Message:
-----------
[Frontend][Offloading] Restore silent ignore for non-existing input files in nvlink (#202352) (#202403)
Partially revert commit
https://github.com/llvm/llvm-project/commit/a0ccab35110951afc9adc5d7dc733ba8c58cf3f9
to restore
the original behavior of silently skipping non-existent positional input
files
in resolveArchiveMembers(), while preserving strict validation in
clang-sycl-linker.
Background:
The original commit added error reporting for non-existent input files
in the
shared resolveArchiveMembers() function to catch genuine user errors.
However,
this broke clang-nvlink-wrapper when unrecognized options were misparsed
as
input files (e.g., "relro" from "-z relro" before the -z option was
properly
declared in NVLinkOpts.td).
Temporary solution:
- Restore the silent skip behavior in resolveArchiveMembers() for
positional
input files that don't exist or are directories
- Move the input validation to clang-sycl-linker's getInput() function,
where
strict checking is appropriate for SYCL's more controlled linking
environment
- This preserves the existing test expectations:
* clang-nvlink-wrapper silently ignores non-existent inputs
* clang-sycl-linker reports "input file not found" errors
See discussion:
https://github.com/llvm/llvm-project/pull/201253#discussion_r3364244664
and comment
https://github.com/llvm/llvm-project/pull/201253#issuecomment-4651284736.
Co-Authored-By: Claude
Commit: 7556cf15527c817983a14eaf20b87fd796f8dc5c
https://github.com/llvm/llvm-project/commit/7556cf15527c817983a14eaf20b87fd796f8dc5c
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
A mlir/test/Conversion/XeGPUToXeVM/loadstore_nd_transpose.mlir
Log Message:
-----------
[MLIR][XeGPU] Support transposed load_nd of sub-32-bit elements (#201636)
The 2D block load transpose feature is only available for 32-bit
elements. When a transposed load_nd is requested for a sub-32-bit
element type, the XeGPU-to-XeVM lowering now emulates it by
reinterpreting the tile as 32-bit elements: the element size is promoted
to 32 bits, the tile width is scaled down by (32 / elemBitSize), and the
column offset (offsetW) is right-shifted by log2(32 / elemBitSize) to
account for the wider element.
Add a conversion test (loadstore_nd_transpose.mlir) covering the f16
transposed load path.
Commit: 790d7f63668c6ead80f3f3f281e5a325bda95eeb
https://github.com/llvm/llvm-project/commit/790d7f63668c6ead80f3f3f281e5a325bda95eeb
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
M mlir/test/Dialect/OpenACC/invalid-cg.mlir
M mlir/test/Dialect/OpenACC/ops-cg.mlir
Log Message:
-----------
[mlir][acc] Format consistency for reduction accumulate (#202414)
Avoid use of parentheses so that format for
`acc.reduction_accumulate` is consistent with rest of acc reduction
operations.
Commit: 046b7e951ab2282e4ee013db4e56a7c4c95a59dc
https://github.com/llvm/llvm-project/commit/046b7e951ab2282e4ee013db4e56a7c4c95a59dc
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm.mlir
Log Message:
-----------
[MLIR][XeGPU] Update Wg dpas_mx integration test. (#201680)
Make problem size smaller and add K loop.
Add host code to call gpu kernel.
Add test input and reference output.
Add comparison code to check output against reference output.
Commit: a8cb8253e4e53138894f646a0bcb5034866e3a95
https://github.com/llvm/llvm-project/commit/a8cb8253e4e53138894f646a0bcb5034866e3a95
Author: nvptm <pmathew at nvidia.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M flang/include/flang/Lower/OpenACC.h
M flang/include/flang/Semantics/symbol.h
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Lower/OpenACC/acc-declare-use-associated-allocatable.f90
M flang/test/Lower/OpenACC/acc-declare.f90
Log Message:
-----------
[flang][acc] Fix separate compilation for module !$acc declare create on allocatables. (#202409)
With separate compilation, a module defining `!$acc declare create` on
an allocatable and a using file that allocates it did not get
declare-action lowering in the using Translation Unit(TU):
`ACCDeclareActionConversion` could not resolve the post-alloc recipe
(defined only in the module .o), so no `fir.call` was emitted.
Add `acc.declare_action` for allocatable/pointer symbols under !$acc
declare.
* In the defining TU: Export module-global post-alloc/post-dealloc
recipes as linkable definitions and mark them with acc.declare_action at
creation.
* In the using TU: When declaring a USE-associated module global, emit
private external recipe stubs so the declare-action conversion pass can
insert fir.calls that link to the module definition.
Commit: c06483c6fb9fc84bed1ae33172323c9aa57a3ca4
https://github.com/llvm/llvm-project/commit/c06483c6fb9fc84bed1ae33172323c9aa57a3ca4
Author: Hamza Khan <99187565+HamzaKodez at users.noreply.github.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
A llvm/test/MC/ARM/bf-invalid-target.s
Log Message:
-----------
[ARM] Reject invalid BF encoding when target is next instruction (#201533)
When the BF instruction targets the immediately following label, the
encoded branch offset becomes zero, causing LLVM to emit invalid machine
code.
Add validation in the fixup_bf_branch path to reject this case and emit
an error instead.
Add MC regression test to cover new validation.
Assisted by ChatGPT. Human-verified, debugged, tested and validating by
author.
Commit: 14baa81e24fcd22cca188cabe3a6c76debd14c95
https://github.com/llvm/llvm-project/commit/14baa81e24fcd22cca188cabe3a6c76debd14c95
Author: Justin Lebar <justin.lebar at gmail.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/frexp.ll
Log Message:
-----------
[InstCombine] Fix invalid IR when folding frexp(frexp(x)) with mismatched exponent types (#202419)
Instcombine folds the idempotent frexp pattern
%inner = call { double, i64 } @llvm.frexp.f64.i64(double %x)
%f = extractvalue { double, i64 } %inner, 0
%outer = call { double, i32 } @llvm.frexp.f64.i32(double %f)
to `{ %f, 0 }`, because the fraction after the first frexp call is known
0. It did this by reusing the inner frexp's result struct and
overwriting field 1 with zero.
But you can see in this example that reusing the inner frexp's
result struct is invalid, because that call returns { double, i64 },
whereas the second call returns { double, i32 }.
Fix this by building the new struct instead of modifying the old one.
Commit: 700febc04caa41923eaf4b3911db26cb13482a83
https://github.com/llvm/llvm-project/commit/700febc04caa41923eaf4b3911db26cb13482a83
Author: Justin Lebar <justin.lebar at gmail.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll
Log Message:
-----------
[InstCombine] Fix incorrect is_zero_poison when folding select+ctlz to cttz (#202388)
foldSelectCtlzToCttz folds
%lz = call i32 @llvm.ctlz.i32(i32 (x & -x), i1 is_zero_poison)
%r = select (icmp eq x, 0), i32 32, i32 (xor %lz, 31)
into
%r = call i32 @llvm.cttz.i32(i32 x, i1 is_zero_poison)
The original select's result is defined when x is zero, even if
is_zero_poison is true. Therefore in the new cttz call, we need to pass
false for the second param, we can't reuse is_zero_poison.
Commit: 9f73a97cfb1a40da42a870906e2221102a71f807
https://github.com/llvm/llvm-project/commit/9f73a97cfb1a40da42a870906e2221102a71f807
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
Log Message:
-----------
[X86] Fix typo in SLH statistic description. NFC (#202424)
Commit: 1d7930a9ef276f6e85aa063c808d53cffb0719b5
https://github.com/llvm/llvm-project/commit/1d7930a9ef276f6e85aa063c808d53cffb0719b5
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/utils/sanitizers/ubsan_ignorelist.txt
Log Message:
-----------
[ubsan] Add [undefined] section to ignorelist (#202380)
`-fsanitize-blacklist` this files passed as which apply to any
sanitizers.
So if Ubsan is combined with Asan, as-is these suppressions apply to
Asan
which is clearly was not the intention.
Commit: 5eae7dc2ac7d8dde06a943771b792aeb91c31f57
https://github.com/llvm/llvm-project/commit/5eae7dc2ac7d8dde06a943771b792aeb91c31f57
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/single-scalar-cast.ll
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve2-histcnt-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/as_cast.ll
M llvm/test/Transforms/LoopVectorize/cast-costs.ll
M llvm/test/Transforms/LoopVectorize/cast-induction.ll
M llvm/test/Transforms/LoopVectorize/preserve-inbounds-gep-with-pointer-casts.ll
Log Message:
-----------
Revert "[VPlan] Use VPInstructionWithType for uniform casts." (#202427)
Reverts llvm/llvm-project#140623
breaks https://lab.llvm.org/buildbot/#/builders/160/builds/39088 due to
visibility issues
Commit: 34208eb1a7fc4088da22099872f09f62c6497154
https://github.com/llvm/llvm-project/commit/34208eb1a7fc4088da22099872f09f62c6497154
Author: Michael Jones <michaelrj at google.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/unittests/ObjectYAML/DXContainerYAMLTest.cpp
Log Message:
-----------
[ObjectYAML] Avoid comparison of compressed data (#202413)
The result of zlib compression isn't consistent across versions.
Downstream this test was failing due to our version giving slightly
different results. This version passes both upstream and downstream.
Assisted-by: Automated tooling, human reviewed.
Commit: 9b128e8b28eb4fd4aa873f984c389dcf9b8fecfd
https://github.com/llvm/llvm-project/commit/9b128e8b28eb4fd4aa873f984c389dcf9b8fecfd
Author: Oleksandr Tarasiuk <oleksandr.tarasiuk at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/FormatString.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/AST/FormatString.cpp
M clang/lib/AST/PrintfFormatString.cpp
M clang/lib/AST/ScanfFormatString.cpp
M clang/lib/Sema/SemaChecking.cpp
A clang/test/Sema/format-strings-decimal.c
Log Message:
-----------
[Clang] add support for C23 'H', 'D', and 'DD' length modifiers (#201098)
This patch adds `-Wformat` support for the C23 `H`, `D`, and `DD` length
modifiers in `printf`/`scanf` format strings. #116962
Commit: d33b8093ce336b92d01f55033aed7021f5244eec
https://github.com/llvm/llvm-project/commit/d33b8093ce336b92d01f55033aed7021f5244eec
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/Transforms/Transforms.h
M mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/test/Dialect/XeGPU/invalid.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_3d_gemm.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_3d_mxfp_gemm.mlir
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
Log Message:
-----------
[MLIR][XeGPU] Add unrolling/blocking support for 3D+ batched operations (#201725)
**Summary**
Add complete transform pass and lowering support for 3D+ batched
operations, building on the operation definition extensions for
load_nd/store_nd/prefetch_nd/dpas/dpas_mx. This enables end-to-end
compilation of batched GEMM workloads (e.g., [4, 64, 32] × [4, 32, 64] →
[4, 64, 64]).
**Key changes:**
Transform passes (XeGPUUnroll.cpp):
> Implement 3D batch unrolling using memref.subview to handle batch
offsets
> UnrollCreateNdOp: For rank > 2 with memref source, create per-batch
memref.subview slices and corresponding create_nd_tdesc ops
> UnrollLoadNdOp/StoreNdOp/PrefetchNdOp: Iterate over batch dimension
then inner 2D tile offsets, reusing batch tdescs across inner tiles
> UnrollDpasOp/UnrollDpasMxOp: Add outer batch loop before M/K/N
unrolling
> Remove returnSingleType parameter, compute correct batch counts
directly
> Use targetShape (inst_data) for tdesc window size
>
Blocking pass (XeGPUBlocking.cpp):
> Update getUnrolledTypes() to handle batch dimensions in TensorDescType
> Extend inst_data extraction for >2D vectors with leading batch dims
> Fix getDpasInstDataVectors() to use correct M dimension for >2D types
Layout propagation (XeGPULayoutImpl.cpp, XeGPUPropagateLayout.cpp):
> Extend createScaleLayout() to handle rank >= 2
> Fix store_nd inst_data propagation for rank > 2
> Update lane layout logic to handle >2D vectors with leading unit dims
Distribution (XeGPUWgToSgDistribute.cpp):
> Extend WgToSgDpasOp and WgToSgDpasMxOp to handle >2D result shapes
Lowering (XeGPUToXeVM.cpp):
> Keep batch offset computation in unroll pass via memref.subview
> Use last 2 dims for H/W offsets and shape in CreateNdDescToXeVMPattern
> Handle tileRank >= 2 in load/store/prefetch lowering
Utilities (XeGPUUtils.cpp):
> Update getDistributedVectorType for batch-aware shapes by trimming
leading layout dims
Tests:
> Add xegpu-blocking.mlir tests for 3D batch dpas and dpas_mx unrolling
> Add simple_3d_gemm.mlir integration test (4-batch GEMM)
> Add simple_3d_mxfp_gemm.mlir integration test (XFAIL)
> Update invalid.mlir with 3D shape mismatch tests
Assisted-by-Claude
---------
Co-authored-by: Claude Sonnet 4.5 <noreply at anthropic.com>
Commit: 52ba9fa9732e8dcace2d28561caf1ef0b9631a78
https://github.com/llvm/llvm-project/commit/52ba9fa9732e8dcace2d28561caf1ef0b9631a78
Author: kwyatt-ext <kwyatt.external at hpe.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/symbol.h
M flang/include/flang/Semantics/tools.h
M flang/include/flang/Semantics/type.h
M flang/lib/Evaluate/type.cpp
M flang/lib/Lower/ConvertType.cpp
M flang/lib/Parser/Fortran-parsers.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Semantics/symbol.cpp
M flang/lib/Semantics/tools.cpp
M flang/lib/Semantics/type.cpp
A flang/test/Parser/enumeration-type.f90
Log Message:
-----------
Reapply "[flang] Enumeration Type: (PR 1/5) Foundation types + Parser" (#202440)
FortranEvaluate referenced DerivedTypeSpec::GetScope(), defined
out-of-line in FortranSemantics, producing an undefined reference in
libFortranEvaluate.so under BUILD_SHARED_LIBS=ON. Made GetScope() inline
in symbol.h so no cross-library symbol is needed.
This is the fix missing from the original PR (#192651), which was
reverted in #202408.
---------
Co-authored-by: Kevin Wyatt <kwyatt at hpe.com>
Commit: 26ebcddb8f886640b20a8643d5ff212f95f7bbd8
https://github.com/llvm/llvm-project/commit/26ebcddb8f886640b20a8643d5ff212f95f7bbd8
Author: jpwang <jpwang at smail.nju.edu.cn>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGen/prefetch-poison-arg.c
Log Message:
-----------
[Clang][CodeGen] Avoid emitting poison immargs for __builtin_prefetch (#201623)
Fixes #201448
This PR fixes invalid clang CodeGen when lowering `__builtin_prefetch`
that is called with a constant expression that produces a poison value.
The code currently assumes that the immediate operands are
`ConstantInt`s. This is not always true as poison values may come from
UB expressions (e.g., `__builtin_prefetch(0, 2 >> 32)`) due to the use
of `EmitScalarExpr`. This would cause the subsequent downcast
`cast<ConstantInt>` in `SelectionDAGBuilder` to fail.
This PR replaces `EmitScalarExpr` with `EmitScalarOrConstFoldImmArg` to
obtain an integer constant instead of emitting a poison value for the
corresponding arguments of `llvm.prefetch`.
A regression test is also added to cover the poison immediate argument
case.
I used GPT-5.5 while working on this PR for understanding the issue and
drafting the PR description / test plan. The actual code changes and
tests are written by me, and I have noted the AI tool usage in the PR
description.
Commit: 5709f9560f261866011e612993e46f72892ddb62
https://github.com/llvm/llvm-project/commit/5709f9560f261866011e612993e46f72892ddb62
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M lldb/include/lldb/API/SBModule.h
M lldb/include/lldb/API/SBModuleSpec.h
M lldb/include/lldb/Core/Module.h
M lldb/include/lldb/Symbol/SymbolFile.h
M lldb/include/lldb/Symbol/SymbolFileOnDemand.h
M lldb/source/API/SBModule.cpp
M lldb/source/API/SBModuleSpec.cpp
M lldb/source/Core/Module.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.h
A lldb/test/API/python_api/sbmodule/SeperateDebugInfo/Makefile
A lldb/test/API/python_api/sbmodule/SeperateDebugInfo/TestSBModuleSeparateDebugInfo.py
A lldb/test/API/python_api/sbmodule/SeperateDebugInfo/bar.cpp
A lldb/test/API/python_api/sbmodule/SeperateDebugInfo/main.cpp
Log Message:
-----------
[LLDB] Expose enumerator for separate-debug-info in SBModule (#144119)
Today we can run `target modules dump separate-debug-info --json` to get
a json blob of all the separate debug info, but it has a few
shortcomings when developing some scripting against it. Namely, the
caller has to know the structure of the JSON per architecture that will
be returned.
I've been working on a Minidump packing utility where we enumerate
symbols and source and put them in a package so we can debug with
symbols portably, and it's been difficult to maintain multiple
architectures due to the above shortcomings. To address this for myself,
I've exposed a simple iterator for the SBModule to get all the
separate-debug-info as list of filespecs with no need for the caller to
have context on what kind of data it is.
I also extened the swig interfaces to make writing my test easier and as
a nice to have.
Commit: 76afb4d5433e3324a34be585ee3adab9ee9f3d2e
https://github.com/llvm/llvm-project/commit/76afb4d5433e3324a34be585ee3adab9ee9f3d2e
Author: Endre Fülöp <endre.fulop at sigmatechnology.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp
M clang/test/Analysis/cstring-uninitread-notes.c
M clang/test/Analysis/placement-new.cpp
M clang/test/Analysis/std-c-library-functions-arg-constraints-tracking-notes.c
M clang/test/Analysis/std-c-library-functions-arg-constraints.c
M clang/test/Analysis/uninit-const.c
M clang/test/Analysis/uninit-vals.m
Log Message:
-----------
[analyzer] Fix misleading 'initialized here' note for uninitialized d… (#198345)
…eclarations
When a variable is declared without an initializer, the
BugReporterVisitor would emit 'initialized here' as a note, which is
confusing because the variable was never initialized.
Change the note to 'declared without an initial value' for declarations
that have no initializer. Global-storage variables are also taken into
consideration.
Removed the SI.Value.isUndef() case, as it is unreachable in
practice because core.uninitialized.Assign (a core checker, always
enabled) reports
the assignment before this note can surface.
Commit: 87966833a691a5cabc0507c09e15e4350e9df854
https://github.com/llvm/llvm-project/commit/87966833a691a5cabc0507c09e15e4350e9df854
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/unittests/Support/DynamicLibrary/PipSqueak.h
Log Message:
-----------
[test][DynamicLibrary] Add visibility attribute for GCC/Clang in PipSqueak.h (#202445)
By default CFI builds with hidden, failing expectation for the test.
Commit: c0c6694ad9e33deebe4187de6de06cd0c65d97c8
https://github.com/llvm/llvm-project/commit/c0c6694ad9e33deebe4187de6de06cd0c65d97c8
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing.ll
A llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions-tail-folded.ll
Log Message:
-----------
[VPlan] Fix vplan printing for VPExpressionRecipe w/conditional reduction. (#198954)
This patch contains two parts.
- Add a new vplan-printing test which is duplicated from
vplan-printing-reductions.ll and force tail folding.
- Fix the printing of VPExpressionRecipe for conditional reductions.
Since the mask operand cannot be accessed directly through the reduction
recipe once folded, it need to be fetched from the expression recipe's
operands.
Commit: 884a4344916ac52b8071317e6b57b6a38acf214e
https://github.com/llvm/llvm-project/commit/884a4344916ac52b8071317e6b57b6a38acf214e
Author: Raphael Isemann <rise at apple.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/CxxStringTypes.cpp
M lldb/source/Plugins/Language/CPlusPlus/GenericBitset.cpp
M lldb/source/Plugins/Language/CPlusPlus/GenericOptional.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxMap.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxUnorderedMap.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibStdcpp.cpp
M lldb/source/Plugins/Language/ObjC/CF.cpp
M lldb/source/Plugins/Language/ObjC/Cocoa.cpp
M lldb/source/Plugins/Language/ObjC/NSSet.cpp
M lldb/source/Plugins/Language/ObjC/ObjCLanguage.cpp
Log Message:
-----------
[lldb][NFC] Remove redundant TypeSystemClang.h includes (#202439)
TypeSystemClang.h includes a lot of other unique headers, and should not
be included unless needed.
Commit: b01fe4e3d192a293caee9ec74ff4012958758d6b
https://github.com/llvm/llvm-project/commit/b01fe4e3d192a293caee9ec74ff4012958758d6b
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUBarrierLatency.cpp
M llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
Log Message:
-----------
[AMDGPU] Do not always add latency between LDSDMA -> S_WAIT_LDSDMA (#201942)
In loop bodies we typically see LDSDMA instructions prefetched an
iteration or more. Thus, we may have LDSDMA, followed by S_WAIT_LDSDMA
that is waiting on prior iteration LDSDMA. Currently, the scheduler
thinks there will be a long stall between this LDSDMA and S_WAIT_LDSDMA.
This adds some basic checking for LDSDMA and S_WAIT_LDSDMA in the same
region to avoid adding latency in cases where we are certain the
S_WAIT_LDSDMA does not correspond with the LDSDMA.
Commit: 7087094b05a1bba64a99474cc501328919e11b4a
https://github.com/llvm/llvm-project/commit/7087094b05a1bba64a99474cc501328919e11b4a
Author: Aviral Goel <aviralg at users.noreply.github.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/data-element-not-object.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/data-entry-missing-data.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/data-entry-missing-summary-name.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/data-not-array.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/duplicate-entity-id-in-data-map.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/duplicate-entity.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/duplicate-summary-name.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/entity-data-element-not-object.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/entity-data-missing-entity-id.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/entity-data-missing-entity-summary.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/entity-id-not-uint64.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/entity-name-missing-suffix.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/entity-name-missing-usr.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/id-table-element-not-object.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/id-table-entry-id-not-uint64.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/id-table-entry-missing-id.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/id-table-entry-missing-name.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/id-table-not-array.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/invalid-kind.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/invalid-syntax.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-duplicate-id.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-element-not-object.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-entry-id-not-uint64.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-entry-linkage-invalid-type.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-entry-linkage-missing-type.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-entry-missing-id.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-entry-missing-linkage.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-extra-id.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-missing-id.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-not-array.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/missing-data.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/missing-id-table.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/missing-kind.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/missing-linkage-table.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/missing-name.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/missing-tu-namespace.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/not-json-extension.txt
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/not-object.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/pairs-element-not-object.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/pairs-invalid-first-field.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/pairs-invalid-pairs-field-type.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/pairs-invalid-second-field.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/pairs-missing-first-field.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/pairs-missing-pairs-field.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/pairs-missing-second-field.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/read-entity-summary-no-format-info.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/rt-empty-data-entry.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/rt-empty.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/rt-link-unit.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/rt-linkage-external.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/rt-linkage-internal.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/rt-linkage-multiple.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/rt-linkage-none.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/rt-two-summary-types.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/id-table.test
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/io.test
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/linkage.test
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/permissions.test
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/round-trip.test
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/summary-data.test
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/top-level.test
M clang/unittests/ScalableStaticAnalysisFramework/Serialization/JSONFormatTest/TUSummaryTest.cpp
Log Message:
-----------
[clang][ssaf] Convert `JSONFormat` tests for `TUSummary` and `TUSummaryEncoding` to lit tests (#192187)
This change converts most of the `TUSummary` json tests in `TUSummaryTest.cpp` to use `lit`. Some tests require more care and will be addressed in future PRs.
Commit: b47267441e513f5d65169933cba48c26eb40b803
https://github.com/llvm/llvm-project/commit/b47267441e513f5d65169933cba48c26eb40b803
Author: Alex Crichton <alex at alexcrichton.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
A llvm/test/CodeGen/WebAssembly/multivalue-do-not-stackify.ll
M llvm/test/CodeGen/WebAssembly/multivalue-stackify.ll
M llvm/test/CodeGen/WebAssembly/multivalue.ll
M llvm/test/CodeGen/WebAssembly/multivalue_libcall.ll
M llvm/test/CodeGen/WebAssembly/wide-arithmetic.ll
Log Message:
-----------
[WebAssembly] Don't stackify multi-def instructions (#200429)
This commit updates the `WebAssemblyRegStackify.cpp` pass to
specifically exclude attempting to stackify the first def of a multi-def
instruction. As the previous comments indicate this is possible to do in
some situations, but the current logic is incomplete and has led to
miscompilations such as #98323 and #199910. One option would be to make
the logic more robust, but in lieu of that in the meantime the change
here is to completely disable stackification in these situations. This
provides at least a "known working" base to build on later and fixes the
known regressions around this.
Closes #98323
Closes #199910
Commit: 89086dbe073123f1a6507c74681d82f674250dcb
https://github.com/llvm/llvm-project/commit/89086dbe073123f1a6507c74681d82f674250dcb
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
A llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_vector_bfloat16_amd.ll
Log Message:
-----------
[SPIR-V] Allow bfloat vector atomics lowering without scalarization (#202083)
This is a workaround only for AMD triple - to use
SPV_NV_shader_atomic_fp16_vector for this lowering.
Commit: 2426b855f30344b603ca84ce5b8c7e0d94799fe7
https://github.com/llvm/llvm-project/commit/2426b855f30344b603ca84ce5b8c7e0d94799fe7
Author: Alexey Bader <alexey.bader at intel.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M clang/docs/ClangSYCLLinker.rst
M clang/test/OffloadTools/clang-sycl-linker/basic.ll
M clang/test/OffloadTools/clang-sycl-linker/link.ll
M clang/test/OffloadTools/clang-sycl-linker/split-mode.ll
M clang/test/OffloadTools/clang-sycl-linker/triple.ll
M clang/tools/clang-nvlink-wrapper/CMakeLists.txt
M clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp
M clang/tools/clang-sycl-linker/CMakeLists.txt
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
M clang/tools/clang-sycl-linker/SYCLLinkOpts.td
R llvm/include/llvm/Frontend/Offloading/ArchiveLinker.h
R llvm/lib/Frontend/Offloading/ArchiveLinker.cpp
M llvm/lib/Frontend/Offloading/CMakeLists.txt
Log Message:
-----------
Revert "[clang][sycl][nvlink] Share static library linking in Frontend/Offloading (#201253)" (#202457)
This reverts commits
https://github.com/llvm/llvm-project/commit/8aafa50c7a2dfb8ca1d5cdf8980f7f2d259779f5,
https://github.com/llvm/llvm-project/commit/dca9eaa98fd71535e8d283ae390c96266c5b9b8c,
https://github.com/llvm/llvm-project/commit/7389aa2ef380ca2b64d8fa34b633e5d2a4efef0a
and
https://github.com/llvm/llvm-project/commit/6c6338b3438704cddc1cf3bc6676316856b64907.
These commits break libomptarget :: nvptx64-nvidia-cuda. See
https://github.com/llvm/llvm-project/pull/201253#issuecomment-4654267605
for more details.
Commit: 7af9c337ba71a58d1d677e0df7fd22c72132bbde
https://github.com/llvm/llvm-project/commit/7af9c337ba71a58d1d677e0df7fd22c72132bbde
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M .github/workflows/bazel-checks.yml
Log Message:
-----------
[Github] Make bazel-checks workflow validate shasums (#202405)
For some added security (although it's probably not super helpful here),
and consistency across the code base.
Commit: 55a17cc57dd0aa3febe11fef55140a334f01e415
https://github.com/llvm/llvm-project/commit/55a17cc57dd0aa3febe11fef55140a334f01e415
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/SandboxIR/Use.h
Log Message:
-----------
[clang-cl] Fix friend class warning on Windows (#201720)
clang-cl warned on "friend class CallInst;" because MSVC may resolve
that to "friend llvm::CallInst" instead of the sbox IR mirrored
hierarchy. Drop the class tag and refer to forward declared names
instead.
Commit: bba08d76c1412f4740188e3528b43a8eeee11c6b
https://github.com/llvm/llvm-project/commit/bba08d76c1412f4740188e3528b43a8eeee11c6b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libcxx/utils/ci/docker/docker-compose.yml
Log Message:
-----------
[libcxx] Bump Github runner image version (#202470)
To stay ahead of the curve on the runner support time horizon.
Commit: dd87edd1f48b02e4a58dbd0a6fdda07c36c4dea8
https://github.com/llvm/llvm-project/commit/dd87edd1f48b02e4a58dbd0a6fdda07c36c4dea8
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M .github/workflows/containers/github-action-ci-windows/Dockerfile
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[Github] Bump container runner version (#202471)
To stay ahead of the curve on the support horizon.
Commit: 564d69a8dec3183ebd78a779efdd8903bbe89f68
https://github.com/llvm/llvm-project/commit/564d69a8dec3183ebd78a779efdd8903bbe89f68
Author: Kees Cook <kees at kernel.org>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M clang/include/clang/AST/Expr.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/Expr.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGen/attr-counted-by-issue200014.c
Log Message:
-----------
[Clang][counted_by] Honor counted_by in __bdos on direct struct access (#201161)
__builtin_dynamic_object_size on a flexible array member must consult
the 'counted_by' attribute even when the containing struct is accessed
directly (a local or global variable) rather than through a pointer
dereference. The pointer-deref form (p->fam) already worked because the
constant evaluator could not determine the LValue for an opaque
parameter and fell through to the counted_by-aware runtime path in
CGBuiltin. The direct form (af.fam, gaf.fam) was being folded by
tryEvaluateBuiltinObjectSize to a layout-derived size (e.g. trailing
struct padding for locals, trailing initializer data for globals)
silently bypassing emitCountedBySize.
Make the AST constant evaluator refuse to fold __bdos on the same
operands that CGBuiltin's __bdos lowering classifies as a counted_by
FAM access. The check runs after the existing negative-offset early
return so that obviously out-of-bounds operands like &p->array[-42]
still fold to 0, preserving the behavior the sanitizer-bounds test in
attr-counted-by.c (test35) relies on.
Rather than duplicate the Expr-walking logic, promote CGBuiltin's
StructFieldAccess visitor into a shared function findStructFieldAccess
declared in clang/AST/Expr.h, with the visitor moved to an
anonymous-namespace implementation in Expr.cpp. Both CGBuiltin's
emitCountedBySize and the new ExprConstant check use it, so they
recognize
exactly the same set of expression shapes.
Note that the helper deliberately treats `&af.fam` (address-of-array)
as *not* a counted_by access. `&af.fam` designates the array object
as a whole and gets the layout-derived size, while `af.fam` (decayed)
and `&af.fam[idx]` designate element-pointers and get the count-based
size. This matches GCC 16's behavior.
The regression test covers the full {local, global, pointer-arg} x
{fam, &fam[idx], &fam} matrix (9 tests) with both -O0 and -O2 RUN
lines, autogenerated via update_cc_test_checks.py. -O0 checks the
frontend output directly: emitCountedBySize's counted_by.gep /
counted_by.load / flexible_array_member_size for the counted_by tests,
and the raw @llvm.objectsize.i64.p0 intrinsic call for the '&fam'
layout tests. -O2 pins down the post-optimization shape (smax(%n, 0)
for the runtime tests, ret i64 <constant> for the layout tests). All
nine tests match GCC 16's __bdos output.
Fixes: #200014
Commit: e34dc2960ce94be069ac2a973c943b61ef9b3b23
https://github.com/llvm/llvm-project/commit/e34dc2960ce94be069ac2a973c943b61ef9b3b23
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/unittests/Support/DynamicLibrary/DynamicLibraryTest.cpp
Log Message:
-----------
[test][Support] Disable CFI-icall for DynamicLibrary Overload test (#202446)
The test performs manual symbol lookup and calls, which triggers
Control Flow Integrity indirect call checks.
Commit: 048e9675f3415c4c758dadbea982037ae1ba3376
https://github.com/llvm/llvm-project/commit/048e9675f3415c4c758dadbea982037ae1ba3376
Author: Alex Crichton <alex at alexcrichton.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
Log Message:
-----------
[WebAssembly] Fix unused variable in #200429 (#202464)
Fixes a mistake from #200429.
Commit: 9ab6d33bc4d30bce9de62e2d96e0f3427ae0eddf
https://github.com/llvm/llvm-project/commit/9ab6d33bc4d30bce9de62e2d96e0f3427ae0eddf
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M clang/test/Driver/fsanitize-realtime.c
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/test/rtsan/lit.cfg.py
Log Message:
-----------
[rtsan][clang] Add Hexagon support for RTSan (#200313)
Enable RTSan for the Hexagon architecture.
* Add Hexagon to ALL_RTSAN_SUPPORTED_ARCH in cmake
* Add a clang driver test for hexagon-unknown-linux-musl
* Guarding a static_assert(sizeof(unsigned long) >= sizeof(off_t)) with
SANITIZER_WORDSIZE >= 64, since off_t syscall args are split into two
regs.
Commit: 7cc09c43384b16a8d8bfca809dae14c2c200451a
https://github.com/llvm/llvm-project/commit/7cc09c43384b16a8d8bfca809dae14c2c200451a
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/MacroToEnumCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/.gitattributes
A clang-tools-extra/test/clang-tidy/checkers/modernize/Inputs/macro-to-enum/crlf.cpp
A clang-tools-extra/test/clang-tidy/checkers/modernize/Inputs/macro-to-enum/crlf.cpp.expected
A clang-tools-extra/test/clang-tidy/checkers/modernize/macro-to-enum-crlf.cpp
Log Message:
-----------
Reland "[clang-tidy] Preserve line endings in macro-to-enum fixes" (#202271)
Use StringRef::detectEOL() when inserting enum braces so fix-its do not
mix LF into CRLF source files.
This reland fixes the previous buildbot failure by adding `--` in test
file.
Commit: 7ed2f70f6c5b3849017f0eb38c521cc5d42040a2
https://github.com/llvm/llvm-project/commit/7ed2f70f6c5b3849017f0eb38c521cc5d42040a2
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/test/CodeGenHLSL/ArrayAssignable.hlsl
M clang/test/CodeGenHLSL/ArrayAssignable.logicalptr.hlsl
M clang/test/CodeGenHLSL/cbuffer-matrix-layout-keyword.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer-empty-struct-array.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_and_namespaces.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_with_packoffset.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_with_static_global_and_function.hlsl
M clang/test/CodeGenHLSL/resources/default_cbuffer.hlsl
M clang/test/CodeGenHLSL/resources/default_cbuffer_with_layout.hlsl
M llvm/include/llvm/Frontend/HLSL/CBuffer.h
M llvm/lib/Frontend/HLSL/CBuffer.cpp
M llvm/lib/Target/DirectX/DXILCBufferAccess.cpp
M llvm/lib/Target/SPIRV/SPIRVCBufferAccess.cpp
A llvm/test/CodeGen/DirectX/cbuffer_global_elim.ll
A llvm/test/CodeGen/SPIRV/cbuffer_global_elim.ll
Log Message:
-----------
[HLSL] Set visibility of cbuffer global variables to internal (#200312)
Global variables for all resources except `cbuffer` are already emitted
with internal linkage (since #166844). This change adds internal linkage
to the `cbuffer` handle globals as well.
One problem is that the `cbuffer` handle globals appears unused between
Clang CodeGen and `{DXIL|SPIRV}CBufferAccess` pass, which replaces
individual `cbuffer` constant globals with accesses through the
`cbuffer` handle globals. Before this pass runs, the unused globals
could get optimized away in `GlobalOptPass` with `-O3`.
To solve this, the `cbuffer` handle globals are added to the
`@llvm.compiler.used` list to make sure they stay in the module until
the `{DXIL|SPRIV}CBufferAccess` pass, which then removes them from the
list.
Commit: 396a31fca9bbeaafc41a60d4e2a9a6cf7ca03398
https://github.com/llvm/llvm-project/commit/396a31fca9bbeaafc41a60d4e2a9a6cf7ca03398
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
A clang/test/CodeGenHIP/offload-pgo-sections.hip
A clang/test/Driver/hip-profile-rocm-runtime.hip
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
A llvm/test/Instrumentation/InstrProfiling/amdgpu-instrumentation.ll
A llvm/test/Instrumentation/InstrProfiling/amdgpu-profc-arrays.ll
A llvm/test/Instrumentation/InstrProfiling/gpu-weak.ll
A llvm/test/Transforms/PGOProfile/amdgpu-disable-value-profiling.ll
Log Message:
-----------
Reland HIP offload PGO compiler support and link the device-profile runtime (#201607)
This mostly relands the compiler part of #177665 (approved and merged,
then reverted in #201416). The first commit restores it as merged: the
AMDGPU instrumentation in LLVM and the HIP codegen in Clang.
#177665 was reverted because of a Windows CRT problem, fixed by
splitting the ROCm runtime into a separate library clang_rt.profile_rocm
(see the compiler-rt PR). The second commit links that library on the
host for HIP device PGO, in addOffloadRTLibs for the Linux and MSVC
toolchains, gated on HIP + profiling + the library being present. It is
a superset of clang_rt.profile and is linked first, so the base library
stays inert. Non-HIP links are unaffected.
Depends on the compiler-rt PR that adds clang_rt.profile_rocm.
Commit: 774c4c9b098f653bb86c7ab4f1bc8255e76b0623
https://github.com/llvm/llvm-project/commit/774c4c9b098f653bb86c7ab4f1bc8255e76b0623
Author: Henry Jiang <henry_jiang2 at apple.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/test/CodeGen/unique-internal-linkage-names.c
M clang/test/CodeGen/unique-internal-linkage-names.cpp
Log Message:
-----------
[clang] -funique-internal-linkage-names should not be applied to asm label (#202004)
Commit: d68c7424d130432a3ab30edbbd860ec00e42f180
https://github.com/llvm/llvm-project/commit/d68c7424d130432a3ab30edbbd860ec00e42f180
Author: Garvit Gupta <garvgupt at qti.qualcomm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
M llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll
M llvm/test/CodeGen/RISCV/frame.ll
M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
M llvm/test/CodeGen/RISCV/ipra.ll
M llvm/test/CodeGen/RISCV/large-stack.ll
M llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
A llvm/test/CodeGen/RISCV/prefer-sp-over-fp-with-v.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
M llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
Log Message:
-----------
Reland [RISCV] Prefer SP over FP for frame index access when offset fits within compressed immediate range. (#201541)
Before this change, we would use fp/s0/x8 for most stack accesses when
frame pointers were present. This is an over-approximation when a
stack slot is reachable from both SP and FP with no scalable offset.
This patch replaces the unconditional getFrameRegister() call in
getFrameIndexReference with an explicit register selection decision
tree.
When both SP and FP are available (no stack realignment, no
variable-sized objects), prefer SP if the SP-relative offset fits in
the compressed instruction immediate range (<=252 for RV32, <=504 for
RV64). This enables compression for sp-relative instructions to
c.swsp/c.lwsp (RV32) and c.sdsp/c.ldsp (RV64) thereby reducing code
size.
The SP preference is guarded by hasReservedCallFrame(MF) to ensure SP
is stable throughout the function body. This is necessary because
hasRVVFrameObject() conservatively returns true for any function
compiled
with V extension, causing hasReservedCallFrame() to return false even
for
scalar functions without RVV spills. Without this guard, SP-relative
offsets would be incorrect when ADJCALLSTACKDOWN/UP move SP during the
function body. This was observed as a miscompile in zstd decompression
when compiled with -fno-omit-frame-pointer -march=rv64gcv.
Reland of 46e07d38e078 with the hasReservedCallFrame guard fix.
Commit: 097e92d5c7ac03ddfdd0ebc55faddd7ac90e947f
https://github.com/llvm/llvm-project/commit/097e92d5c7ac03ddfdd0ebc55faddd7ac90e947f
Author: Mitch Briles <mitchbriles at gmail.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/test/CodeGen/NVPTX/math-intrins.ll
Log Message:
-----------
[NVPTX] Support lowering of `(l)lround` (#183901)
These intrinsics should have the same semantics as libm `round`, but
with an integer return type. Nits appreciated.
Fixes #182378
Commit: 7a1c71410feb5d5069ebbaa886b7e4331fe774da
https://github.com/llvm/llvm-project/commit/7a1c71410feb5d5069ebbaa886b7e4331fe774da
Author: Christian Sigg <csigg at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Port 7ed2f70 (#202497)
Commit: a581124cd4b332d04ba1e7824066f41ae8a31b42
https://github.com/llvm/llvm-project/commit/a581124cd4b332d04ba1e7824066f41ae8a31b42
Author: Thrrreeee <shijinrui at bytedance.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lldb/source/Expression/DWARFExpression.cpp
A lldb/test/Shell/SymbolFile/DWARF/x86/DW_OP_impilict_value.s
M lldb/unittests/Expression/DWARFExpressionTest.cpp
Log Message:
-----------
[LLDB] Fix DW_OP_implicit_value GetOpcodeDataSize() error (#201344)
LLDB does not handle `DW_OP_implicit_value` right, causing a "cannot get
opcode data size for Unknown DW_OP constant" error when LLDB parses
location expressions containing this opcode.
`DW_OP_implicit_value` takes two operands: a ULEB128-encoded length
followed by a byte sequence of that length. The current
`GetOpcodeDataSize` implementation has no case for this opcode, only
skip. This prevents LLDB from correctly determining opcode boundaries
when scanning multi-operation location expressions.
>From DWARFv5
> The DW_OP_implicit_value operation specifies an immediate value using
two operands: an unsigned LEB128 length, followed by a sequence of bytes
of the given length that contain the value.
Although the evaluation path (`DWARFExpression::Evaluate`) handles this
opcode correctly and produces the right result, the validation/parsing
path emits a confusing error message to the user.
Commit: 2da234946a4f13a27d4322565cb4103caf9cbff1
https://github.com/llvm/llvm-project/commit/2da234946a4f13a27d4322565cb4103caf9cbff1
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/test/CodeGen/NVPTX/math-intrins.ll
Log Message:
-----------
Revert "[NVPTX] Support lowering of `(l)lround`" (#202500)
Reverts llvm/llvm-project#183901
Looks like using removeFromUseLists from Transforms doesn’t work in
certain configurations.
Commit: 29b36a16f111e5a57264c5706b254c82ff0a24bc
https://github.com/llvm/llvm-project/commit/29b36a16f111e5a57264c5706b254c82ff0a24bc
Author: yonghong-song <yhs at fb.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/BPF/BTFDebug.h
A llvm/test/CodeGen/BPF/BTF/func-nocall-all-dead.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-bool-arg.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-const-arg.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-const-no-shift.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-dead-arg.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-dead-type-mismatch.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-decl-tag.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-mixed-types.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-multi-dead.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-no-dead-arg.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-stack-arg-i64.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-stack-arg.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-stack-homed-arg.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-undef-dead-arg.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-void-return.ll
Log Message:
-----------
[BPF] Emit ABI-accurate BTF prototypes for DW_CC_nocall (#198426)
DW_CC_nocall subprograms can end up with an optimized IR signature that no
longer matches the original source-level DISubroutineType. Dead argument
elimination may drop source parameters, and the return value may be
removed entirely, while the debug type still describes the original
prototype. In that case BTFDebug emits a FUNC_PROTO that no longer
matches the real BPF ABI.
Teach BTFDebug to derive a filtered FUNC_PROTO for nocall functions.
Detecting surviving arguments (collectNocallEntryArgRegs):
Scan all DBG_VALUE instructions in the entry block while tracking which
registers have been redefined by non-debug instructions:
- A DBG_VALUE whose register has not been redefined records a
register-passed argument (R1-R5 at function entry).
- A DBG_VALUE whose register was most recently loaded via LDD $r11,
offset records a stack-passed argument (beyond the first five).
LowerFormalArguments always places stack argument loads in the entry
block, so scanning MF.front() is sufficient.
- Indirect DBG_VALUEs (describing memory locations, e.g. spills to
[$r10 + offset]) are skipped -- the register is a base address,
not the argument value.
- DBG_VALUEs with immediate operands (constant-propagated args) are
skipped because MO.isReg() returns false.
Emitting a filtered prototype:
A filtered prototype (true ABI signature) is emitted when all of the
following hold:
- The number of surviving source arguments equals the number of
optimized IR arguments (no merging or splitting).
- Every surviving source argument matches the corresponding IR type
(pointer, same-width integer/boolean/float, or same-width enum).
- For up to the first std::size(CC_BPF64_ArgRegs) surviving
arguments, entry-block DBG_VALUEs assign BPF registers in order
R1..R5.
The original source prototype is used as fallback when:
- The surviving source arg count differs from the IR arg count.
- Any surviving source type does not match its IR type (e.g. structs).
- The register assignment does not follow R1..R5 order.
Independently, if the IR return type is void but the debug info declares a
non-void return, the emitted BTF return type becomes void. This applies
regardless of whether the parameter list is filtered.
When using the filtered prototype, decl_tag component indices are
remapped to the filtered parameter list.
Add coverage for dead register and stack args, all-dead args, unchanged
signatures, const/bool/mixed types, type mismatches, decl_tags, poisoned
DBG_VALUE inputs, and voided returns.
Commit: d74a606a93e73ea995d6628d4893b95bcd8f6325
https://github.com/llvm/llvm-project/commit/d74a606a93e73ea995d6628d4893b95bcd8f6325
Author: Daniil Dudkin <unterumarmung at yandex.ru>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang-tools-extra/test/clang-tidy/checkers/altera/id-dependent-backward-branch.cpp
Log Message:
-----------
[clang-tidy] Fix OpenCL builtin redeclaration in test (#202429)
Guard the local `get_local_id` declaration so OpenCL C++ runs use the
builtin declaration and non-OpenCL C++ runs still compile.
Reported in:
https://github.com/llvm/llvm-project/pull/200660#issuecomment-4651173130
Commit: 4797c60469843f02a1999934d2534331668a3aef
https://github.com/llvm/llvm-project/commit/4797c60469843f02a1999934d2534331668a3aef
Author: eiytoq <eiytoq at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libcxx/test/std/containers/views/views.span/enable_borrowed_range.compile.pass.cpp
M libcxx/test/std/containers/views/views.span/range_concept_conformance.compile.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/array.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/assign.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/copy.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/deduct.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/default.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/initializer_list.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/iterator_len.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/iterator_len.verify.cpp
M libcxx/test/std/containers/views/views.span/span.cons/iterator_sentinel.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/iterator_sentinel.verify.cpp
M libcxx/test/std/containers/views/views.span/span.cons/range.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/span.dtor.compile.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/span.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/span.verify.cpp
M libcxx/test/std/containers/views/views.span/span.cons/stdarray.pass.cpp
M libcxx/test/std/containers/views/views.span/span.elem/at.pass.cpp
M libcxx/test/std/containers/views/views.span/span.elem/back.pass.cpp
M libcxx/test/std/containers/views/views.span/span.elem/data.pass.cpp
M libcxx/test/std/containers/views/views.span/span.elem/front.pass.cpp
M libcxx/test/std/containers/views/views.span/span.elem/op_idx.pass.cpp
M libcxx/test/std/containers/views/views.span/span.iterators/begin.pass.cpp
M libcxx/test/std/containers/views/views.span/span.iterators/end.pass.cpp
M libcxx/test/std/containers/views/views.span/span.iterators/iterator.pass.cpp
M libcxx/test/std/containers/views/views.span/span.iterators/iterator_concept_conformance.compile.pass.cpp
M libcxx/test/std/containers/views/views.span/span.iterators/rbegin.pass.cpp
M libcxx/test/std/containers/views/views.span/span.iterators/rend.pass.cpp
M libcxx/test/std/containers/views/views.span/span.objectrep/as_bytes.pass.cpp
M libcxx/test/std/containers/views/views.span/span.objectrep/as_writable_bytes.pass.cpp
M libcxx/test/std/containers/views/views.span/span.obs/empty.nodiscard.verify.cpp
M libcxx/test/std/containers/views/views.span/span.obs/empty.pass.cpp
M libcxx/test/std/containers/views/views.span/span.obs/size.pass.cpp
M libcxx/test/std/containers/views/views.span/span.obs/size_bytes.pass.cpp
M libcxx/test/std/containers/views/views.span/trivially_copyable.compile.pass.cpp
M libcxx/test/std/containers/views/views.span/types.pass.cpp
Log Message:
-----------
[libc++][span][test] Various cleanups for <span> tests (#202319)
This patch does:
- Simplify some test implementations
- Polish comments and synopsis
---------
Co-authored-by: A. Jiang <de34 at live.cn>
Commit: d43169c43c69343d2f00271de4fc236db1e49540
https://github.com/llvm/llvm-project/commit/d43169c43c69343d2f00271de4fc236db1e49540
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
[clang][bytecode] Loosen a __builtin_subcb assertion (#202284)
The types should match, but `QualType`s can't be compared with `==` like
that.
Commit: e4e8ea4c913bbf253cbab2dbcb29d3500a5689ac
https://github.com/llvm/llvm-project/commit/e4e8ea4c913bbf253cbab2dbcb29d3500a5689ac
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
M llvm/test/MC/RISCV/rvv/invalid.s
M llvm/test/MC/RISCV/rvv/vsetvl-alt.s
M llvm/test/MC/RISCV/rvv/vsetvl-invalid.s
M llvm/test/MC/RISCV/rvv/zvfbdota32f-invalid.s
Log Message:
-----------
[RISCV] Don't require specific extensions to use altfmt with vset(i)vli. (#202458)
The list of extensions that use altfmt is increasing and is becoming
unsustainable. The likelihood of the bit being repurposed is decreasing
with each new use. Let's just allow it unconditionally.
There is some risk here since all of these extensions are still
unratified and experimental so it could be that all of these extensions
get redefined so that this bit doesn't become altfmt. But I think that's
unlikely.
Commit: bf14b9ff2a61daed7a4bae710908f12b467568d6
https://github.com/llvm/llvm-project/commit/bf14b9ff2a61daed7a4bae710908f12b467568d6
Author: Shivam Gupta <shivam98.tkg at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
A clang/test/OpenMP/critical-dso-local.cpp
M clang/test/OpenMP/critical_codegen.cpp
M clang/test/OpenMP/critical_codegen_attr.cpp
Log Message:
-----------
[OpenMP] Mark critical region lock variables as dso_local (#201157)
OpenMP named critical regions use lock variables of the form
.gomp_critical_user_<name>.var, which are created through
CGOpenMPRuntime::getCriticalRegionLock().
These variables are created via
OpenMPIRBuilder::getOrCreateInternalVariable() and bypass the normal
CodeGenModule::setDSOLocal() path used for other Clang-generated
globals. As a result, OpenMP critical lock variables do not receive the
usual frontend dso_local inference.
Apply CodeGenModule::setDSOLocal() to critical lock variables after
creation. This matches the existing frontend
dso_local inference logic.
On ELF targets with a static relocation model, this results in direct
accesses to the lock variable instead of GOT-based accesses. For
example, x86-64 code generation changes from R_X86_64_REX_GOTPCRELX
relocations
to direct relocations for .gomp_critical_user_<name>.var, while PIC code
generation remains unchanged.
Rework of #75564.
Commit: 5ec4461fee4c0e82451b000f06b6ab916449de9f
https://github.com/llvm/llvm-project/commit/5ec4461fee4c0e82451b000f06b6ab916449de9f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/State.cpp
M clang/lib/AST/ByteCode/State.h
M clang/lib/AST/ExprConstant.cpp
Log Message:
-----------
[clang][ExprConst] Remove `State::getBottomFrame()` (#202277)
This is not necessary since `Frame` already has a `getCaller()`
function, which can be used to identify the bottom frame.
And the current code never needs the bottom frame for anything other
than checking if another frame is the bottom frame.
Commit: cd3950d972b06e16983d2cd0b6fda53af5e088be
https://github.com/llvm/llvm-project/commit/cd3950d972b06e16983d2cd0b6fda53af5e088be
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M clang/test/CodeGen/attr-counted-by-issue200014.c
Log Message:
-----------
[Clang][test] Add inferred nofree to attr-counted-by-issue200014.c checks (#202491)
Commit 89905ff21441 ("[FunctionAttrs] Add support for nofree argument
inference", #201591) infers a `nofree` parameter attribute at `-O2`. The
test `attr-counted-by-issue200014.c` (added later in #201161) was
generated before that change, so its `O2-SAME` lines omit `nofree` and
currently fail on `main`:
```
O2-SAME: ptr noundef readonly captures(none) ... (expected by test)
ptr nofree noundef readonly captures(none) ... (actual codegen)
```
This regenerates the checks with `update_cc_test_checks.py`. Test-only,
NFC.
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: 4bf399dabb18f74adfacdc708b7352a0ccfa44bc
https://github.com/llvm/llvm-project/commit/4bf399dabb18f74adfacdc708b7352a0ccfa44bc
Author: halbi2 <hehiralbi at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libcxx/include/__iterator/wrap_iter.h
Log Message:
-----------
[libc++] Finish converting __wrap_iter::operator<,== to C++20 (#193287)
+ operator< was overlooked in #179590
+ operator< was not marked constexpr in C++11
+ operator== should be defaulted when possible in C++20
Fixes #193283
Commit: 9737387fe5739a8b8e6d4b33bf2ea42f8117ef83
https://github.com/llvm/llvm-project/commit/9737387fe5739a8b8e6d4b33bf2ea42f8117ef83
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M .github/workflows/release-binaries.yml
M llvm/utils/release/build_llvm_release.bat
Log Message:
-----------
workflows/release-binaries: Install zstd on windows-11-arm (#201672)
Assisted-by: codex
Commit: 32b423ec57d76315cd42b99c0cdd9c63623d8b7b
https://github.com/llvm/llvm-project/commit/32b423ec57d76315cd42b99c0cdd9c63623d8b7b
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M flang/include/flang/Optimizer/HLFIR/Passes.td
M flang/lib/Optimizer/HLFIR/Transforms/CMakeLists.txt
A flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRCopy.cpp
R flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRCopyIn.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
R flang/test/HLFIR/inline-hlfir-copy-in.fir
A flang/test/HLFIR/inline-hlfir-copy.fir
Log Message:
-----------
[flang][hlfir] Extend InlineHLFIRCopy to inline copy_out with copy-back (#202290)
Rename `InlineHLFIRCopyIn` to `InlineHLFIRCopy` and extend it to inline
the paired `hlfir.copy_out` operation. The copy_out is inlined at its
original location, after the call, ensuring proper ordering of copy-back
and deallocation.
Only inlines when no copy-back is required (intent(in));
intent(inout/out) pairs are left untransformed.
Based on https://github.com/llvm/llvm-project/pull/179096.
Co-Authored-By: Kazuaki Matsumura <kmatsumura at nvidia.com> (Original
author of the changes).
Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>
Co-authored-by: Kazuaki Matsumura <kmatsumura at nvidia.com>
Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
Commit: 6efcb27a7436004d7b78473c467a7e00d83deb4a
https://github.com/llvm/llvm-project/commit/6efcb27a7436004d7b78473c467a7e00d83deb4a
Author: Maosu Zhao <maosu.zhao at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
Log Message:
-----------
[HWASan] Fix UB in tag-bits mask shift (#202269)
`TagMaskByte &= (1 << ClTagBits) - 1` shifts an `int` literal, which is
undefined behavior for `ClTagBits >= 32`.
Commit: ce507885e580a33d7dab8ed882925e812d7cbd2f
https://github.com/llvm/llvm-project/commit/ce507885e580a33d7dab8ed882925e812d7cbd2f
Author: Himadhith <79003240+Himadhith at users.noreply.github.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/offset_range.pass.cpp
Log Message:
-----------
[AIX][libc++] Mark offset_range test UNSUPPORTED on 32-bit AIX due to 32-bit off_t (#200861)
Marking the test as UNSUPPORTED and combined the comment since both
platforms have the same fundamental limitation with `32-bit off_t`.
---------
Co-authored-by: himadhith <himadhith.v at ibm.com>
Commit: 324ea3aa6b5c779cf97c10a018dda65fef38d18d
https://github.com/llvm/llvm-project/commit/324ea3aa6b5c779cf97c10a018dda65fef38d18d
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libcxx/include/__exception/nested_exception.h
Log Message:
-----------
[libc++] Make __can_dynamic_cast a variable template (#202297)
This makes the code a bit easier to read and avoids a class template
instatiation.
Commit: 1ada747bd3be297fcd2ac309f679f0a4024c1b1f
https://github.com/llvm/llvm-project/commit/1ada747bd3be297fcd2ac309f679f0a4024c1b1f
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-06-08 (Mon, 08 Jun 2026)
Changed paths:
M llvm/tools/llvm-exegesis/lib/Assembler.h
Log Message:
-----------
[NFC][llvm-exegesis] Disable CFI-icall for JIT-executed function (#202472)
Commit: edfcac6a5a4c63ee7b7414956031ad87ca635ae8
https://github.com/llvm/llvm-project/commit/edfcac6a5a4c63ee7b7414956031ad87ca635ae8
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Context.h
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
Log Message:
-----------
[clang][bytecode] Refactor backtrace param printing (#202325)
Instead of `classify()`ing the parameter types here, just use the saved
`PrimType` in the `ParamDescriptor`.
This also fixed an oddity with `interp::Context`: `Pointer::toRValue()`
takes an `interp::Context`, but some call sites passed an `ASTContext`
instead, which worked because of the implicit constructor. Make it
explicit.
Commit: 391cbd232dfded7d9af778f9a1fdb04982a15a42
https://github.com/llvm/llvm-project/commit/391cbd232dfded7d9af778f9a1fdb04982a15a42
Author: Garvit Gupta <garvgupt at qti.qualcomm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
Log Message:
-----------
Reland [RISCV] Check SP-relative offset in needsFrameBaseReg when FP offset overflows (#202499)
When a frame pointer is present, needsFrameBaseReg previously only
checked the FP-relative offset to decide if a virtual base register was
needed. If the worst-case FP offset exceeded the 12-bit immediate range,
a base register was always materialized, even when the SP-relative
offset would fit.
Since getFrameIndexReference can now select SP over FP when the offset
fits in the compressed instruction immediate range, also check the
SP-relative offset before deciding a base register is needed. This
avoids unnecessary base register materialization and results in some
code size savings.
Reland of b5d577d3faef.
Commit: eb954b0bb91f3a9374a00279650e1a0977871062
https://github.com/llvm/llvm-project/commit/eb954b0bb91f3a9374a00279650e1a0977871062
Author: ritter-x2a <9519134+ritter-x2a at users.noreply.github.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
Log Message:
-----------
[AMDGPU] Drop docs for invalid load-release and store-acquire operations (#202338)
The LangRef says "release and acq_rel orderings are not valid on load
instructions" [for loads](https://llvm.org/docs/LangRef.html#load-instruction)
and "acquire and acq_rel orderings aren't valid on store instructions"
[for stores](https://llvm.org/docs/LangRef.html#store-instruction).
Providing them in textual IR is diagnosed with an error.
Therefore, we should not define semantics for these invalid constructs.
Part of LCOMPILER-2273.
Commit: fc9bf89cfd9aa312bc5f1a855c76d04cf715d868
https://github.com/llvm/llvm-project/commit/fc9bf89cfd9aa312bc5f1a855c76d04cf715d868
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libcxx/include/CMakeLists.txt
R libcxx/include/__type_traits/dependent_type.h
M libcxx/include/module.modulemap.in
M libcxx/include/variant
Log Message:
-----------
[libc++] Simplify some meta programming in <variant> (#201538)
Specifically, this avoids `__dependent_type` and `__type_identity`
instantiations, reducing compile times a bit.
Commit: 188c0486bd8db4ac51afe1b986228fafe1bdf21b
https://github.com/llvm/llvm-project/commit/188c0486bd8db4ac51afe1b986228fafe1bdf21b
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/test/Analysis/LoopAccessAnalysis/early-exit-runtime-checks.ll
M llvm/test/Transforms/LoopVectorize/early-exit-calls.ll
Log Message:
-----------
[LAA] Don't check for free in evaluatePtrAddRecAtMaxBTCWillNotWrap() (#202341)
The fact that an object of a certain size existed at the the location at
some point is sufficient to prove the desired nowrap fact. Whether the
object still exists there doesn't matter in this context.
Commit: 1ad448f48b3ea8c79e3246dff691d41449db562d
https://github.com/llvm/llvm-project/commit/1ad448f48b3ea8c79e3246dff691d41449db562d
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
Log Message:
-----------
[InstCombine] Don't reuse a sibling binop with extra flags via demanded elts (#199782) (#201545)
SimplifyDemandedVectorElts can replace a vector binop with a sibling
binop. But if the sibling carries a flag the original lacked, it could
produce a result the original never would. E.g.
Reusing `sub nuw` could make the result poison on wrap.
Reusing `fmul nsz` could flip the sign of a zero.
Reusing `fdiv arcp` could make the result less accurate.
Fix by only reusing the sibling when its flags are a subset of the
replaced binop's.
https://alive2.llvm.org/ce/z/9yEaG7
Fixes #199782.
Commit: ae85794cf3a2a6a2742940609be64c1a4f4a60b7
https://github.com/llvm/llvm-project/commit/ae85794cf3a2a6a2742940609be64c1a4f4a60b7
Author: Jiahao Guo <eoonguo at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[CIR][AArch64] Lower NEON vpmax intrinsics (#201495)
### summary
part of : https://github.com/llvm/llvm-project/issues/185382
Adds ClangIR support for all AArch64 NEON pairwise-maximum intrinsics
(vpmax*) in
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#pairwise-maximum
Also enables the scalar pairwise reductions vpmaxs_f32, vpmaxqd_f64,
vpmaxnms_f32, and vpmaxnmqd_f64 by routing them through the common NEON
SISD path (fmaxv / fmaxnmv).
Commit: 6b90b6b4a38d4692d321c03684de6853622c59ea
https://github.com/llvm/llvm-project/commit/6b90b6b4a38d4692d321c03684de6853622c59ea
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/cxx20.cpp
Log Message:
-----------
[clang][bytecode] Check Ptr primtype in Store op (#202314)
Commit: 69215c5e4f03253d78218bf5ac55f81b90118082
https://github.com/llvm/llvm-project/commit/69215c5e4f03253d78218bf5ac55f81b90118082
Author: Jakob Koschel <jakobkoschel at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/docs/SafeStack.rst
M clang/lib/Sema/SemaChecking.cpp
A clang/test/Sema/safestack-deprecated-builtins.c
M compiler-rt/include/CMakeLists.txt
A compiler-rt/include/sanitizer/safestack_interface.h
M compiler-rt/lib/safestack/CMakeLists.txt
M compiler-rt/lib/safestack/safestack.cpp
M compiler-rt/test/safestack/sigaltstack.c
Log Message:
-----------
[SafeStack] Introduce public interface header and deprecate builtins (#198292)
Introduce `sanitizer/safestack_interface.h` to expose SafeStack utility
functions as a public interface, similar to other sanitizers.
Exposed functions:
* `__safestack_get_unsafe_stack_ptr`
* `__safestack_get_unsafe_stack_bottom`
* `__safestack_get_unsafe_stack_top`
Deprecate the existing `__builtin___get_unsafe_stack_*` builtins and
emit warnings suggesting the new `__safestack_` equivalents.
Runtime compatibility aliases `__get_unsafe_stack_*` are maintained.
Commit: c04c945d2563297ca75baf13050594e2bd3dcec5
https://github.com/llvm/llvm-project/commit/c04c945d2563297ca75baf13050594e2bd3dcec5
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/LICM/hoist-deref-load.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/masked-loads-side-effects-after-vec.ll
Log Message:
-----------
[ValueTracking] Handle chain of single-pred blocks in willNotFreeBetween() (#202308)
willNotFreeBetween() currently handles the case where both instructions
are in the same block, or one is in the single predecessor of the other.
This patch extends this to handle a chain of single predecessor blocks.
The budget now applies to all checked instructions, rather than per
block. Also increase the budget by a factor of two (which means that new
budget interpretation should never regress relative to the previous).
Commit: 19250eb71a32aafd540b5f9b03eea6be8121b2d2
https://github.com/llvm/llvm-project/commit/19250eb71a32aafd540b5f9b03eea6be8121b2d2
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/IR/BundleAttributes.h
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/IR/BundleAttributes.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Analysis/ValueTracking/assume.ll
M llvm/test/Transforms/InstCombine/assume.ll
M llvm/test/Verifier/assume-bundles.ll
Log Message:
-----------
[InstCombine] Drop zero size dereferenceable assumptions (#202411)
Commit: e12a55706f77052a20cf315d0d8c83a910b360fb
https://github.com/llvm/llvm-project/commit/e12a55706f77052a20cf315d0d8c83a910b360fb
Author: Yexuan Xiao <bizwen at nykz.org>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGCoroutine.cpp
A clang/test/CodeGenCoroutines/coro-cwg2935.cpp
Log Message:
-----------
[Clang][CodeGen][Coroutines] Make coroutine startup exception-safe (C… (#202279)
…WG2935)
This patch attempts to implement the solution I proposed for [CWG2935
(Github)](https://github.com/cplusplus/CWG/issues/575), aligning Clang's
behavior with GCC and MSVC instead of leaving it undefined. When
`initial_suspend` (as well as `ready` and `suspend`) throws an
exception, Clang fails to destroy the task even though the task has
already been initialized (see https://godbolt.org/z/E4Y4bEn54).
This patch updates CGCoroutine.cpp to clean up the coroutine return
value after an exception is thrown when it is constructed in place,
addressing CWG2935.
I would like to hear more opinions on the solution and seek help to fix
Clang.
Commit: cbffca291f395f8b8055396a417ee7620f6582b9
https://github.com/llvm/llvm-project/commit/cbffca291f395f8b8055396a417ee7620f6582b9
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/InterpFrame.h
Log Message:
-----------
[clang][bytecode] Only save frame offset in debug builds (#202294)
We only ever use this value to verify that a frame has cleaned up after
itself, i.e. in assertions.
Commit: c30ea28015bf0c2899b485c3bf531d7c7e61f518
https://github.com/llvm/llvm-project/commit/c30ea28015bf0c2899b485c3bf531d7c7e61f518
Author: Vaisman <vasili.svirski at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/test/Dialect/NVGPU/invalid.mlir
Log Message:
-----------
[mlir][nvgpu] Add negative tests for warpgroup MMA accumulator ops (#202516)
Add verifier tests for warpgroup MMA accumulator initialization
and store operations.
The tests cover invalid accumulator shapes, unsupported non-f32
store results, and mismatched store destination shapes.
The verifier logic for these cases exists in
WarpgroupMmaInitAccumulatorOp::verify() and
WarpgroupMmaStoreOp::verify(), but lacked explicit negative test
coverage in invalid.mlir.
Commit: bccd1b9cb744e5dd96ee59baa4bf4583457feea3
https://github.com/llvm/llvm-project/commit/bccd1b9cb744e5dd96ee59baa4bf4583457feea3
Author: Fangrui Song <i at maskray.me>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/ADT/StringMap.h
M llvm/lib/Transforms/IPO/StripSymbols.cpp
M llvm/unittests/ADT/StringMapTest.cpp
Log Message:
-----------
[StringMap] Invalidate iterators in remove() (#202520)
erase() bumps the epoch to invalidate iterators (#202237), but the
lower-level remove() — which detaches an entry without destroying it,
used
by ValueSymbolTable via Value::setName() — did not. Move the
incrementEpoch() into remove() so remove-while-iterating fails fast
under
LLVM_ENABLE_ABI_BREAKING_CHECKS too.
Aided by Claude Opus 4.8
Commit: 239a898a235ff81e6208be31670ef143435506c8
https://github.com/llvm/llvm-project/commit/239a898a235ff81e6208be31670ef143435506c8
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
Log Message:
-----------
[AArch64][GlobalISel] Fix post-legalizer observer notifications (#202376)
Assisted-by: codex
Commit: 6a18bd7be02b5f2f663018a5ab30ac12b2d3a00e
https://github.com/llvm/llvm-project/commit/6a18bd7be02b5f2f663018a5ab30ac12b2d3a00e
Author: A. Jiang <de34 at live.cn>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libcxx/include/__format/range_formatter.h
M libcxx/test/std/utilities/format/format.range/format.range.fmtset/format.functions.tests.h
M libcxx/test/std/utilities/format/format.range/format.range.formatter/format.functions.tests.h
Log Message:
-----------
[libc++][format] Propagate `m` when formatting range elements (#94562)
As per
[[tab:formatter.range.type]](https://eel.is/c++draft/tab:formatter.range.type),
the effects of the `m` option need to be propagated to the formatter of
range elements.
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Commit: c155183957c7d4a0a53cf781c266b02dd6f1a377
https://github.com/llvm/llvm-project/commit/c155183957c7d4a0a53cf781c266b02dd6f1a377
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
A llvm/test/CodeGen/AArch64/sve-multivector-fold-imms.ll
Log Message:
-----------
[AArch64][SVE] Select immediate offsets for multi-vector instructions (#201637)
This handles multi-vector intrinsics in getMemVTFromNode() and
implements the missing ISEL patterns needed to select the immediate
(mul vl) offsets.
Commit: 2990f95ae247808e5c0f413d9e91658302ea5b6f
https://github.com/llvm/llvm-project/commit/2990f95ae247808e5c0f413d9e91658302ea5b6f
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
Log Message:
-----------
[SPIR-V] Deduplicate createVariable and createExitVariable helpers into SPIRVUtils (#202512)
Commit: 620cdfb1d1000e9de4cdeb35dfa60ff0299d925e
https://github.com/llvm/llvm-project/commit/620cdfb1d1000e9de4cdeb35dfa60ff0299d925e
Author: Access <ShootingStarDragons at protonmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang-tools-extra/clangd/CompileCommands.cpp
M clang-tools-extra/clangd/unittests/CompileCommandsTests.cpp
Log Message:
-----------
[clangd][Mangler] Drop unknown compile options (#200001)
this pr remove the options that not work for clang, which will make
compile failed for clang++, and this will make modules completions of
clangd work. And we will also log the unsupported options
Commit: 99f6a20075abd71b4dd64b073c6159e507495cd2
https://github.com/llvm/llvm-project/commit/99f6a20075abd71b4dd64b073c6159e507495cd2
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/test/AST/ByteCode/codegen.cpp
Log Message:
-----------
[clang][bytecode] Check floating-point semantics in `Memcpy` op (#202204)
We shouldn't try to do the memcpy if the semantics don't match.
Commit: 7f6f60f8325aa724331a768a589e2c22b19f0416
https://github.com/llvm/llvm-project/commit/7f6f60f8325aa724331a768a589e2c22b19f0416
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/lib/Conversion/MemRefToSPIRV/MemRefToSPIRV.cpp
M mlir/test/Conversion/MemRefToSPIRV/atomic.mlir
Log Message:
-----------
[mlir][SPIR-V] Support floating-point atomic_rmw addf in MemRefToSPIRV (#202330)
Commit: 95c24830265cba8c4844dda3384025bac0bf96b4
https://github.com/llvm/llvm-project/commit/95c24830265cba8c4844dda3384025bac0bf96b4
Author: Diego Novillo <dnovillo at nvidia.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Options/Options.td
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/CodeGenHLSL/preserve-interface-dce.hlsl
A clang/test/CodeGenHLSL/preserve-interface.hlsl
A clang/test/Driver/dxc_fspv_preserve_interface.hlsl
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/test/CodeGen/SPIRV/preserve-interface-dce.ll
A llvm/test/CodeGen/SPIRV/preserve-interface.ll
Log Message:
-----------
[clang][SPIR-V] Implement -fspv-preserve-interface (#196404)
This flag, originally implemented in DXC, prevents GlobalDCE from
removing entry-point interface variables, even if they are unreferenced
after inlining.
This adds `HLSLSpvPreserveInterface` to `LangOptions.def` and
`Options.td`. In `CGHLSLRuntime::finishCodeGen()`, it adds all
`addrspace(7)` and `addrspace(8)` globals to `llvm.compiler.used`.
In `processGlobalValue()`, it extends the condition that emits
`spv_unref_global` to fire for globals whose only uses come from
`llvm.compiler.used` or `llvm.used`.
Fixes https://github.com/llvm/llvm-project/issues/136936
Commit: 8b4902300521d4a0980d9d35210c02b405f0df86
https://github.com/llvm/llvm-project/commit/8b4902300521d4a0980d9d35210c02b405f0df86
Author: Garvit Gupta <garvgupt at qti.qualcomm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M compiler-rt/test/builtins/Unit/lit.cfg.py
Log Message:
-----------
[Compiler-rt][test] Fix circular link dependency between builtins and libc (#199482)
Currently, the link order is `libclang_rt.builtins.a -lc -lm`. Builtins
are scanned first after which symbols like `abort` are unresolved
references that are resolved through libc.a. However, resolving the
references to these symbols further lead to undefined references to
`_aeabi_uldivmod` etc. that can only resolved through builtins.
Reversing the order also wont fix the issue because `libc.a` introduces
`__aeabi_uldivmod` which is resolved by builtins but it introduces
`abort` which can only be resolved libc.a.
This patch fixes this by wrapping the archives in a linker group
(--start-group/--end-group), which instructs the linker to rescan all
archives in the group until no new symbols can be resolved.
This error is exposed only when bfd like linkers are used.
Commit: ab31c28892a9ad5e016e94500861c93018736e7b
https://github.com/llvm/llvm-project/commit/ab31c28892a9ad5e016e94500861c93018736e7b
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Target/LLVMIR/nvvm/convert_fp4x2.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp6x2.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp8x2.mlir
M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
Log Message:
-----------
[MLIR][NVVM] Add support for narrow-fp to bf16x2 conversions (#200157)
This change adds the following NVVM Ops to support narrow-fp to bf16x2
conversions:
- `nvvm.convert.f6x2.to.bf16x2`
- `nvvm.convert.f4x2.to.bf16x2`
- `nvvm.convert.f8x2.to.bf16x2` (updated to allow `E4M3FN` and `E5M2`
types)
Also removes unnecessary verifiers for narrow-fp to `f16x2` conversions
to instead use `TypeAttrOf` to validate the source type in the ODS
definition.
Commit: c3d13ceb8a894312211c88bf2ef947708442a855
https://github.com/llvm/llvm-project/commit/c3d13ceb8a894312211c88bf2ef947708442a855
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization.ll
Log Message:
-----------
[AMDGPU] Use alloc size for array stride in LowerBufferFatPointers (#202530)
Array elements are laid out at multiples of getTypeAllocSize, not
getTypeStoreSize
LLVM memory model lays out array element `i` at `i * allocSize`
(reflected in `DataLayout::getTypeAllocSize`), apply it for fat pointers
to prevent miscompile
Commit: 3fec9c702b597e1a0204ff30137ae8d1557e395c
https://github.com/llvm/llvm-project/commit/3fec9c702b597e1a0204ff30137ae8d1557e395c
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/test/Conversion/SPIRVToLLVM/cast-ops-to-llvm.mlir
A mlir/test/Conversion/SPIRVToLLVM/cl-ops-to-llvm.mlir
M mlir/test/Conversion/SPIRVToLLVM/gl-ops-to-llvm.mlir
M mlir/test/Conversion/SPIRVToLLVM/logical-ops-to-llvm.mlir
Log Message:
-----------
[mlir][SPIR-V] Add SPIRVToLLVM direct conversions for cast, CL, GL and logical ops (#202506)
Lower the OpenCL extended instruction set math ops, GL math ops (Trunc,
Asin, Acos, Atan), logical Ordered/Unordered, and the pointer cast ops
to their LLVM dialect equivalents
Commit: 6bf8d4b059bd5cd4b660be6063769a9f162e5ec0
https://github.com/llvm/llvm-project/commit/6bf8d4b059bd5cd4b660be6063769a9f162e5ec0
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-step.ll
M llvm/test/Transforms/LoopVectorize/expand-scev-after-invoke.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleave-with-i65-induction.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
Log Message:
-----------
[VPlan] Look through BCast when folding live-ins (#202527)
This gives us some minor improvements.
Commit: bf860889a8ff3fea28dbace895cd633ccbe79608
https://github.com/llvm/llvm-project/commit/bf860889a8ff3fea28dbace895cd633ccbe79608
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/unittests/Support/DynamicLibrary/DynamicLibraryTest.cpp
Log Message:
-----------
Revert "[test][Support] Disable CFI-icall for DynamicLibrary Overload test" (#202550)
Reverts llvm/llvm-project#202446
Commit: 383db8a1ddc9f8db49c8305e463b3a80b7cd8638
https://github.com/llvm/llvm-project/commit/383db8a1ddc9f8db49c8305e463b3a80b7cd8638
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M .ci/compute_projects.py
Log Message:
-----------
[CI][Offload] Fix offload depends on openmp (#202541)
It appears that Offload depends on OpenMP. Thus, enable OpenMP as a
runtime to test when offload has changes.
Commit: 08636d456502fb7404e632598e16f3698367a6f7
https://github.com/llvm/llvm-project/commit/08636d456502fb7404e632598e16f3698367a6f7
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
A mlir/include/mlir/Dialect/SPIRV/IR/SPIRVExperimentalMLOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.td
A mlir/test/Dialect/SPIRV/IR/experimental-ml-ops.mlir
A mlir/test/Target/SPIRV/experimental-ml-ops.mlir
Log Message:
-----------
[mlir][spirv] Add Arm.ExperimentalMLOperations.1 extended inst set (#202283)
This instruction set provides a mechanism to encode experimental ML
operations in SPIR-V modules. Such instructions are encoded via the
single CALL operator in the instruction set by specifying an op_code and
customized inputs values.
Reference:
https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extended/Arm.ExperimentalMLOperations.asciidoc
Signed-off-by: Niklas Lithammer <niklas.lithammer at arm.com>
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: 514f5b766667c4c696b260f783403e8b41bc8798
https://github.com/llvm/llvm-project/commit/514f5b766667c4c696b260f783403e8b41bc8798
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/test/Transforms/InstSimplify/bitcast-vector-fold.ll
Log Message:
-----------
[ConstantFolding] Fix dropped bits in non-integer-ratio bitcast with undef lane (#202282)
When constant-folding a vector bitcast(e.g. <4 x i24> -> <3 x i32>), an
undef source element inserted a DstBitSize-wide zero placeholder into
the bit buffer. This could clobber defined source element, producing a
wrong result on big-endian targets.
Fix by inserting SrcBitSize-wide zero instead.
Alive2 proof:
before (unsound): https://alive2.llvm.org/ce/z/R_ZQ75
after (verified): https://alive2.llvm.org/ce/z/VuV3mz
Commit: 6746898d2bfc086947d86715e065f8dbf74e9690
https://github.com/llvm/llvm-project/commit/6746898d2bfc086947d86715e065f8dbf74e9690
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Options/Options.td
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
R clang/test/CodeGenHLSL/preserve-interface-dce.hlsl
R clang/test/CodeGenHLSL/preserve-interface.hlsl
R clang/test/Driver/dxc_fspv_preserve_interface.hlsl
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
R llvm/test/CodeGen/SPIRV/preserve-interface-dce.ll
R llvm/test/CodeGen/SPIRV/preserve-interface.ll
Log Message:
-----------
Revert "[clang][SPIR-V] Implement -fspv-preserve-interface (#196404)" (#202558)
This reverts commit 95c24830265cba8c4844dda3384025bac0bf96b4.
Fail log:
https://lab.llvm.org/buildbot/#/builders/226/builds/9015/steps/7/logs/stdio
```
FAILED: lib/libLLVMFrontendHLSL.so.23.0git
: && /opt/rh/gcc-toolset-13/root/usr/bin/c++ -fPIC -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror=date-time -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wno-uninitialized -Wno-nonnull -Wno-class-memaccess -Wno-dangling-reference -Wno-redundant-move -Wno-pessimizing-move -Wno-array-bounds -Wno-stringop-overread -Wno-dangling-pointer -Wno-noexcept-type -Wdelete-non-virtual-dtor -Wsuggest-override -Wno-comment -Wno-misleading-indentation -Wctad-maybe-unsupported -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -Wl,-z,defs -Wl,-z,nodelete -Wl,-rpath-link,/home/botworker/bbot/amdgpu-offload-build-only/build/./lib -Wl,--gc-sections -shared -Wl,-soname,libLLVMFrontendHLSL.so.23.0git -o lib/libLLVMFrontendHLSL.so.23.0git lib/Frontend/HLSL/CMakeFiles/LLVMFrontendHLSL.dir/CBuffer.cpp.o lib/Frontend/HLSL/CMakeFiles/LLVMFrontendHLSL.dir/HLSLBinding.cpp.o lib/Frontend/HLSL/CMakeFiles/LLVMFrontendHLSL.dir/HLSLResource.cpp.o lib/Frontend/HLSL/CMakeFiles/LLVMFrontendHLSL.dir/HLSLRootSignature.cpp.o lib/Frontend/HLSL/CMakeFiles/LLVMFrontendHLSL.dir/RootSignatureMetadata.cpp.o lib/Frontend/HLSL/CMakeFiles/LLVMFrontendHLSL.dir/RootSignatureValidations.cpp.o -Wl,-rpath,"\$ORIGIN/../lib:\$ORIGIN/../lib/x86_64-unknown-linux-gnu:/home/botworker/bbot/amdgpu-offload-build-only/build/lib:" lib/libLLVMCore.so.23.0git lib/libLLVMBinaryFormat.so.23.0git lib/libLLVMSupport.so.23.0git -Wl,-rpath-link,/home/botworker/bbot/amdgpu-offload-build-only/build/lib && :
/opt/rh/gcc-toolset-13/root/usr/libexec/gcc/x86_64-redhat-linux/13/ld: lib/Frontend/HLSL/CMakeFiles/LLVMFrontendHLSL.dir/CBuffer.cpp.o: in function `llvm::hlsl::CBufferMetadata::removeCBufferGlobalsFromUseList(llvm::Module&)':
CBuffer.cpp:(.text._ZN4llvm4hlsl15CBufferMetadata31removeCBufferGlobalsFromUseListERNS_6ModuleE+0xce): undefined reference to `llvm::removeFromUsedLists(llvm::Module&, llvm::function_ref<bool (llvm::Constant*)>)'
collect2: error: ld returned 1 exit status
```
Commit: a172eb9fcdebc93ad123b1f9d8b3ba953b904e7d
https://github.com/llvm/llvm-project/commit/a172eb9fcdebc93ad123b1f9d8b3ba953b904e7d
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
Log Message:
-----------
[GlobalISel][AMDGPU] Emit proper diagnostic when inline asm register allocation fails (#201380)
Replace the silent fallback return with a DiagnosticInfoInlineAsm error
and undef result values, so the failure is reported to the user instead
of relying on -global-isel-abort
discussed in https://github.com/llvm/llvm-project/pull/200771
Commit: 944284fe6329eb133bdbf9af77af6fa0cd280070
https://github.com/llvm/llvm-project/commit/944284fe6329eb133bdbf9af77af6fa0cd280070
Author: Matthias Springer <me at m-sp.org>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
Log Message:
-----------
[mlir][Interfaces] Document completeness requirement of `RegionBranchOpInterface` (#202018)
Document that interface implementations must report all possible control
flow edges. Failure to report a possible edge may break
analyses/transformations/APIs such as
`RegionBranchOpInterface::isRepetitiveRegion`.
Commit: 0f6f15a59f3f774a7f055f9754fe97c088390c4e
https://github.com/llvm/llvm-project/commit/0f6f15a59f3f774a7f055f9754fe97c088390c4e
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
A llvm/test/Transforms/IndVarSimplify/exit-value-safe-udiv.ll
Log Message:
-----------
[SCEVExpander] Don't expand a UDiv with a possibly-poison divisor (#202378)
SCEVExpander::isSafeToExpand only check divisor isKnownNonZero, which
ignore the possibility of poison. For the following divisor:
```
%ct = call i32 @llvm.cttz.i32(i32 %x, i1 true)
%divisor = add i32 %ct, 1
...
%rem = urem i32 1, %divisor
```
The urem may be hoisted unsafely.
Fix by also check divisor isGuaranteedNotToBePoison.
Fixes https://github.com/llvm/llvm-project/issues/202028
Commit: 96a263602fa6a8130cf9f67723bddb27787b7d97
https://github.com/llvm/llvm-project/commit/96a263602fa6a8130cf9f67723bddb27787b7d97
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/InterpFrame.h
Log Message:
-----------
[clang][bytecode] Remove `InterpFrame::ThisPointerOffset` (#202322)
Replace it with a `uint8_t` representing some bool flags about the
function. This reduces the size of a frame from 88 to 80 bytes.
Commit: 09b451f1e7f7715b5cf994c24ef698b2a8579dbc
https://github.com/llvm/llvm-project/commit/09b451f1e7f7715b5cf994c24ef698b2a8579dbc
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libcxx/include/__bit_reference
A libcxx/test/libcxx/containers/sequences/vector.bool/nodiscard.iterator.verify.cpp
Log Message:
-----------
[libc++][vector] Apply `[[nodiscard]]` to `vector<bool>::iterator` (#202265)
Towards #172124
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Commit: c4f4206ff3ab97db9577f11bb2dabd40896bcca9
https://github.com/llvm/llvm-project/commit/c4f4206ff3ab97db9577f11bb2dabd40896bcca9
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
A libcxx/test/libcxx/containers/sequences/vector/nodiscard.iterator.verify.cpp
Log Message:
-----------
[libc++][vector] Test `[[nodiscard]]` applied to `vector::iterator` (#202262)
Adds test coverage.
`[[nodicard]]` applied in:
- #198489
- #198492
Towards #172124
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Commit: 01d3932364bee33f8e861d5664c2983cc855124f
https://github.com/llvm/llvm-project/commit/01d3932364bee33f8e861d5664c2983cc855124f
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/Headers/__clang_hip_runtime_wrapper.h
A clang/test/Headers/hip-constexpr-cmath.hip
Log Message:
-----------
[Clang][HIP] Include `__clang_cuda_math_forward_declares.h` before `<cmath>` (#201563)
In HIP, `constexpr` functions are treated as both `__host__` and
`__device__`.
A new version of the MS STL shipped with the build tools version
14.51.36231 has `constexpr` definitions for some `cmath` functions when
the
compiler in use is Clang (this gets worse when C++23 is in use).
These definitions conflict with the `__device__` declarations we provide
in the header wrappers.
There is a workaround for this: We do not mark `constexpr`
functions [_that are defined in a system
header_](https://github.com/llvm/llvm-project/blob/03127a03860b9d8cb440fe8f51c00647f45eb8be/clang/lib/Sema/SemaCUDA.cpp#L877)
as
`__host__` and `__device__` if there is a previous `__device__`
declaration.
By moving `__clang_cuda_math_forward_declares.h` before `<cmath>` is
included we're able to benefit from this behavior.
This fixes error like this one
https://github.com/ggml-org/llama.cpp/issues/22570
even for recent versions of C++.
This patch should address C++23 concerns where more functions are marked
as `constexpr`.
However, we should still figure out how to provide `__device__
constexpr` versions for those functions, or not provide ours and use the
system's if they exist.
This patch replaces https://github.com/llvm/llvm-project/pull/200395
Commit: d7d9601c182889ec5e25492fb94d22a70c03fc2b
https://github.com/llvm/llvm-project/commit/d7d9601c182889ec5e25492fb94d22a70c03fc2b
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/Loads.h
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/MemDerefPrinter.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/MachineOperand.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
Log Message:
-----------
[Loads] Migrate isDereferenceable APIs to SimplifyQuery (#202553)
These take the usual set of analysis parameters, so we can encapsulate
them using SimplifyQuery.
Commit: 0e9ff9805decab9896068f37c18a713a68e53f93
https://github.com/llvm/llvm-project/commit/0e9ff9805decab9896068f37c18a713a68e53f93
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M offload/plugins-nextgen/level_zero/src/L0Queue.cpp
Log Message:
-----------
[OFFLOAD][L0] Add wait events for AsyncQueue memFill (#202287)
Fix an issue where memFill operations were not chained properly with respect prior operations.
Commit: 9ac836b3ddff45ebd9f4d23cae3e573991c7f64c
https://github.com/llvm/llvm-project/commit/9ac836b3ddff45ebd9f4d23cae3e573991c7f64c
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/intap.cpp
Log Message:
-----------
[clang][bytecode] Fix shifting by negative IntAP values (#202505)
The negation of a negative value didn't necessarily result in a positive
value. Fix that by giving it one more bit of precision.
Commit: 96480b2880838fe3fb3f3120347beb1ed1560d37
https://github.com/llvm/llvm-project/commit/96480b2880838fe3fb3f3120347beb1ed1560d37
Author: Andrei Golubev <andrey.golubev at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationTypeInterfaces.td
M mlir/lib/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationDialect.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-non-module-bufferize.mlir
A mlir/test/Dialect/Bufferization/Transforms/test-one-shot-module-bufferize.mlir
M mlir/test/lib/Dialect/Bufferization/TestOneShotModuleBufferize.cpp
M mlir/test/lib/Dialect/Bufferization/TestTensorCopyInsertion.cpp
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
M mlir/test/lib/Dialect/Test/TestTypes.cpp
Log Message:
-----------
[mlir][bufferization] Drop TensorLikeType::getBufferType() (#201350)
Replace TensorLikeType::getBufferType() with
options.unknownTypeConverterFn() hook. Make the hook work with
tensor-like and buffer-like types (instead of builtins) to maintain the
same behaviour at the API boundary level and still allow user types to
be properly supported.
Historically, an attempt to support user types within the one-shot
bufferization framework was made. As part of it,
TensorLikeType::getBufferType() was introduced to allow user-provided
types to customize bufferization. However, the whole affair proved to be
overly complex: there is an interface with customization points for
user-provided tensors, and options-based (not sufficient) implementation
for builtin tensors. On top of this, there was always a
function-specific hook to customize function-level behaviour further. As
a result of this, users would need to implement two different mechanisms
on their end: interface implementation + option hooks.
It seems more reasonable at this stage to thus drop the interface part
and just allow unknown type conversion hook to be used directly. That
way, users would only need to supply that hook themselves (with the
caveat of having to perform a type dispatch inside of the hook).
As a drive by, multiple tests that exercise the usage of custom tensor
type (e.g. !test.test_tensor) are moved to work on top of a test pass.
Default memory space inference hook is also updated to work on top of
tensor-like type to align the signature to the unknown type conversion.
Note for LLVM integration:
* Implementation(s) of `TensorLikeType::getBufferType()` for
(user-provided) tensor types should now be moved into a user-specified
`BufferizationOptions::unknownTypeConverterFn()` hook
* In case upstream one-shot-bufferization pass was used to bufferize IR
with user types, such a setup would likely fail now, since a fallback to
type-based bufferization can now only be set through bufferization
options, and cannot be configured at the upstream pass level. One needs
to create a new pass that sets up the necessary bufferization hooks and
calls one-shot-bufferization infrastructure manually.
Commit: f704a92281ee2ff741fa94048970ac6dea19a1b6
https://github.com/llvm/llvm-project/commit/f704a92281ee2ff741fa94048970ac6dea19a1b6
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/test/CodeGenHLSL/ArrayAssignable.hlsl
M clang/test/CodeGenHLSL/ArrayAssignable.logicalptr.hlsl
M clang/test/CodeGenHLSL/cbuffer-matrix-layout-keyword.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer-empty-struct-array.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_and_namespaces.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_with_packoffset.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_with_static_global_and_function.hlsl
M clang/test/CodeGenHLSL/resources/default_cbuffer.hlsl
M clang/test/CodeGenHLSL/resources/default_cbuffer_with_layout.hlsl
M llvm/include/llvm/Frontend/HLSL/CBuffer.h
M llvm/lib/Frontend/HLSL/CBuffer.cpp
M llvm/lib/Target/DirectX/DXILCBufferAccess.cpp
M llvm/lib/Target/SPIRV/SPIRVCBufferAccess.cpp
R llvm/test/CodeGen/DirectX/cbuffer_global_elim.ll
R llvm/test/CodeGen/SPIRV/cbuffer_global_elim.ll
Log Message:
-----------
Revert "[HLSL] Set visibility of cbuffer global variables to internal" (#202538)
Reverts llvm/llvm-project#200312
Breaks several buildbots, e.g.,
https://lab.llvm.org/buildbot/#/builders/203/builds/48531
Co-authored-by: Nikolas Klauser <nikolasklauser at berlin.de>
Commit: 00e3e6f4cbbba60ddfcd648269dd5f2e8d799cbc
https://github.com/llvm/llvm-project/commit/00e3e6f4cbbba60ddfcd648269dd5f2e8d799cbc
Author: Xiaomeng Zhang <zhangxiaomeng at hygon.cn>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/Basic/Targets/X86.cpp
M clang/test/CodeGen/target-builtin-noerror.c
M clang/test/Driver/x86-march.c
M clang/test/Frontend/x86-target-cpu.c
M clang/test/Misc/target-invalid-cpu-note/x86.c
M clang/test/Preprocessor/predefined-arch-macros.c
M compiler-rt/lib/builtins/cpu_model/x86.c
M llvm/include/llvm/TargetParser/Host.h
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/TargetParser/X86TargetParser.h
M llvm/lib/Target/X86/X86.td
A llvm/lib/Target/X86/X86ScheduleC864GM4.td
A llvm/lib/Target/X86/X86ScheduleC864GM7.td
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/test/CodeGen/X86/bypass-slow-division-64.ll
M llvm/test/CodeGen/X86/cmp16.ll
A llvm/test/CodeGen/X86/cpus-hygon.ll
M llvm/test/CodeGen/X86/rdpru.ll
M llvm/test/CodeGen/X86/slow-unaligned-mem.ll
M llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
M llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll
M llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
M llvm/test/MC/X86/x86_long_nop.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-adx.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-aes.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-avx1.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-avx2.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-bmi1.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-bmi2.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-clflushopt.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-clzero.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-cmov.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-cmpxchg.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-f16c.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-fma.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-fsgsbase.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-lea.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-lzcnt.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-mmx.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-movbe.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-mwaitx.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-pclmul.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-popcnt.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-prefetchw.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-rdrand.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-rdseed.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sha.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse1.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse2.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse3.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse41.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse42.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse4a.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-ssse3.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-x86_32.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-x86_64.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-x87.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-xsave.s
A llvm/test/tools/llvm-mca/X86/C864GM4/zero-idioms.s
A llvm/test/tools/llvm-mca/X86/C864GM7/independent-load-stores.s
A llvm/test/tools/llvm-mca/X86/C864GM7/partially-overlapping-group-resources.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-adx.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-aes.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx1.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx2.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bitalg.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bitalgvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bw.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bwvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512cd.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512cdvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512dq.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512dqvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512gfni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512gfnivl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512ifma.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512ifmavl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vaes.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vaesvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi2.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi2vl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmivl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vnni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vnnivl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vp2intersect.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vp2intersectvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpclmulqdq.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpclmulqdqvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpopcntdq.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpopcntdqvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avxgfni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avxvnni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-bmi1.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-bmi2.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-clflushopt.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-clwb.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-cmov.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-cmpxchg.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-f16c.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-fma.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-fsgsbase.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-gfni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-lea.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-lzcnt.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-mmx.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-movbe.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-mwaitx.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-pclmul.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-popcnt.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-prefetchw.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-rdrand.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-rdseed.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sha.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse1.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse2.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse3.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse41.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse42.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse4a.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-ssse3.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-vaes.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-vpclmulqdq.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-x86_32.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-x86_64.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-x87.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-xsave.s
A llvm/test/tools/llvm-mca/X86/C864GM7/zero-idioms.s
Log Message:
-----------
[X86] Hygon Processors Initial enablement (#187622)
This patch adds initial support for several Hygon architectures.
The Hygon architectures include:
- c86-4g-m4
- c86-4g-m6
- c86-4g-m7
This patch includes:
- Added Hygon architectures CPU targets recognition in Clang and LLVM
- Added Hygon architectures to target parser and host CPU detection
- Updated compiler-rt CPU model detection for Hygon architectures
- Added Hygon architectures to various optimizer tests
- Added scheduler models for Hygon architectures CPU targets
Commit: 11cf29581486565b04767ce313602312824d0109
https://github.com/llvm/llvm-project/commit/11cf29581486565b04767ce313602312824d0109
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/tools/llvm-exegesis/lib/Assembler.h
Log Message:
-----------
Revert "[NFC][llvm-exegesis] Disable CFI-icall for JIT-executed function" (#202571)
Reverts llvm/llvm-project#202472
Commit: a1c1cdd44b372c08125d2b6a4aa445620cd284a3
https://github.com/llvm/llvm-project/commit/a1c1cdd44b372c08125d2b6a4aa445620cd284a3
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/AlignmentFromAssumptions.cpp
M llvm/test/Transforms/AlignmentFromAssumptions/simple.ll
Log Message:
-----------
[AlignmentFromAssumes] Skip huge alignment (#202567)
Fixes https://github.com/llvm/llvm-project/issues/202043
Though `align` on huge alignment is not supported, the case below
confirms we allow huge alignment in `assume`:
https://github.com/llvm/llvm-project/blob/c4f4206ff3ab97db9577f11bb2dabd40896bcca9/llvm/test/Transforms/InstCombine/assume.ll#L71
In this case, we should skip huge alignment in AlignmentFromAssumes.
Commit: 0f8a3b23f1e1ffe69d6d49576347ea967ec611be
https://github.com/llvm/llvm-project/commit/0f8a3b23f1e1ffe69d6d49576347ea967ec611be
Author: Anshul Nigham <nigham at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-and.mir
M llvm/test/CodeGen/AArch64/GlobalISel/opt-overlapping-and-postlegalize.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combine-ptr-add-chain.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-hoist-same-hands.mir
Log Message:
-----------
[NewPM][AArch64][GlobalISel] Port AArch64PostLegalizerCombiner to NewPM (#194156)
Adds a standard porting.
Updates some (but not all) tests to verify the NewPM path is working.
Commit: 85ab77340528a7d2e03595aa43c42fcb6105f650
https://github.com/llvm/llvm-project/commit/85ab77340528a7d2e03595aa43c42fcb6105f650
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
A llvm/test/Transforms/InstCombine/issue173148-sext-phi-select-infloop.ll
Log Message:
-----------
[InstCombine] Fix infinite combine loop in evaluateInDifferentType (#202572)
The implementation assumes that all original uses inside visited
instructions would get removed as part of changing the type. However,
this is not true for uses in select conditions, as only the value
operands change type in that case. Bail out if we encounter uses in
select conditions to avoid this.
Fixes https://github.com/llvm/llvm-project/issues/173148.
Commit: 9dfcf7663b1604ae5ced030a69e2be0e93632d5e
https://github.com/llvm/llvm-project/commit/9dfcf7663b1604ae5ced030a69e2be0e93632d5e
Author: Fangrui Song <i at maskray.me>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/docs/ProgrammersManual.rst
M llvm/include/llvm/ADT/StringMap.h
M llvm/lib/Support/StringMap.cpp
M llvm/unittests/ADT/StringMapTest.cpp
M llvm/utils/gdb-scripts/prettyprinters.py
Log Message:
-----------
[StringMap] Replace tombstone deletion with TAOCP 6.4 Algorithm R (#202103)
StringMap uses quadratic probing with lazy deletion: an erased entry
becomes a tombstone, a third bucket state alongside empty and live that
every find/insert must inspect.
Switch to linear probing with Knuth TAOCP 6.4 Algorithm R deletion,
similar to DenseMap #200595.
erase now relocates the following entries to close the hole. StringMap
buckets are pointers to heap-allocated entries, so only the pointers
(and the parallel hash array) move. References and pointers to entries
remain valid, but iterators are invalidated.
Depends on #202237 and #202520
Aided by Claude Opus 4.8
Commit: ca227bff07085250e3a146dadf2ea3246d8b23a8
https://github.com/llvm/llvm-project/commit/ca227bff07085250e3a146dadf2ea3246d8b23a8
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
Log Message:
-----------
[AMDGPU] Produce ballot/icmp/fcmp lane masks at wavefront width (#201358)
Commit: f7e4167f816ac8c5a6e553c66f3b90fe040d1362
https://github.com/llvm/llvm-project/commit/f7e4167f816ac8c5a6e553c66f3b90fe040d1362
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
Log Message:
-----------
[AMDGPU] Clamp load_monitor scope to minimum SCOPE_SE (#198245)
The load_monitor instructions monitor L2 cache lines and therefore
require at least SCOPE_SE to ensure the L2 cache is hit. The current
memory model requires the user to ensure that the specified scope is
such that it results in at least SCOPE_SE, otherwise the behaviour is
undefined. Instead, we now clamp the emitted scope at a minimum of
SCOPE_SE, so that the undefined behaviour is converted into a
performance loss instead.
Assisted-By: Claude Opus 4.6
Commit: 323285f141535bfa8607f773c814000dd4f69e98
https://github.com/llvm/llvm-project/commit/323285f141535bfa8607f773c814000dd4f69e98
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-vectorized-later.ll
Log Message:
-----------
[SLP] Update test against const-folding (#202532)
223ef1f3 ([IRBuilder] ConstFold unary intrinsics, #200496) made a lot of
test updates to SLPVectorizer. The tests were written a long time ago,
and it is unclear what their intent was, but at least update the one
test to replace constants with arguments, where the intent is clear.
Commit: 7581dc5a298dd1736c84ff21fbc310d40901a894
https://github.com/llvm/llvm-project/commit/7581dc5a298dd1736c84ff21fbc310d40901a894
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/unions.cpp
Log Message:
-----------
[clang][bytecode] Fix an assertion failure in visitDtorCall() (#202507)
In `emitDestructionPop()`, we assert that the Descriptor has a
non-trivial dtor. Check this first here so we don't do all this work for
nothing.
Commit: 057a1fe9bd5b3c72ea6d65c456d1266fc20d8e33
https://github.com/llvm/llvm-project/commit/057a1fe9bd5b3c72ea6d65c456d1266fc20d8e33
Author: anjenner <161845516+anjenner at users.noreply.github.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
Log Message:
-----------
[AMDGPU][GISel] Add register bank legalization rules for amdgcn_raw_buffer_load_async_lds (#201406)
Also amdgcn_struct_buffer_load_async_lds,
amdgcn_raw_ptr_buffer_load_async_lds, and
amdgcn_struct_ptr_buffer_load_async_lds.
Commit: 271c8b75cde53d78da5ce971ced8694cca149749
https://github.com/llvm/llvm-project/commit/271c8b75cde53d78da5ce971ced8694cca149749
Author: Vinit Deodhar <vadeodhar89 at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgEnums.td
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
M mlir/test/Dialect/Linalg/roundtrip-morphism-linalg-category-ops.mlir
M mlir/test/Dialect/Linalg/specialize-generic-ops.mlir
Log Message:
-----------
[mlir][linalg] Add sin, cos, tan to elementwise operations (#200950)
Add sin, cos, and tan as UnaryFn entries in the linalg dialect, enabling
their use via linalg.elementwise, named ops (linalg.sin, linalg.cos,
linalg.tan), and specialization from linalg.generic.
---------
Co-authored-by: Vinit Deodhar <vinitdeodhar at users.noreply.github.com>
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
Co-authored-by: Vinit Deodhar <vdeodhar at ah-vdeodhar-l.dhcp.mathworks.com>
Commit: 9129363adbcc3474639e2a3b2b263905da1f86ca
https://github.com/llvm/llvm-project/commit/9129363adbcc3474639e2a3b2b263905da1f86ca
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
Log Message:
-----------
[GlobalISel] Use more inline elements in a match table SmallVector (#202568)
The 4 inline elements for OnFailResumeAt only cover 36.8% (33455 / 90902) of
aarch64-isel executeMatchTable invocations encountered while compiling sqlite3
on aarch64-O0-g.
The 8 inline elements cover 100% (maximum observed depth was 6). Small -0.09%
CTMark geomean improvement on aarch64-O0-g.
https://llvm-compile-time-tracker.com/compare.php?from=2de2edb943fe1b83d79bdffa03606eb8c5452e9b&to=8deb4f949b5f80a26a8a61775fb411bf30fefd80&stat=instructions%3Au
Assisted-by: codex
Commit: 54d5646b0d70e3a198817c61c40ba0226a66bf29
https://github.com/llvm/llvm-project/commit/54d5646b0d70e3a198817c61c40ba0226a66bf29
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/test/SemaCXX/attr-section.cpp
Log Message:
-----------
[Sema] Add original GH192264 reproducer as a section-conflict regression test (#202276)
Follow up of https://github.com/llvm/llvm-project/pull/200873
Commit: 8b0223858b1e15a4310de18445d972e7648b740f
https://github.com/llvm/llvm-project/commit/8b0223858b1e15a4310de18445d972e7648b740f
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
M clang/include/clang/Sema/SemaAMDGPU.h
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/test/CodeGen/amdgpu-builtin-is-invocable.c
M clang/test/CodeGen/amdgpu-builtin-processor-is.c
M clang/test/CodeGen/link-builtin-bitcode.c
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
A clang/test/CodeGenOpenCL/builtins-amdgcn-global-load-store.cl
A clang/test/SemaHIP/amdgpu-av-load-store.hip
A clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-error.cl
A clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-target-error.cl
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
Log Message:
-----------
[AMDGPU][Clang] add __builtin_amdgcn_av_(load|store)_b128 (#199176)
These builtins allow the program to request store-available and
load-visible accesses as described in #191246. Each of them takes a
__MEMORY_SCOPE_* operand that is then translated to target-specific
cache policy bits.
This patch was extracted from #172090.
Co-authored-by: macurtis-amd <macurtis at amd.com>
Assisted-by: Claude Opus 4.6
---------
Co-authored-by: macurtis-amd <macurtis at amd.com>
Commit: 88caf8ef2bd61005e854952b8a1e699aa72347d8
https://github.com/llvm/llvm-project/commit/88caf8ef2bd61005e854952b8a1e699aa72347d8
Author: Erik Enikeev <evonatarius at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
M llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
M llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll
M llvm/test/CodeGen/PowerPC/spe.ll
Log Message:
-----------
Reland "[PowerPC] set libcall lowering for fp setcc ops on SPE boards" (#199198)
This is a reland of 4d0100789dc9b4db7d77c033d8f53f8b7dc68437, which was
reverted by c24ab4c814f680c5ac71600bf80d551123abd84d.
The functionality is unchanged from the original patch. This version
only fixes the fast-math flag propagation issue by passing `SDNodeFlags`
explicitly to `DAG.getSetCC()` (same as #199105 which was closed because
the underlying patch had been reverted).
Commit: 59e1338da9e97be33e19dbe0b0cda46a9eefe834
https://github.com/llvm/llvm-project/commit/59e1338da9e97be33e19dbe0b0cda46a9eefe834
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Strip Ctx arg from tryToFoldLiveIns (NFC) (#202559)
We get the Plan anyway, so the context doesn't need to be passed
separately.
Commit: b1880a09469217aab192ded75643f860fb3d55a8
https://github.com/llvm/llvm-project/commit/b1880a09469217aab192ded75643f860fb3d55a8
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVBaseInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
A llvm/lib/Target/SPIRV/SPIRVAuxDataHandler.cpp
A llvm/lib/Target/SPIRV/SPIRVAuxDataHandler.h
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-all-function-attributes.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-all-function-metadata-debug.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-all-function-metadata.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-auxdata-requires-extension.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-auxdata.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-gv-attributes.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-gv-metadata.ll
A llvm/test/CodeGen/SPIRV/linkage/available-externally-function.ll
A llvm/test/CodeGen/SPIRV/linkage/available-externally-global.ll
M llvm/test/CodeGen/SPIRV/linkage/linkage-types.ll
Log Message:
-----------
[SPIR-V] Add NonSemantic.AuxData emission (-spirv-preserve-auxdata) (#200002)
Add a NonSemantic.AuxData extended instruction set to the SPIR-V
backend, matching SPIRV-LLVM-Translator's --spirv-preserve-auxdata wire
format
- `-spirv-preserve-auxdata` emits LLVM attributes and metadata as
NonSemantic.AuxData records (requires SPV_KHR_non_semantic_info).
- `available_externally` functions keep their linkage via an AuxData
linkage record, emitted unconditionally.
Commit: 97b131ec4a7e021c45586a37832d380c0c16ce1c
https://github.com/llvm/llvm-project/commit/97b131ec4a7e021c45586a37832d380c0c16ce1c
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
Log Message:
-----------
[AMDGPU][NFC] Add atomic optimization tests for gfx13 (#201299)
Commit: dae2935b32a673557e7060f8e90e73eaae4d6199
https://github.com/llvm/llvm-project/commit/dae2935b32a673557e7060f8e90e73eaae4d6199
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/memcpy.align.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/memmove.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll
Log Message:
-----------
[SPIR-V] Drop constant zero-sized memcpy/memmove/memset before selection (#201904)
A constant zero Size operand is invalid for OpCopyMemorySized, and these
intrinsics are no-ops, so erase them instead of lowering
Commit: 70b68dff845403f62d77f42850ac779a78662272
https://github.com/llvm/llvm-project/commit/70b68dff845403f62d77f42850ac779a78662272
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
Log Message:
-----------
[AMDGPU] Fix si-optimize-exec-masking stepping into debug values (#201947)
Summary:
This pass tries to step between register uses and would try to enter a
debug instruction if it managed to get between them.
Commit: 13b28db64845fc9fe7431338d5dc8919b28a6022
https://github.com/llvm/llvm-project/commit/13b28db64845fc9fe7431338d5dc8919b28a6022
Author: CarolineConcatto <caroline.concatto at arm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.td
M llvm/test/TableGen/target-mem-intrinsic-attrs.td
M llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
Log Message:
-----------
[TableGen] Add ArgMem memory location (#201597)
This will allow to use IntrRead/IntrWrite with ArgMem. So this:
```
[IntrWriteMem , IntrInaccessibleMemOrArgMemOnly]
```
could become this:
```
[IntrWriteMem, IntrWrite<[ArgMem, InaccessibleMem]>]
```
Commit: 53870f797be01f586078c1f129d05325c83a3143
https://github.com/llvm/llvm-project/commit/53870f797be01f586078c1f129d05325c83a3143
Author: Arnav Mundada <arnav.dev.mail at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libc/include/math.yaml
Log Message:
-----------
[libc][math] Add missing math function entries dfmal,dfmaf128 to math.yaml (#199485)
Part of https://github.com/llvm/llvm-project/issues/199266
Added missing math function entries to `libc/include/math.yaml`:
- dfmaf128
- dfmal
Commit: ee39c604feff48ce4b5396f8a7c51da86768479b
https://github.com/llvm/llvm-project/commit/ee39c604feff48ce4b5396f8a7c51da86768479b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/docs/Multilib.rst
M clang/docs/ReleaseNotes.rst
M clang/lib/Driver/ToolChains/MSVC.cpp
A clang/test/Driver/Inputs/multilib_msvc_tree/bin/.keep
A clang/test/Driver/Inputs/multilib_msvc_tree/include/x86_64-pc-windows-msvc/.keep
A clang/test/Driver/Inputs/multilib_msvc_tree/include/x86_64-pc-windows-msvc/debug/.keep
A clang/test/Driver/Inputs/multilib_msvc_tree/include/x86_64-pc-windows-msvc/noexcept/.keep
A clang/test/Driver/Inputs/multilib_msvc_tree/include/x86_64-pc-windows-msvc/release/.keep
A clang/test/Driver/msvc-multilib.yaml
M clang/test/Driver/print-multi-selection-flags.c
Log Message:
-----------
[Clang] Support multilibs on Windows (#200212)
Summary:
This was pushed to a follow-up, and I think the previous has lingered
long enough to expand this to Windows. the per-target runtime directory
this uses is default-off, but nothing stops us from just providing this.
The interest in this is for ROCm builds on Windows to be able to provide
asan / debug builds the same way on Linux.
Commit: 9c54c82d80271c326535f73064a8763d0c730a59
https://github.com/llvm/llvm-project/commit/9c54c82d80271c326535f73064a8763d0c730a59
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lldb/docs/resources/lldbgdbremote.md
M lldb/include/lldb/Host/ProcessLaunchInfo.h
M lldb/include/lldb/Host/windows/PseudoConsole.h
M lldb/include/lldb/Utility/StringExtractorGDBRemote.h
M lldb/source/Host/common/ProcessLaunchInfo.cpp
M lldb/source/Host/windows/PseudoConsole.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.h
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Utility/StringExtractorGDBRemote.cpp
Log Message:
-----------
[lldb][gdb-remote] Forward client terminal size to lldb-server (#201141)
Add a new gdb-remote packet, `QSetSTDIOWindowSize:cols=N;rows=N`, to
send the dimension of the terminal to the debuggee.
On Windows, the ConPTY emulates a PTY. The client's terminal (the one
the user is running lldb from) has to match the dimensions of the ConPTY
so that the debuggee (which is attached to the ConPTY) gets proper
terminal emulation. If there is a mismatch, lines will not wrap at the
right column and VT sequences will be out of place. In practice, in
lldb, this results in the `(lldb)` prompt being overwritten by the
stdout of the debuggee.
This patch forwards the dimension of the client (the terminal lldb.exe
is running in) to the ConPTY (opened by the server) so that the
dimensions of the client's terminal match the ones of the ConPTY.
As an example, here is the opposite case where the terminal does not
have dimensions (the vscode debug console) and the ConPTY still has
finite dimensions: https://github.com/llvm/llvm-project/pull/186472.
This is a follow up to:
- https://github.com/llvm/llvm-project/pull/201124
Commit: 5ec036aba1243801320611f23f644707496e69c9
https://github.com/llvm/llvm-project/commit/5ec036aba1243801320611f23f644707496e69c9
Author: David Green <david.green at arm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/test/CodeGen/AArch64/ldst-opt-umov-fpr-store.mir
Log Message:
-----------
[AArch64] Protect against mismatching sizes in UMOV combine. (#202116)
This fixes an issue from #199139 where a later revision was not checking
the connection between the size of the UMOV and the size of the store.
This adds a check, based on the register sizes and the memory size from
the MMO.
Commit: 67e3b31450012b939980fc91075d0ab0b035f284
https://github.com/llvm/llvm-project/commit/67e3b31450012b939980fc91075d0ab0b035f284
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M compiler-rt/cmake/caches/AMDGPU.cmake
M compiler-rt/cmake/caches/NVPTX.cmake
M compiler-rt/cmake/caches/SPIRV64.cmake
Log Message:
-----------
[compiler-rt] Fix misspelled variable name in GPU caches (#202604)
Summary:
This likely didn't do anything, but it's best for things to be spelled
right.
Commit: 4662e7136d02accfeb11f5255eb1bcae10cff7ed
https://github.com/llvm/llvm-project/commit/4662e7136d02accfeb11f5255eb1bcae10cff7ed
Author: David Green <david.green at arm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/ldexp.ll
Log Message:
-----------
[AArch64][GlobalISel] BF16 libcalls operations. (#200740)
This fills in a number of bf16 instructions that lower through f32
libcall.
Commit: 85d4138c12cd1eae0eb7083279ca7b0b26cd15b1
https://github.com/llvm/llvm-project/commit/85d4138c12cd1eae0eb7083279ca7b0b26cd15b1
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libsycl/CMakeLists.txt
A libsycl/cmake/Modules/AddUnitTest.cmake
M libsycl/docs/index.rst
M libsycl/src/CMakeLists.txt
M libsycl/src/detail/device_kernel_info.hpp
M libsycl/src/detail/program_manager.cpp
M libsycl/src/detail/program_manager.hpp
A libsycl/unittests/CMakeLists.txt
A libsycl/unittests/common/device_images.hpp
A libsycl/unittests/mock/CMakeLists.txt
A libsycl/unittests/mock/helpers.cpp
A libsycl/unittests/mock/helpers.hpp
A libsycl/unittests/mock/mock.cpp
A libsycl/unittests/platform/CMakeLists.txt
A libsycl/unittests/platform/get_platforms.cpp
A libsycl/unittests/program_manager/CMakeLists.txt
A libsycl/unittests/program_manager/register_and_unregister.cpp
A libsycl/unittests/queue/CMakeLists.txt
A libsycl/unittests/queue/queue.cpp
Log Message:
-----------
[libsycl] Add UT build and min test set (#199915)
This PR was assisted by GH Copilot (replication of base mock functions
according to my example, fake device image helpers).
---------
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: cbfe4adc92bc0c9680285e9a47201f0ff68c9b66
https://github.com/llvm/llvm-project/commit/cbfe4adc92bc0c9680285e9a47201f0ff68c9b66
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/test/CodeGen/SPIRV/pointers/getelementptr-empty-struct.ll
Log Message:
-----------
[SPIR-V] Fix infinite loop on GEP handling for an empty struct (#202587)
Commit: 431a821cbbb66f89d0cd7d97c6eb7792801fd90e
https://github.com/llvm/llvm-project/commit/431a821cbbb66f89d0cd7d97c6eb7792801fd90e
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/logical-memcpy.inline.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/memcpy.inline.ll
Log Message:
-----------
[SPIRV] Add support for selection of G_MEMCPY_INLINE (#201925)
`G_MEMCPY_INLINE` is the same as `G_MEMCPY` but it's supposed to
guarantee the instruction will not be lowered to an external function
call. This is useful for projects like `libc`.
In SPIR-V, we would never lower to an external function call, we always
lower `G_MEMCPY` to `OpCopyMemory` or `OpCopyMemorySized`, or the copy
is optimized out, so we should be able to handle `G_MEMCPY_INLINE` and
`G_MEMCPY` the same.
Co-Authored-By: Claude Opus 4.8
[noreply at anthropic.com](mailto:noreply at anthropic.com)
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Co-authored-by: Claude Opus 4.8 <noreply at anthropic.com>
Commit: 3f28ade7a938f410baa061c4fe0c69a98dd58281
https://github.com/llvm/llvm-project/commit/3f28ade7a938f410baa061c4fe0c69a98dd58281
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/SPIRV/concat-vectors.ll
Log Message:
-----------
[SPIRV] Support selection of G_CONCAT_VECTORS (#201686)
Implement the G_CONCAT_VECTOR opcode using `OpCompositeConstruct`. The
semantics are similar so the implementation is straightforward.
This opcode being generated is somewhat rare, in this case it seems to
have remained due to the non-power of 2 vector length ABI.
Co-Authored-By: Claude Opus 4.8 <noreply at anthropic.com>
Co-authored-by: Claude Opus 4.8 <noreply at anthropic.com>
Commit: 45f6ab064f881334affa6ff5e3b3cb056cde67cb
https://github.com/llvm/llvm-project/commit/45f6ab064f881334affa6ff5e3b3cb056cde67cb
Author: Sergey Semenov <sergey.semenov at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libsycl/src/detail/program_manager.cpp
Log Message:
-----------
[libsycl] Fix _LIBSYCL_EXPORT placement (#201364)
Fixes another instance of _LIBSYCL_EXPORT causing compiilation errors on
Windows.
Commit: 4d7ba1f5ef6402183372e2ea6358c53a9c182868
https://github.com/llvm/llvm-project/commit/4d7ba1f5ef6402183372e2ea6358c53a9c182868
Author: Drew Kersnar <dkersnar at nvidia.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/IR/Instructions.cpp
M llvm/test/Transforms/InstCombine/addrspacecast.ll
Log Message:
-----------
[IR] Preserve pointer-byte bitcasts around addrspacecast (#202454)
This fixes cast-pair elimination for addrspacecast combined with
pointer/byte bitcast.
The LLVM LangRef defines [bN byte
types](https://llvm.org/docs/LangRef.html#byte-type) as raw memory data
in SSA registers, where each bit may be an integer bit, part of a
pointer value, or poison.
The LangRef permits pointer-to-byte bitcast: the [bitcast .. to
instruction](https://llvm.org/docs/LangRef.html#bitcast-to-instruction)
says that if the source type is a pointer, the destination type must be
a pointer or a byte/vector-of-bytes type of the same size.
The same [bitcast .. to
section](https://llvm.org/docs/LangRef.html#bitcast-to-instruction) also
defines byte-to-pointer behavior: when the destination type is a pointer
type, a byte value whose bits all come from the same correctly ordered
pointer produces that pointer; otherwise it produces a pointer with the
address encoded by the input and no provenance.
By contrast, [addrspacecast ..
to](https://llvm.org/docs/LangRef.html#addrspacecast-to-instruction) is
only valid from a pointer or vector-of-pointers value to a pointer type
in a different address space.
So these two-step sequences are valid:
```
%p = addrspacecast ptr addrspace(1) %x to ptr
%b = bitcast ptr %p to b64
```
```
%p = bitcast b64 %x to ptr
%q = addrspacecast ptr %p to ptr addrspace(1)
```
But they cannot be folded into a single addrspacecast, because that
would require addrspacecast to cast directly to or from bN, which the
LangRef does not allow.
This patch prevents cast-pair elimination from performing those invalid
folds and adds InstCombine regression coverage for both directions. Both
tests crashed before this patch. This patch was created with the
assistance of AI, based on a real case I found while working on
https://github.com/llvm/llvm-project/pull/177908. I'm pretty sure I'm
reading the langref correctly, but please let me know if I am mistaken.
Commit: 26c72f1b4d375a7dc93df4435b012c221f4ae902
https://github.com/llvm/llvm-project/commit/26c72f1b4d375a7dc93df4435b012c221f4ae902
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for tensor load/store to lds (#202363)
Commit: 727ad9a21d32f19dd0fdf26b39a9c6a064692287
https://github.com/llvm/llvm-project/commit/727ad9a21d32f19dd0fdf26b39a9c6a064692287
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[AMDGPU] Add a feature for VOP3PX2 instructions incrementing VA_VDST twice (#202613)
Commit: 1723b7a301450d7000fe3a86e48adb9f9794d1e9
https://github.com/llvm/llvm-project/commit/1723b7a301450d7000fe3a86e48adb9f9794d1e9
Author: Srividya Sundaram <srividya.sundaram at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/Frontend/CompilerInvocation.cpp
R clang/test/CodeGenSYCL/filescope_asm.c
A clang/test/CodeGenSYCL/filescope_asm.cpp
M clang/test/Driver/offload-target.c
M clang/test/Driver/sycl.cpp
A clang/test/Frontend/sycl-c-input-error.cpp
M clang/test/Headers/__cpuidex_conflict.c
M clang/test/SemaSPIRV/BuiltIns/generic_cast_to_ptr_explicit.c
M clang/test/SemaSPIRV/BuiltIns/ids_and_ranges.c
M clang/test/SemaSPIRV/BuiltIns/subgroup-errors.c
M clang/unittests/Frontend/CompilerInvocationTest.cpp
Log Message:
-----------
[SYCL] Error on C inputs when compiling with -fsycl (#200318)
`SYCL` is a `C++`-based programming model and requires `C++` source
files.
Enforce this invariant in the frontend by rejecting `C` inputs when SYCL
mode is active, ensuring that `LangOpts.SYCL` implies
`LangOpts.CPlusPlus` regardless of how the compiler is invoked.
Commit: 6c706ed5896d10b2a900d5860b80851f01cfe943
https://github.com/llvm/llvm-project/commit/6c706ed5896d10b2a900d5860b80851f01cfe943
Author: xys-syx <xuyuansui at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Dialect/LLVMIR/nvvm.mlir
M mlir/test/Target/LLVMIR/nvvm/barrier.mlir
Log Message:
-----------
[MLIR][NVVM] Add explicit aligned attribute to nvvm.barrier and nvvm.barrier.reduction (#200745)
This PR according to the third PR commitments in #192203
This PR adds an explicit aligned boolean attribute to `nvvm.barrier`,
defaulting to true to preserve the existing semantic default, and
extends the op's LLVM IR lowering to pick between the `.aligned` and
non-`.aligned` spellings of the `@llvm.nvvm.barrier.cta.*` intrinsic
family.
Notes on using `BoolAttr` instead of UnitAttr: `nvvm.barrier`'s existing
lowering always emits an aligned intrinsic variant. Making aligned a
BoolAttr with default true captures that as the op's default, and the
`custom<Aligned>` described below only emits the keyword when
non-default.
(I am not able to merge branches, please help me)
Commit: 859ee9d83ef227848a98c5948f887574f5e7420c
https://github.com/llvm/llvm-project/commit/859ee9d83ef227848a98c5948f887574f5e7420c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.h
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
M clang/lib/Driver/ToolChains/HIPSPV.cpp
M clang/lib/Driver/ToolChains/HIPSPV.h
M clang/test/Driver/amdgpu-openmp-sanitize-options.c
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/hip-binding.hip
M clang/test/Driver/hip-device-compile.hip
M clang/test/Driver/hip-offload-compress-zlib.hip
M clang/test/Driver/hip-offload-compress-zstd.hip
M clang/test/Driver/hip-phases.hip
M clang/test/Driver/hip-rdc-device-only.hip
M clang/test/Driver/hip-sanitize-options.hip
M clang/test/Driver/hip-save-temps.hip
M clang/test/Driver/hip-spirv-backend-bindings.c
M clang/test/Driver/hip-spirv-backend-opt.c
M clang/test/Driver/hip-spirv-backend-phases.c
M clang/test/Driver/hip-spirv-linker-crash.c
M clang/test/Driver/hip-target-id.hip
M clang/test/Driver/hip-toolchain-device-only.hip
M clang/test/Driver/hip-toolchain-no-rdc.hip
M clang/test/Driver/hip-toolchain-rdc-flto-partitions.hip
M clang/test/Driver/hip-toolchain-rdc-separate.hip
M clang/test/Driver/hip-toolchain-rdc-static-lib.hip
M clang/test/Driver/hip-toolchain-rdc.hip
M clang/test/Driver/hip-unbundle-preproc.hipi
M clang/test/Driver/hipspv-toolchain-rdc-separate.hip
M clang/test/Driver/hipspv-toolchain-rdc.hip
M clang/test/Driver/hipspv-toolchain.hip
M clang/test/Driver/openmp-offload-gpu.c
M clang/test/Driver/spirv-amd-toolchain.c
M clang/test/Driver/spirv-openmp-toolchain.c
Log Message:
-----------
[Clang] Set default LTO mode for AMDGCN/SPIR-V targets to full (#201457)
Summary:
Previously we had several layers of if conditions that functionally
amounted to pretending like we were in LTO-mode. The previous changes
moved the LTO settings into the toolchain so we can now override it for
our offloading toolchains. This allows us to respect the LTO mode, where
previously there was no way to override it.
The main artifact of this PR should be trimming up the massive if
statement.
Some slight by-products on the old-driver path, but this can be
recovered with `-fno-offload-lto` and the old driver should be deleted
in a few months anyways.
Commit: f8b0120edb7f19b30870462299e5f7eb0e40f656
https://github.com/llvm/llvm-project/commit/f8b0120edb7f19b30870462299e5f7eb0e40f656
Author: Rose Hudson <rose.hudson at sony.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/lib/Driver/ToolChains/PS4CPU.h
M clang/test/Driver/ps4-ps5-toolchain.c
Log Message:
-----------
[Clang][Driver] default-on include path backslash warning on PS5 (#202300)
It seems like there is precedent for using addClangWarningOptions in the
driver to set warning default states per-target, in e.g. AMDGPU.
These warnings are usually disabled by default to avoid overdiagnosing
common patterns on Windows host+target builds which don't care about
portability. Since PS5 builds are cross-compiled it makes less sense to
assume things about the host, so we want to diagnose portability issues
more eagerly.
Commit: 2ae3fa77da6c393c5b47ced09b6d91551d178b57
https://github.com/llvm/llvm-project/commit/2ae3fa77da6c393c5b47ced09b6d91551d178b57
Author: Nuri Amari <nuri.amari99 at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lld/MachO/Driver.cpp
M lld/docs/ReleaseNotes.rst
R lld/test/MachO/lc-linker-option-order.ll
A lld/test/MachO/lc-linker-option-postprocess.ll
A lld/test/MachO/lc-linker-option-sort.ll
Log Message:
-----------
[lld-macho] Sort LC_LINKER_OPTIONS before processing (#201604)
Previously https://reviews.llvm.org/D157716 brought handling of
LC_LINKER_OPTIONS closer to Apple linker behavior by processing the
options at the end after all object files have been added.
This corrects another difference in behavior, processing frameworks
before regular libraries (linked with -lFoo), and processing each group
in sorted order.
Processing a LC_LINKER_OPTIONS can trigger loads of more object files
which in turn may have more LC_LINKER_OPTIONS. We iterate this to a
fixed point, walking this graph in BFS order, processing each "level" of
the graph in the order described above. This graph traversal order
hasn't changed in this commit, only the sorting has.
The diff of the linker map produced for the included test before and
after:
```
23,28c23,28
< 0x000003D0 0x00000001 [ 4] _zlib
< 0x000003E0 0x00000001 [ 5] _zed_framework
< 0x000003F0 0x00000001 [ 6] _mlib
< 0x00000400 0x00000001 [ 7] _alpha_framework
< 0x00000410 0x00000001 [ 8] _alib
< 0x00000420 0x00000001 [ 9] _mid_framework
---
> 0x000003D0 0x00000001 [ 4] _alpha_framework
> 0x000003E0 0x00000001 [ 5] _mid_framework
> 0x000003F0 0x00000001 [ 6] _zed_framework
> 0x00000400 0x00000001 [ 7] _alib
> 0x00000410 0x00000001 [ 8] _mlib
> 0x00000420 0x00000001 [ 9] _zlib
```
Apple's linker produces the same order as after.
---------
Co-authored-by: Nuri Amari <nuriamari at fb.com>
Commit: cefb93799312e772f2d71529075bc4ab1b94b845
https://github.com/llvm/llvm-project/commit/cefb93799312e772f2d71529075bc4ab1b94b845
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
A llvm/test/CodeGen/SPIRV/ptrmask-logical.ll
A llvm/test/CodeGen/SPIRV/ptrmask-vec.ll
A llvm/test/CodeGen/SPIRV/ptrmask32.ll
A llvm/test/CodeGen/SPIRV/ptrmask64-32.ll
A llvm/test/CodeGen/SPIRV/ptrmask64.ll
Log Message:
-----------
[SPIRV] Add support for G_PTRMASK (#201450)
This instruction is generated by the
[llvm.ptrmask](https://llvm.org/docs/LangRef.html#llvm-ptrmask-intrinsic)
intrinsic, which is used for Clang builtins like
[__builtin_align_up](https://clang.llvm.org/docs/LanguageExtensions.html#alignment-builtins)
which is used in `libc`.
We are working on building `libc` for SPIR-V, so we hit this problem.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Co-Authored-By: Claude Sonnet 4.5 <noreply at anthropic.com>
---------
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Co-authored-by: Claude Sonnet 4.5 <noreply at anthropic.com>
Commit: f4ecab143affd2c2c7953f58802673152fbd8c4b
https://github.com/llvm/llvm-project/commit/f4ecab143affd2c2c7953f58802673152fbd8c4b
Author: Justin Lebar <justin.lebar at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/test/CodeGen/AArch64/ldexp.ll
A llvm/test/CodeGen/AArch64/powi-ldexp-promote-libcall-error.ll
Log Message:
-----------
[SelectionDAG] Promote FPOWI/FLDEXP exponents where possible, and raise an error otherwise (#200621)
PromoteIntOp_ExpOp is reached when the exponent type is illegal.
- When the exponent type was smaller than int, we'd hit an assertion. In
builds where asserts were disabled, we actually ended up doing the right
thing; makeLibCall would sign-extend the value to int.
- When the exponent type was too large, we'd also hit an assertion. In
builds were asserts were disabled, we would *not* do the right thing;
we'd end up silently truncating the value. Now we explicitly raise an
error.
Commit: 02cd239f7d3d9261af719b38f1afc18c0e9ea6f2
https://github.com/llvm/llvm-project/commit/02cd239f7d3d9261af719b38f1afc18c0e9ea6f2
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for cvt f16<->fp8/bf8 (#202361)
Small types are impemented using integers in LLVMIR,
because of this there are no irtranslator failures.
Commit: a2ec5c68ba8767c5dc1266946663c8715389da66
https://github.com/llvm/llvm-project/commit/a2ec5c68ba8767c5dc1266946663c8715389da66
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M flang/include/flang/Semantics/openmp-utils.h
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/openmp-utils.cpp
M flang/test/Semantics/OpenMP/copyprivate04.f90
M flang/test/Semantics/OpenMP/copyprivate05.f90
M flang/test/Semantics/OpenMP/declare-target01.f90
M flang/test/Semantics/OpenMP/from-clause-v45.f90
M flang/test/Semantics/OpenMP/from-clause-v51.f90
M flang/test/Semantics/OpenMP/in-reduction.f90
M flang/test/Semantics/OpenMP/lastprivate01.f90
M flang/test/Semantics/OpenMP/name-conflict.f90
M flang/test/Semantics/OpenMP/named-constants.f90
M flang/test/Semantics/OpenMP/reduction04.f90
M flang/test/Semantics/OpenMP/reduction16.f90
M flang/test/Semantics/OpenMP/task-reduction.f90
M flang/test/Semantics/OpenMP/to-clause-v45.f90
M flang/test/Semantics/OpenMP/to-clause-v51.f90
Log Message:
-----------
[flang][OpenMP] More detailed checks for argument list items in clauses (#201334)
For clauses that take list of variable, locator, and extended list
items, perform checks that the actual arguments meet the corresponding
requirements. This is version-based, since clause requirements have
changed over time.
Commit: d439dde4e6c0af6126ccb6c222653bfce07ad3d1
https://github.com/llvm/llvm-project/commit/d439dde4e6c0af6126ccb6c222653bfce07ad3d1
Author: Lucas Chollet <lucas.chollet at serenityos.org>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/test/CodeGen/zero-call-used-regs.c
M llvm/test/CodeGen/AArch64/zero-call-used-regs.ll
M llvm/test/CodeGen/X86/zero-call-used-regs.ll
Log Message:
-----------
[clang] Add more test coverage for "zero-call-used-regs" (#201834)
In clang, the main function is treated as a special case and no
"zero-call-used-regs" attributes are emitted for it. This patch adds
proper unit testing for that functionality.
AFAIU, treating `main` as a special case was initially implemented in
the backend. However, during review [1] the logic was moved to clang
while the associated test case was never updated (and then copied over
to the AArch64 test file).
[1] https://reviews.llvm.org/D110869
More specifically this comment: https://reviews.llvm.org/D110869#3285932
---
Commenting out
https://github.com/llvm/llvm-project/blob/8e217eda17df80d2035d6ff27e74bfa8df77339a/clang/lib/CodeGen/CodeGenFunction.cpp#L1102-L1104
makes the new tests fail while the removed test still pass.
Commit: 44714f90d8e203b9227613c52e7794b58b78454e
https://github.com/llvm/llvm-project/commit/44714f90d8e203b9227613c52e7794b58b78454e
Author: jpwang <jpwang at smail.nju.edu.cn>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/powi.ll
Log Message:
-----------
[InstCombine] Fold afn powi(2.0, x) to ldexp(1.0, x) (#202114)
This PR adds a conservative InstCombine fold `powi(2.0, x) -> ldexp(1.0,
x)` with an `afn` flag.
This together with the existing fold `y * ldexp(1.0, x) -> ldexp(y, x)`
makes it possible to optimize cases like `y * __builtin_powif(2.0f, x)`
under fast-math.
The fold is intentionally limited to cases where the base is exactly 2.0
for now to make it simple.
Fixes #200654
Commit: eac7bb457352bad9d630c057b6336b7168eb9e7b
https://github.com/llvm/llvm-project/commit/eac7bb457352bad9d630c057b6336b7168eb9e7b
Author: woruyu <1214539920 at qq.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFrameInfo.h
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
M llvm/include/llvm/Target/Target.td
M llvm/lib/CodeGen/MachineFrameInfo.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/VirtRegMap.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
A llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
M llvm/test/TableGen/RegisterInfoEmitter-errors.td
M llvm/unittests/CodeGen/MachineInstrTest.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
Log Message:
-----------
[AMDGPU] Set SGPR spill stack IDs when creating spill slots (#197628)
### Summary
This PR resolves https://github.com/llvm/llvm-project/issues/195092.
Teach register classes to describe the StackID to use for their spill
slots, and use it when creating spill frame objects. This lets AMDGPU
SGPR spill slots be marked as TargetStackID::SGPRSpill at construction
time instead of patching the frame object later while emitting spill
instructions.
Also handle SGPR callee-saved spill slots created directly by
SILowerSGPRSpills, which bypass the generic PEI spill slot creation
path. Without this, late SGPR scavenging can see an SGPR spill pseudo
using a default-stack frame index and trip the SGPRSpill assertion.
Commit: 85ac9a1e00690b1a956aa1ede7fbb11a298b9a78
https://github.com/llvm/llvm-project/commit/85ac9a1e00690b1a956aa1ede7fbb11a298b9a78
Author: Artem Chikin <achikin at apple.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/include/clang/DependencyScanning/DependencyScanningFilesystem.h
M clang/lib/DependencyScanning/DependencyScanningFilesystem.cpp
M clang/unittests/DependencyScanning/CMakeLists.txt
M clang/unittests/DependencyScanning/DependencyScanningFilesystemTest.cpp
M llvm/include/llvm/Support/VirtualFileSystem.h
M llvm/lib/Support/VirtualFileSystem.cpp
M llvm/unittests/Support/VirtualFileSystemTest.cpp
Log Message:
-----------
[clang][deps] Add in-flight query caching to `DependencyScanningFilesystemSharedCache` (#199680)
Concurrent dep-scan workers querying the same filename or UID each issue
their own `stat` and `open` against the underlying filesystem; only the
first to finish wins the cache insert, the others' work is wasted.
Add per-key in-flight tracking to `CacheShard`. `InProgressByFilename`
and `InProgressByUID` map each active key to a
`std::shared_ptr<InProgressEntry>` carrying a `std::condition_variable`,
a `Done` predicate, and the produced entry pointer.
`acquireFilenameSlot` / `acquireUIDSlot` collapse three outcomes
(resolved hit, in-progress wait, fresh producer slot) into one critical
section against the shard lock. `fulfilFilenameSlot`,`fulfilUIDSlot`
publish the produced entry, set `Done`, erase the slot, and `notify_all`
waiters outside the lock.
`computeAndStoreResult` now claims the filename slot before `stat` and
the UID slot before `readFile`, so both stat and open redundancy
collapse.
Commit: 2bbf94d210f73d2e1fd52a4179cd89834198675d
https://github.com/llvm/llvm-project/commit/2bbf94d210f73d2e1fd52a4179cd89834198675d
Author: khaki3 <47756807+khaki3 at users.noreply.github.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
M flang/test/HLFIR/assign-bufferize.fir
M flang/test/HLFIR/associate-codegen.fir
M flang/test/HLFIR/bufferize01.fir
M flang/test/HLFIR/extents-of-shape-of.f90
M flang/test/HLFIR/mul_transpose.f90
M flang/test/HLFIR/shapeof-lowering.fir
Log Message:
-----------
[flang][hlfir] Reset lower bounds to one when bufferizing hlfir.as_expr move (#202406)
Example:
```fortran
module m
type t
integer, allocatable :: a(:)
end type
contains
function pf()
integer, allocatable :: pf(:)
allocate(pf(-5:-3)); pf = [1,2,3]
end function
end module
program p
use m
type(t) :: z
z = t(pf())
print *, lbound(z%a,1) ! must be 1
end program
```
In this code, the allocatable function result `pf()` is used in the
structure constructor `t(...)`. As an expression its lower bound is 1,
but lowering wraps the result descriptor in `hlfir.as_expr ... move`,
and bufferization forwarded that descriptor as-is — so its lower bound
`-5` leaked into the reallocated component, printing `-5`.
Fix: when bufferizing `hlfir.as_expr` with `move`, rebox a descriptor
that may carry non-default lower bounds back to lower bound 1
(descriptor only, no data copy).
Commit: 1732c650bff1a34aff3b001d4670b2eb1ab02798
https://github.com/llvm/llvm-project/commit/1732c650bff1a34aff3b001d4670b2eb1ab02798
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/test/tools/llvm-objdump/MachO/function-starts.test
Log Message:
-----------
[llvm-objdump] Remove path from test output (#201940)
Commit: 790f0623411d5d9d5c989f14e87f2fe86f52eaf3
https://github.com/llvm/llvm-project/commit/790f0623411d5d9d5c989f14e87f2fe86f52eaf3
Author: Ömer Sinan Ağacan <omeragacan at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
M llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/ARC/ARCISelLowering.cpp
M llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
M llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
M llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp
M llvm/lib/Target/BPF/BPFSelectionDAGInfo.h
M llvm/lib/Target/CSKY/CSKYISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp
M llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h
M llvm/lib/Target/Lanai/LanaiISelLowering.cpp
M llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp
M llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/M68k/M68kISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
M llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
M llvm/lib/Target/X86/X86SelectionDAGInfo.h
M llvm/lib/Target/XCore/XCoreISelLowering.cpp
M llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp
M llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/test/Analysis/CostModel/ARM/memcpy.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/X86/pr57673.ll
Log Message:
-----------
[SelectionDAG] Pass dest and src alignments separately to memcpy and memmove lowering functions (#201119)
Implements FIXMEs around memcpy and memmove lowering code about passing
destination and source alignments to lowering functions.
Fixes ARM cost model's cost estimation for an inlined `memcpy`. The test
shows the generated code as two instructions so the cost should've been 2,
but it was estimated as a libcall which costs 4.
In the backend functions that don't care about destination and source
alignments, the old alignment calculation `std::min(dstAlign, srcAlign)`
used as the alignment. This gives us the old lowering behavior on those
backends.
Commit: 2d4afb8f9d12901cc472e14f9c2c8146226f5aa4
https://github.com/llvm/llvm-project/commit/2d4afb8f9d12901cc472e14f9c2c8146226f5aa4
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/ds_gws_align.ll
A llvm/test/CodeGen/AMDGPU/si-fold-operands-bundle.mir
Log Message:
-----------
[AMDGPU] SIFoldOperands: update BUNDLE header implicit use when folding (#201872)
When folding an operand inside a BUNDLE, also rewrite the matching
implicit use on the bundle header. LiveVariables iterates a
MachineBasicBlock with the bundle-aware iterator and only inspects the
header, so without this update its kill flags go stale and a later
MachineVerifier run reports "Using a killed virtual register".
Co-Authored-By: Claude Opus 4 <noreply at anthropic.com>
Co-authored-by: Claude Opus 4 <noreply at anthropic.com>
Commit: 743283c295ccc6411296a9a2a757ae4e3b3aa1e0
https://github.com/llvm/llvm-project/commit/743283c295ccc6411296a9a2a757ae4e3b3aa1e0
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lldb/test/API/functionalities/breakpoint/breakpoint_command/TestBreakpointCommand.py
Log Message:
-----------
[lldb][Windows] enable skipped tests (#202689)
Commit: 86f543d6e809fc8de6772aa29fca98e4276bd5c8
https://github.com/llvm/llvm-project/commit/86f543d6e809fc8de6772aa29fca98e4276bd5c8
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp
Log Message:
-----------
[NFC][analyzer] Refactor VisitReturnStmt (#202675)
Simplify an old-style for loop that used explicit iterator manipulation,
and clarify the manipulation of the exploded nodes by removing the
`NodeBuilder`.
This is part of my commit series that gradually removes the class
`NodeBuilder`.
Commit: e0d0d3db9dd47ab9649ebb356ce404b55a2e4a77
https://github.com/llvm/llvm-project/commit/e0d0d3db9dd47ab9649ebb356ce404b55a2e4a77
Author: Chenguang Wang <w3cing at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
M llvm/include/llvm/MC/MCRegisterInfo.h
M llvm/test/TableGen/ConcatenatedSubregs.td
M llvm/test/TableGen/RegisterClassCopyCost.td
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
M llvm/utils/TableGen/Common/InfoByHwMode.h
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
Log Message:
-----------
[llvm][MC] Store RegSize using uint32_t instead of uint16_t. (#201886)
`uint32_t` is needed for working with registers with size >= 65535,
which is the case for a private ISA that I am currently working on. The
performance impact is negligible. See discussions in [LLVM
Discourse](https://discourse.llvm.org/t/rfc-support-reg-sizes-greater-than-65534/90970/2).
Commit: 5adc7ddc15cdb39d0f2f8e1daa8ca21aaa374d3a
https://github.com/llvm/llvm-project/commit/5adc7ddc15cdb39d0f2f8e1daa8ca21aaa374d3a
Author: Sairudra More <sairudra60 at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M openmp/runtime/src/i18n/en_US.txt
M openmp/runtime/src/kmp_ftn_entry.h
A openmp/runtime/test/api/omp_nteams_api_restriction.c
Log Message:
-----------
[OpenMP] Ignore teams ICV setters in restricted contexts (#194428)
This patch prevents `omp_set_num_teams()` and
`omp_set_teams_thread_limit()` from updating teams-related ICVs when
called from restricted runtime contexts.
The non-implicit parallel-region case follows the OpenMP 5.1
restriction. The active `teams`-region case is handled defensively
because these ICVs are device-scoped and updating them during an active
`teams` region can affect later teams execution.
The calls now warn and return without updating the ICVs.
Fixes #194426.
Commit: f31853255c300e07b93783425e40948cc0dfdb0f
https://github.com/llvm/llvm-project/commit/f31853255c300e07b93783425e40948cc0dfdb0f
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/decorators.py
M lldb/test/API/commands/platform/connect/TestPlatformConnect.py
M lldb/test/API/functionalities/breakpoint/breakpoint_command/TestBreakpointCommand.py
M lldb/test/API/functionalities/breakpoint/breakpoint_locations/TestBreakpointLocations.py
M lldb/test/API/functionalities/breakpoint/delayed_breakpoints/TestDelayedBreakpoint.py
M lldb/test/API/functionalities/scripted_frame_provider/circular_dependency/TestFrameProviderCircularDependency.py
Log Message:
-----------
[lldb][Windows] extend @skipIfWindows to lldb-server or in process (#202688)
Some tests fail when using `lldb-server.exe` and pass when using the in
process plugin and vice-versa.
This patch adds the `skipIfWindowsAndNoLLDBServer` and
`expectedFailureWindowsAndNoLLDBServer` decorators (and their opposites)
to only skip tests if they run on `lldb-server` or the in process
plugin.
This fixes 4 XPASS when running tests with `USE_LLDB_SERVER=1`.
rdar://179117754
Commit: b2ee616a926eb2936b892431c7f8a574104e34b9
https://github.com/llvm/llvm-project/commit/b2ee616a926eb2936b892431c7f8a574104e34b9
Author: Yihan Wang <yronglin777 at gmail.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Lex/Lexer.cpp
A clang/test/CXX/lex/lex.header/p2.cpp
Log Message:
-----------
[clang][Lex] Don't parsing header name as a string literal (#201763)
Fixes https://github.com/llvm/llvm-project/issues/132643.
---------
Signed-off-by: yronglin <yronglin777 at gmail.com>
Commit: a147be81a246188ad954ecd2fd1ee93684f49c95
https://github.com/llvm/llvm-project/commit/a147be81a246188ad954ecd2fd1ee93684f49c95
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lldb/unittests/Expression/DWARFExpressionTest.cpp
Log Message:
-----------
[lldb] Add missing period in DWARFExpressionTest (NFC) (#202706)
Commit: 48a4b66451149e0c456a5479c695d894d368de2d
https://github.com/llvm/llvm-project/commit/48a4b66451149e0c456a5479c695d894d368de2d
Author: Yihan Wang <yronglin777 at gmail.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/ExprClassification.cpp
A clang/test/AST/dependent-assignment-classification.cpp
Log Message:
-----------
[clang] Classify binary op value kinds use ClassifyExprValueKind when it's type-dependent (#202696)
The crash is from an internal inconsistency in Clang’s expression
classification.
Expr::ClassifyImpl computes a classification like CL_LValue or
CL_PRValue, then asserts that this agrees with the AST node’s own value
category:
- clang/lib/AST/ExprClassification.cpp:37
- CL_LValue must satisfy E->isLValue()
- CL_PRValue must satisfy E->isPRValue()
Fixes https://github.com/llvm/llvm-project/issues/202693.
Signed-off-by: yronglin <yronglin777 at gmail.com>
Commit: c0e8b29f009bf504b9aafe1f39a539a4f68ca60c
https://github.com/llvm/llvm-project/commit/c0e8b29f009bf504b9aafe1f39a539a4f68ca60c
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
Log Message:
-----------
[CIR][NFC] Align emitLValue with classic codegen (#202448)
This reorganizes the `CIRGenFunction::emitLValue` function to align it
with `CodeGenFunction::EmitLValueHelper` in classic codegen. Previously,
the default handler for the switch statement reported an NYI diagnostic
for any l-value class that wasn't handled in the function. This change
adds case handlers for every class that is handled by classic codegen,
giving each their own NYI diagnostic.
The purpose of this is to more explicitly show what is missing and to
make it easier to port the classic codegen implementation to CIR.
The existing CIR handling is not changed, just the order.
Commit: f4ee842902bf1fb29a956b6a36b17c547407cdbf
https://github.com/llvm/llvm-project/commit/f4ee842902bf1fb29a956b6a36b17c547407cdbf
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M compiler-rt/CMakeLists.txt
Log Message:
-----------
compiler-rt: Suppress -g error for gpu builds (#202230)
Commit: de42f4f2130183111d4d62865177190d6e642ade
https://github.com/llvm/llvm-project/commit/de42f4f2130183111d4d62865177190d6e642ade
Author: Konrad Kleine <kkleine at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M .github/workflows/release-documentation.yml
M .github/workflows/release-doxygen.yml
M .github/workflows/release-tasks.yml
M llvm/utils/release/build-docs.sh
Log Message:
-----------
[docs] Release man pages (#201376)
This adds the possibility to generate man pages from the `llvm/utils/release/build-docs.sh` script. Furthermore the `release-documentation` github workflow was modified to build and upload the man pages.
This was done to prevent dependency problems when myst-parser will become a hard dependency to build the documentation in LLVM. See https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/90840/26?u=kwk
Additionally the `build-docs.sh` script now determines the release from the source directory if no release was given. Otherwise the generated tarballs would be missing the release entirely. To make it clear that something was generated from any git directory, a short git revision will be attached to the release (e.g. `23.0.0-gc823de88d51f58`).
The script generates a total of 67 man pages for the 22.1.7 release (see below).
`lld` has their own man page hardcoded in [`lld/docs/ld.lld.1`](https://github.com/llvm/llvm-project/blob/main/lld/docs/ld.lld.1). It gets packaged manually because of a missing cmake target. To get all projects install their man pages in the same directory to package up, we have to run the install targets rather than just the build targets (e.g. `install-docs-clang-man` instead of just `docs-clang-man`).
Here's what's in the tarball for the `22.1.7` release when you run the script from this change:
```console
$ rm -rf llvm_man_pages-* docs-build llvm-project
$ ./llvm/utils/release/build-docs.sh -no-sphinx -no-doxygen -release 22.1.7
```
```console
$ tar -tf llvm_man_pages-22.1.7.tar.xz
llvm_man_pages-22.1.7/
llvm_man_pages-22.1.7/polly.1
llvm_man_pages-22.1.7/lldb.1
llvm_man_pages-22.1.7/lldb-server.1
llvm_man_pages-22.1.7/extraclangtools.1
llvm_man_pages-22.1.7/flang.1
llvm_man_pages-22.1.7/clang.1
llvm_man_pages-22.1.7/diagtool.1
llvm_man_pages-22.1.7/FileCheck.1
llvm_man_pages-22.1.7/bugpoint.1
llvm_man_pages-22.1.7/clang-tblgen.1
llvm_man_pages-22.1.7/dsymutil.1
llvm_man_pages-22.1.7/lit.1
llvm_man_pages-22.1.7/llc.1
llvm_man_pages-22.1.7/lldb-tblgen.1
llvm_man_pages-22.1.7/lli.1
llvm_man_pages-22.1.7/llvm-addr2line.1
llvm_man_pages-22.1.7/llvm-ar.1
llvm_man_pages-22.1.7/llvm-as.1
llvm_man_pages-22.1.7/llvm-bcanalyzer.1
llvm_man_pages-22.1.7/llvm-cgdata.1
llvm_man_pages-22.1.7/llvm-config.1
llvm_man_pages-22.1.7/llvm-cov.1
llvm_man_pages-22.1.7/llvm-cxxfilt.1
llvm_man_pages-22.1.7/llvm-cxxmap.1
llvm_man_pages-22.1.7/llvm-debuginfo-analyzer.1
llvm_man_pages-22.1.7/llvm-diff.1
llvm_man_pages-22.1.7/llvm-dis.1
llvm_man_pages-22.1.7/llvm-dwarfdump.1
llvm_man_pages-22.1.7/llvm-dwarfutil.1
llvm_man_pages-22.1.7/llvm-exegesis.1
llvm_man_pages-22.1.7/llvm-extract.1
llvm_man_pages-22.1.7/llvm-ifs.1
llvm_man_pages-22.1.7/llvm-install-name-tool.1
llvm_man_pages-22.1.7/llvm-ir2vec.1
llvm_man_pages-22.1.7/llvm-lib.1
llvm_man_pages-22.1.7/llvm-libtool-darwin.1
llvm_man_pages-22.1.7/llvm-link.1
llvm_man_pages-22.1.7/llvm-lipo.1
llvm_man_pages-22.1.7/llvm-locstats.1
llvm_man_pages-22.1.7/llvm-mc.1
llvm_man_pages-22.1.7/llvm-mca.1
llvm_man_pages-22.1.7/llvm-nm.1
llvm_man_pages-22.1.7/llvm-objcopy.1
llvm_man_pages-22.1.7/llvm-objdump.1
llvm_man_pages-22.1.7/llvm-offload-binary.1
llvm_man_pages-22.1.7/llvm-opt-report.1
llvm_man_pages-22.1.7/llvm-otool.1
llvm_man_pages-22.1.7/llvm-pdbutil.1
llvm_man_pages-22.1.7/llvm-profdata.1
llvm_man_pages-22.1.7/llvm-profgen.1
llvm_man_pages-22.1.7/llvm-ranlib.1
llvm_man_pages-22.1.7/llvm-readelf.1
llvm_man_pages-22.1.7/llvm-readobj.1
llvm_man_pages-22.1.7/llvm-reduce.1
llvm_man_pages-22.1.7/llvm-remarkutil.1
llvm_man_pages-22.1.7/llvm-size.1
llvm_man_pages-22.1.7/llvm-stress.1
llvm_man_pages-22.1.7/llvm-strings.1
llvm_man_pages-22.1.7/llvm-strip.1
llvm_man_pages-22.1.7/llvm-symbolizer.1
llvm_man_pages-22.1.7/llvm-tblgen.1
llvm_man_pages-22.1.7/llvm-test-mustache-spec.1
llvm_man_pages-22.1.7/llvm-tli-checker.1
llvm_man_pages-22.1.7/mlir-tblgen.1
llvm_man_pages-22.1.7/opt.1
llvm_man_pages-22.1.7/tblgen.1
llvm_man_pages-22.1.7/ld.lld.1
```
Commit: 5f864f90fd20209ce63c3a1280ac2e8fdc44a3c3
https://github.com/llvm/llvm-project/commit/5f864f90fd20209ce63c3a1280ac2e8fdc44a3c3
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/tools/llvm-exegesis/lib/Assembler.h
Log Message:
-----------
[NFC][llvm-exegesis] Disable CFI-icall for JIT-executed function (#202472) (#202682)
Reland of #202472 reverted with #202571.
Here we are going to use LLVM_NO_SANITIZE.
Commit: 26c550852a90c0eb1732ce3fd48bdf25124eaa4b
https://github.com/llvm/llvm-project/commit/26c550852a90c0eb1732ce3fd48bdf25124eaa4b
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-non-scheduled-node.ll
Log Message:
-----------
[SLP] Recompute copyable operand deps of bundled members in scheduleBlock
An instruction modeled as a copyable element in one node may be used directly
by another node registered only after its deps were last computed. The
deferred recomputation is consumed before that node joins the tree, so the
direct def-use edge is missed and the count stays too low, tripping the
unscheduled-deps assertion. Clear and recompute such bundled members against
the full tree in scheduleBlock.
Fixes #202463
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/202712
Commit: 95bd483fbb6c7b94dd8fa9d8577d633aa02da6b8
https://github.com/llvm/llvm-project/commit/95bd483fbb6c7b94dd8fa9d8577d633aa02da6b8
Author: gulfemsavrun <gulfem at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M compiler-rt/lib/asan/CMakeLists.txt
Log Message:
-----------
[asan] Make exceptions for asan_new_delete.cpp conditional (#202436)
Introduce the COMPILER_RT_ASAN_ENABLE_EXCEPTIONS CMake
option to control whether the ASan C++ runtime
(asan_new_delete.cpp) is compiled with exception
support.
This fixes build failures on platforms with noexcept
toolchains (like Fuchsia's noexcept variant) where
ASan was compiled with exceptions but linked against a
noexcept libc++abi, resulting in undefined symbol
errors for __cxa_begin_catch and __gxx_personality_v0.
The option defaults to ON to preserve the behavior of
#200719, but automatically defaults to OFF if
LIBCXX_ENABLE_EXCEPTIONS or LIBCXXABI_ENABLE_EXCEPTIONS
is set to OFF in the same runtimes build.
Commit: b7cdfe410b1eda88d732709217830fb7bd432432
https://github.com/llvm/llvm-project/commit/b7cdfe410b1eda88d732709217830fb7bd432432
Author: Tom Stellard <tstellar at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
R .github/workflows/issue-subscriber.yml
R .github/workflows/pr-subscriber.yml
A .github/workflows/subscriber.yml
Log Message:
-----------
workflows: Consolidate pr-subscriber and issue-subscriber (#200503)
This consolidates duplicate logic from the pr-subscriber and
issue-subscriber workflows into a single workflow.
Commit: 93c95d3d18f3aa35648daff21544794f90fe9cec
https://github.com/llvm/llvm-project/commit/93c95d3d18f3aa35648daff21544794f90fe9cec
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper-hip-no-rdc.c
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
Log Message:
-----------
[HIP] Fix `-flto` overriding `--no-lto` not that it is default (#202699)
Summary:
The previous changes to LTO made the flto flag passed by default which
overrode the hack we did to ervert to the old non-LTO pipline. This is a
temporary hack so I'm hacking it even further to fix it.
Commit: 93bc18ff2d13e3246a7629ca17bb8352d2c51d89
https://github.com/llvm/llvm-project/commit/93bc18ff2d13e3246a7629ca17bb8352d2c51d89
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lld/MachO/ConcatOutputSection.cpp
M lld/MachO/ConcatOutputSection.h
A lld/test/MachO/arm64-thunk-stubs-multi-text.s
A lld/test/MachO/arm64-thunk-stubs.s
M lld/test/MachO/arm64-thunks.s
Log Message:
-----------
[lld][macho] Fix thunks with multiple text sections (#199747)
When there are multiple `__text` sections, LLD might not generate thunks
to stubs sections when they are required, leading to relocation errors.
```
ld64.lld: error: a.o:(symbol _foo+0x0): relocation BRANCH26 is out of range: 134217744 is not in [-134217728, 134217727]; references _extern_sym
```
Create `TextOutputSection::estimateStubsEndVA()` to correctly estimate
the end VA of the last stubs section so we can tell when branches to
stub symbols will be in range.
Technically this could cause lld to generate more thunks in some cases.
If a binary requires thunks (the `__TEXT` segment is >128MiB) and has
multiple `__text` sections like `__text_cold` or `__lcxx_override`, then
all branches to stub symbols will require thunks. Without this change we
could get the relocation errors above. We might be able to workaround
the problem by placing the `__text` section last.
Fixes https://github.com/llvm/llvm-project/issues/195387.
Commit: 5f689cd94ab1ba030eb9a9fc607b941acba87e93
https://github.com/llvm/llvm-project/commit/5f689cd94ab1ba030eb9a9fc607b941acba87e93
Author: jimingham <jingham at apple.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTrampolineHandler.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTrampolineHandler.h
Log Message:
-----------
Remove support for the obsolete "_fixup" and "_fixedup" modes of objc_msgSend (#202449)
This was one of a long series of tricks for accelerating ObjC dispatch,
but this one hasn't been used for many years now, and the ObjC
maintainers have no intention of reviving this notion.
Commit: 14b2935dba9eab5a52aa2a8c806e29102fbafcf6
https://github.com/llvm/llvm-project/commit/14b2935dba9eab5a52aa2a8c806e29102fbafcf6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M compiler-rt/CMakeLists.txt
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
M compiler-rt/cmake/base-config-ix.cmake
M compiler-rt/cmake/config-ix.cmake
M compiler-rt/lib/builtins/CMakeLists.txt
M compiler-rt/lib/profile/CMakeLists.txt
M compiler-rt/test/builtins/CMakeLists.txt
M compiler-rt/test/ubsan_minimal/CMakeLists.txt
Log Message:
-----------
compiler-rt: Consolidate regex checks for amdgpu targets (#202281)
Commit: 146abed5cd072a27c4240c7cf53b764571e62462
https://github.com/llvm/llvm-project/commit/146abed5cd072a27c4240c7cf53b764571e62462
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
Log Message:
-----------
[AArch64][NFC] Avoid relocations in LdStNInstrDesc (#202025)
These are small strings, so instead of an 8 byte string pointer that
needs a relocation store the strings directly inline. This avoids 320
relocations in libLLVM.so.
Commit: 5fd8036c0cd6eeab4cbc1dea1ca8569c082e874c
https://github.com/llvm/llvm-project/commit/5fd8036c0cd6eeab4cbc1dea1ca8569c082e874c
Author: fineg74 <61437305+fineg74 at users.noreply.github.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVTypeInst.cpp
M llvm/lib/Target/SPIRV/SPIRVTypeInst.h
M llvm/test/CodeGen/SPIRV/transcoding/atomic-load-store-unsupported.ll
A llvm/test/CodeGen/SPIRV/transcoding/store-atomic-ptr.ll
Log Message:
-----------
[SPIRV] Let atomic store store pointers (#201251)
SPIRV atomic store permits only integer or floats as per SPIRV spec.
When compiling libc there several places in the code where pointers are
atomically stored causing compilation to break. It can be fixed by using
casting in the libc code but in order to keep the libc code clean it is
preferrable to do it in SPIRV backend. This change will cast pointer
parameters to integers of appropriate size and generate atomic store
instruction that uses integers per SPIRV spec.
Commit: 473fc95e5e297663a18d8399cce7c6f2a3cb6135
https://github.com/llvm/llvm-project/commit/473fc95e5e297663a18d8399cce7c6f2a3cb6135
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/test/Sema/Inputs/lifetime-analysis.h
M clang/test/Sema/warn-lifetime-safety.cpp
Log Message:
-----------
[LifetimeSafety] Diagnose UAF for aligned and nothrow new expressions (#202286)
Previously LifetimeSafety skips issuing a heap allocation loan for
replaceable global allocation functions such as aligned and nothrow
operator new. This commit fixes that by modeling those forms as heap
allocations.
Closes https://github.com/llvm/llvm-project/issues/196208
Commit: 655462209f3444ecaf526de6e1df2a84d5e54e4b
https://github.com/llvm/llvm-project/commit/655462209f3444ecaf526de6e1df2a84d5e54e4b
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.h
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
M clang/lib/Driver/ToolChains/HIPSPV.cpp
M clang/lib/Driver/ToolChains/HIPSPV.h
M clang/test/Driver/amdgpu-openmp-sanitize-options.c
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/hip-binding.hip
M clang/test/Driver/hip-device-compile.hip
M clang/test/Driver/hip-offload-compress-zlib.hip
M clang/test/Driver/hip-offload-compress-zstd.hip
M clang/test/Driver/hip-phases.hip
M clang/test/Driver/hip-rdc-device-only.hip
M clang/test/Driver/hip-sanitize-options.hip
M clang/test/Driver/hip-save-temps.hip
M clang/test/Driver/hip-spirv-backend-bindings.c
M clang/test/Driver/hip-spirv-backend-opt.c
M clang/test/Driver/hip-spirv-backend-phases.c
M clang/test/Driver/hip-spirv-linker-crash.c
M clang/test/Driver/hip-target-id.hip
M clang/test/Driver/hip-toolchain-device-only.hip
M clang/test/Driver/hip-toolchain-no-rdc.hip
M clang/test/Driver/hip-toolchain-rdc-flto-partitions.hip
M clang/test/Driver/hip-toolchain-rdc-separate.hip
M clang/test/Driver/hip-toolchain-rdc-static-lib.hip
M clang/test/Driver/hip-toolchain-rdc.hip
M clang/test/Driver/hip-unbundle-preproc.hipi
M clang/test/Driver/hipspv-toolchain-rdc-separate.hip
M clang/test/Driver/hipspv-toolchain-rdc.hip
M clang/test/Driver/hipspv-toolchain.hip
M clang/test/Driver/openmp-offload-gpu.c
M clang/test/Driver/spirv-amd-toolchain.c
M clang/test/Driver/spirv-openmp-toolchain.c
Log Message:
-----------
Revert "[Clang] Set default LTO mode for AMDGCN/SPIR-V targets to full" (#202714)
Reverts llvm/llvm-project#201457
Caused flang lit test failures, e.g.
https://lab.llvm.org/buildbot/#/builders/80/builds/22848
Commit: 9c3de270df396a85b01d9aa5dd6729a27f841f2b
https://github.com/llvm/llvm-project/commit/9c3de270df396a85b01d9aa5dd6729a27f841f2b
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M flang/include/flang/Semantics/openmp-utils.h
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/openmp-utils.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Semantics/OpenMP/allocate03.f90
M flang/test/Semantics/OpenMP/allocators02.f90
M flang/test/Semantics/OpenMP/declare-target01.f90
M flang/test/Semantics/OpenMP/detach01.f90
M flang/test/Semantics/OpenMP/firstprivate02.f90
M flang/test/Semantics/OpenMP/lastprivate03.f90
M flang/test/Semantics/OpenMP/linear-clause-array-section.f90
M flang/test/Semantics/OpenMP/parallel-private01.f90
M flang/test/Semantics/OpenMP/parallel-private02.f90
M flang/test/Semantics/OpenMP/parallel-private03.f90
M flang/test/Semantics/OpenMP/parallel-private04.f90
M flang/test/Semantics/OpenMP/parallel-sections01.f90
M flang/test/Semantics/OpenMP/parallel-shared01.f90
M flang/test/Semantics/OpenMP/parallel-shared02.f90
M flang/test/Semantics/OpenMP/parallel-shared03.f90
M flang/test/Semantics/OpenMP/parallel-shared04.f90
M flang/test/Semantics/OpenMP/resolve01.f90
M flang/test/Semantics/OpenMP/threadprivate01.f90
Log Message:
-----------
[flang][OpenMP] Move check for substring to semantic checks (#201384)
Move it to CheckVarIsNotPartOfAnotherVar, which is also refactored a
bit.
Commit: 13a95bf84c1a2378b97a03493da2b37f3a71fb7c
https://github.com/llvm/llvm-project/commit/13a95bf84c1a2378b97a03493da2b37f3a71fb7c
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/bolt/unittests/Profile/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/StaticAnalyzer/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/include/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Windows/Common/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Target/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Frontend/Offloading/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Target/AArch64/BUILD.gn
Log Message:
-----------
[gn build] Port commits (#202730)
1ef2f3b98b13
2426b855f303
2bd098b819c1
69215c5e4f03
88bd366041fd
a08dce6881f6
fc9bf89cfd9a
Commit: 7e526f7bc4ace92236d7d07cb5771031347f2ce4
https://github.com/llvm/llvm-project/commit/7e526f7bc4ace92236d7d07cb5771031347f2ce4
Author: Federico Bruzzone <federico.bruzzone.i at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp
M mlir/test/Dialect/Affine/SuperVectorize/vector_utils.mlir
M mlir/test/Dialect/Affine/SuperVectorize/vectorize_1d.mlir
M mlir/test/Dialect/Affine/SuperVectorize/vectorize_2d.mlir
A mlir/test/Dialect/Affine/SuperVectorize/vectorize_2d_inbounds.mlir
M mlir/test/Dialect/Affine/SuperVectorize/vectorize_affine_apply.mlir
M mlir/test/Dialect/Affine/SuperVectorize/vectorize_reduction.mlir
Log Message:
-----------
[mlir][affine] emit `in_bounds` on `transfer_read`/`write` when statically provable in `affine-super-vectorize` (#201180)
This patch fixes an issue reported on the MLIR Discourse ([May
2026](https://discourse.llvm.org/t/mlir-affine-affine-super-vectorize-does-not-set-in-bounds-on-transfer-ops-for-statically-divisible-shapes/90785/3)),
that I also came across during a study I reported in [my blog
post](https://federicobruzzone.github.io/posts/mlir-study.html).
`affine-super-vectorize` always creates `vector.transfer_read` and
`vector.transfer_write` without an `in_bounds` attribute, even when it
is statically provable that every access stays within bounds. This
forces downstream lowering to unconditionally emit
`llvm.intr.masked.load`/`llvm.intr.masked.store`: masked intrinsics that
carry $\sim3\times$ overhead on AArch64/NEON and prevent
auto-vectorization (see the MLIR Discourse).
## Root cause
`vectorizeAffineLoad` and `vectorizeAffineStore` in `SuperVectorize.cpp`
forwarded neither the `in_bounds` mask nor any analysis of it when
constructing the transfer ops. The fix computes the mask at
vectorization time by inspecting the permutation map and the memref type
via a new `computeInBoundsMask` helper:
- `AffineDimExpr`: the vector dimension maps to a concrete memref
dimension. If that dimension is static and divisible by the vector
width, the accesses are guaranteed in-bounds.
- `AffineConstantExpr`: a broadcast (the dimension is collapsed to a
constant index). A broadcast can never be out-of-bounds.
- Everything else (e.g., AffineAddExpr on dynamic dimensions):
conservatively left false.
<details>
<summary>Reproduction</summary>
Run the lowering pipeline on any static-size affine copy loop:
```mlir
// file: copy.mlir
func.func @copy(%A: memref<512x512xf32>, %B: memref<512x512xf32>) {
affine.for %i = 0 to 512 {
affine.for %j = 0 to 512 {
%v = affine.load %A[%i, %j] : memref<512x512xf32>
affine.store %v, %B[%i, %j] : memref<512x512xf32>
}
}
return
}
```
```
mlir-opt copy.mlir \
--affine-super-vectorize="virtual-vector-size=4" \
--convert-vector-to-llvm \
--finalize-memref-to-llvm \
--convert-func-to-llvm
```
Before this patch: masked intrinsics despite fully static, divisible
dimensions:
```
%31 = llvm.intr.masked.load %30, %25, %16 {alignment = 4 : i32} : (!llvm.ptr, vector<4xi1>, vector<4xf32>) -> vector<4xf32>
llvm.intr.masked.store %31, %43, %38 {alignment = 4 : i32} : vector<4xf32>, vector<4xi1> into !llvm.ptr
```
After this patch: plain vector load/store:
```
%23 = llvm.load %22 {alignment = 4 : i64} : !llvm.ptr -> vector<4xf32>
llvm.store %23, %28 {alignment = 4 : i64} : vector<4xf32>, !llvm.ptr
```
</details>
AI Disclaimer: I used AI for the tests.
---------
Signed-off-by: Federico Bruzzone <federico.bruzzone.i at gmail.com>
Co-authored-by: Artem Gindinson <gindinson at roofline.ai>
Commit: 2aaaff72e65f8a8e67515ca51768ef65f222d524
https://github.com/llvm/llvm-project/commit/2aaaff72e65f8a8e67515ca51768ef65f222d524
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/openmp-utils.cpp
M flang/test/Semantics/OpenMP/assumed-size-array-dsa.f90
M flang/test/Semantics/OpenMP/cray-pointer-usage.f90
M flang/test/Semantics/OpenMP/reduction-assumed.f90
Log Message:
-----------
[flang][OpenMP] Move assumed-size array check to list item verification (#201385)
The presence of whole assumed-size arrays will now be diagnosed in a
single location, together with the verification of list item kinds.
Commit: 3c0e69e655a28a0061404b5f296a07abf037e5be
https://github.com/llvm/llvm-project/commit/3c0e69e655a28a0061404b5f296a07abf037e5be
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
Log Message:
-----------
[compiler-rt] Fix undefined AMDGPU variable not set for builtins (#202733)
Summary:
compiler-rt is weird and has multiple config files, make sure this is
set for both libs and builtins.
Commit: 2b9a8e2d76e1d99f95a13f70dc619dc679187432
https://github.com/llvm/llvm-project/commit/2b9a8e2d76e1d99f95a13f70dc619dc679187432
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowExtractor.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
Log Message:
-----------
[SSAF] Increase Expr kind coverage in EntityPointerLevelTranslator (#197568)
- Add support for more kinds of Expr that can be translated to
EntityPointerLevel(s).
- Additionally, fix bugs in PointerFlowExtractor discovered by tests
added for the new Expr kinds.
Commit: 6e7c4fd79d769bf860045af798a1ee7eefc88305
https://github.com/llvm/llvm-project/commit/6e7c4fd79d769bf860045af798a1ee7eefc88305
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lldb/CMakeLists.txt
Log Message:
-----------
[lldb][cmake] Fix lldb_python_target_dir in unusual build configurations (#202492)
The lldb binary, when running regression tests, will search for Python
bindings relative to itself. Normally,
`${CMAKE_BINARY_DIR}/${CMAKE_CFG_INTDIR}` is consistent with that path,
but both Arm and Qualcomm build toolchains using a configuration where
that doesn't work.
Fix the configuration to use LLVM_RUNTIME_OUTPUT_INTDIR as the source of
truth for where lldb will be installed. This is the variable used to
determine where the lldb binary is located in the build directory, so it
will always be consistent.
Commit: 7d1cc51305618bfe2d63603d9cec3a4a4c147a10
https://github.com/llvm/llvm-project/commit/7d1cc51305618bfe2d63603d9cec3a4a4c147a10
Author: cmtice <cmtice at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py
Log Message:
-----------
[LLDB] Fix race/collision in TestGlobalModuleCache.py (#202731)
https://github.com/llvm/llvm-project/pull/201561 sped up the test so
much that, on very fast machines, there is now a collision. The two
different a.out files get created with the exact same timestmp, which
confuses the module caching and can result in odd test failures:
make: Leaving directory
'/build/work/8a9b9199309f6c504f12c8bdaef77b319248/google3/tmp/lldb-test-build.noindex/python_api/global_module_cache/TestGlobalModuleCache.test_TwoTargetsOneDebugger_dwarf'
Unable to load lldb extension module. Possible reasons for this include:
1) LLDB was built with LLDB_ENABLE_PYTHON=0
2) PYTHONPATH and PYTHONHOME are not set correctly. PYTHONHOME should
refer to
the version of Python that LLDB built and linked against, and PYTHONPATH
should contain the Lib directory for the same python distro, as well as
the
location of LLDB's site-packages folder.
3) A different version of Python than that which was built against is
exported in
the system's PATH environment variable, causing conflicts.
4) The executable
'/build/work/8a9b9199309f6c504f12c8bdaef77b319248/google3/runfiles/google3/third_party/llvm/llvm-project/lldb/lldb'
could not be found. Please check
that it exists and is executable.
This PR fixes that by future-dating the second a.out file.
AI-assisted by Gemini.
Commit: 219c085c45b8e0bb4f2ea0e1131646e7916b9936
https://github.com/llvm/llvm-project/commit/219c085c45b8e0bb4f2ea0e1131646e7916b9936
Author: albertbolt1 <albertboltinfinity at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/MicrosoftMangle.cpp
A clang/test/CodeGenCXX/aarch64-mangle-sme-attrs-ms.cpp
Log Message:
-----------
[arm64] Added Microsoft mangling code for sme attributes (#199567)
Fixes #178804 .
Commit: 8dac043eb036250cfc2010c44c75b54d08d2d5ef
https://github.com/llvm/llvm-project/commit/8dac043eb036250cfc2010c44c75b54d08d2d5ef
Author: John Otken <john at otken.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M flang-rt/lib/runtime/edit-input.cpp
M flang-rt/unittests/Runtime/InputExtensions.cpp
M flang/docs/Extensions.md
Log Message:
-----------
[flang-rt] Add support for logical binary input edit descriptor (#193490)
Add binary 'B' input edit descriptor support for logical values to flang
runtime EditLogicalInput(). The logical binary 'B' edit descriptor is
already supported in EditLogicalOutput().
Co-authored-by: John Otken john.otken at hpe.com
Commit: df75b5d458b9faef2007485e8348d83b32798a5c
https://github.com/llvm/llvm-project/commit/df75b5d458b9faef2007485e8348d83b32798a5c
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/CodeGenOptions.h
M clang/include/clang/Options/Options.td
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/CodeGen/epilog-unwind.c
A clang/test/CodeGen/winx64-eh-unwind-egpr.c
M clang/test/Driver/cl-options.c
A clang/test/Driver/winx64-eh-unwind.c
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/IR/Module.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/MC/MCWin64EH.h
M llvm/include/llvm/MC/MCWinEH.h
M llvm/include/llvm/Support/CodeGen.h
M llvm/lib/IR/Module.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MC/MCWin64EH.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/CMakeLists.txt
M llvm/lib/Target/X86/X86.h
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86WinEHUnwindV2.cpp
A llvm/lib/Target/X86/X86WinEHUnwindV3.cpp
A llvm/test/CodeGen/X86/apx/push2-pop2-cfi-seh-v3.ll
M llvm/test/CodeGen/X86/apx/push2-pop2-cfi-seh.ll
A llvm/test/CodeGen/X86/win64-eh-unwindv3-egpr-required.ll
A llvm/test/CodeGen/X86/win64-eh-unwindv3-funclet-prolog.ll
A llvm/test/CodeGen/X86/win64-eh-unwindv3-push2pop2.ll
A llvm/test/CodeGen/X86/win64-eh-unwindv3-split.ll
A llvm/test/CodeGen/X86/win64-eh-unwindv3-too-many-epilog-ops.mir
A llvm/test/CodeGen/X86/win64-eh-unwindv3-too-many-prolog-ops.mir
A llvm/test/CodeGen/X86/win64-eh-unwindv3.ll
M llvm/test/DebugInfo/COFF/apx-egpr.ll
M llvm/test/MC/AsmParser/seh-directive-errors.s
A llvm/test/MC/COFF/seh-unwindv3-error.s
A llvm/test/MC/COFF/seh-unwindv3-inheritance.s
A llvm/test/MC/COFF/seh-unwindv3-large.s
A llvm/test/MC/COFF/seh-unwindv3-nonmirror.s
A llvm/test/MC/COFF/seh-unwindv3-pool-sharing.s
A llvm/test/MC/COFF/seh-unwindv3.s
M llvm/unittests/MC/CMakeLists.txt
A llvm/unittests/MC/WODRoundTripTest.cpp
Log Message:
-----------
[win][x64] Add support for Windows x64 unwind v3 (#200249)
The extended registers in Intel APX cannot be described in the current
Windows x64 unwind information, this has made it neccesary to introduce
a new version. While designing this new version, improvements have been
made from the lessons learnt from the existing unwind information
formats (both x64 and AArch64).
Documentation for unwind v3 is available at:
<https://learn.microsoft.com/en-us/cpp/build/x64-unwind-information-v3>
This change:
* Implements encoding unwind v3 information in MC. This includes support
for non-mirror epilogs, WOD pool sharing and using large infos if
required.
* Add support for encoding push2/pop2 SEH info: a new `SEH_Push2Regs`
pseudo-instruction and `.seh_push2regs` assembly directive.
* Changes the prolog/epilog codegen to support unwind v3. Specifically,
adding pseudos into the epilog (as non-mirror epilogs are permitted) and
placing the pseudos in the prolog before the instruction instead of
after (as v3 measures its offsets from the start rather than the end of
an instruction).
* Add an unwind v3 pass to chain unwind info if there are too many
epilogs in a function and raise a fatal error if there are too many
instructions in a prolog or epilog.
* Changes the module flag and code gen enums to allow selecting
"Default" vs "v1" vs "v2 best effort" vs "v2 required" vs "v3" unwind
info version.
* Adds new Clang and cc1 flags for selecting the unwind info version and
deprecates the old v2 flag. The default unwind info version stays as v1
UNLESS the EGPR target feature is enabled (then it will use v3). Trying
to enable EGPR when v1/v2 is explicitly enabled will result in an error.
Windows 11 [build
29576](https://learn.microsoft.com/en-us/windows-insider/release-notes/experimental-future-platforms/preview-build-29576-1000)
and above support unwind v3 in user-mode, but do not yet support large
info.
Commit: e95d6365af4a04f70f7f76743b58197a163a6d52
https://github.com/llvm/llvm-project/commit/e95d6365af4a04f70f7f76743b58197a163a6d52
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
A llvm/test/Transforms/LoopInterchange/complex-inner-latch-condition.ll
Log Message:
-----------
[LoopInterchange] Add test for legality check missing latch condition (NFC) (#202725)
Add a test case reported in #202220. This is a case where the condition
of the inner loop's latch branch is complex, in particular, it's not a
`cmp` instruction, and thus the legality check fails to properly detect
an unsupported case.
Commit: 870c33765b7da53d7234fd1d93eda20d1775d971
https://github.com/llvm/llvm-project/commit/870c33765b7da53d7234fd1d93eda20d1775d971
Author: Miguel A. Arroyo <miguel.arroyo at rockstargames.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Support/CommandLine.cpp
Log Message:
-----------
[llvm][cmake] Print Integrated CRT Alloc (#201741)
* As with other similar toggle-able features, the `--version` reports if
a custom allocator is used (e.g. `+alloc:<name>`).
Commit: 89b969eadbaf49a2de6b7722f248f67a42944d10
https://github.com/llvm/llvm-project/commit/89b969eadbaf49a2de6b7722f248f67a42944d10
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.h
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
M clang/lib/Driver/ToolChains/HIPSPV.cpp
M clang/lib/Driver/ToolChains/HIPSPV.h
M clang/test/Driver/amdgpu-openmp-sanitize-options.c
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/hip-binding.hip
M clang/test/Driver/hip-device-compile.hip
M clang/test/Driver/hip-offload-compress-zlib.hip
M clang/test/Driver/hip-offload-compress-zstd.hip
M clang/test/Driver/hip-phases.hip
M clang/test/Driver/hip-rdc-device-only.hip
M clang/test/Driver/hip-sanitize-options.hip
M clang/test/Driver/hip-save-temps.hip
M clang/test/Driver/hip-spirv-backend-bindings.c
M clang/test/Driver/hip-spirv-backend-opt.c
M clang/test/Driver/hip-spirv-backend-phases.c
M clang/test/Driver/hip-spirv-linker-crash.c
M clang/test/Driver/hip-target-id.hip
M clang/test/Driver/hip-toolchain-device-only.hip
M clang/test/Driver/hip-toolchain-no-rdc.hip
M clang/test/Driver/hip-toolchain-rdc-flto-partitions.hip
M clang/test/Driver/hip-toolchain-rdc-separate.hip
M clang/test/Driver/hip-toolchain-rdc-static-lib.hip
M clang/test/Driver/hip-toolchain-rdc.hip
M clang/test/Driver/hip-unbundle-preproc.hipi
M clang/test/Driver/hipspv-toolchain-rdc-separate.hip
M clang/test/Driver/hipspv-toolchain-rdc.hip
M clang/test/Driver/hipspv-toolchain.hip
M clang/test/Driver/openmp-offload-gpu.c
M clang/test/Driver/spirv-amd-toolchain.c
M clang/test/Driver/spirv-openmp-toolchain.c
M flang/test/Driver/omp-driver-offload.f90
Log Message:
-----------
Reapply "[Clang] Set default LTO mode for AMDGCN/SPIR-V targets to full" (#202714) (#202736)
This reverts commit 655462209f3444ecaf526de6e1df2a84d5e54e4b.
Commit: c901f5bcc757f5fa2ef037287465f68b7a90b67c
https://github.com/llvm/llvm-project/commit/c901f5bcc757f5fa2ef037287465f68b7a90b67c
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/include/clang/Basic/Attr.td
A clang/test/Driver/driverkit26-boundary.c
A clang/test/Driver/simple-darwin.c
M llvm/lib/TargetParser/Triple.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
Log Message:
-----------
[clang][Darwin] Canonicalize DriverKit platform between DriverKit 26<->27 (#202690)
* Canonicalize driverkit26 to 27 in availability & deployment
versioning.
* Make darwin27 and later map 1:1 to the same macOS major version.
Resolves: rdar://178548081
Commit: d0a1f86e78908ab30d48a9408cc4673c20203422
https://github.com/llvm/llvm-project/commit/d0a1f86e78908ab30d48a9408cc4673c20203422
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lldb/source/Plugins/ObjectFile/Mach-O/CMakeLists.txt
A lldb/source/Plugins/ObjectFile/Mach-O/MachOTrie.cpp
A lldb/source/Plugins/ObjectFile/Mach-O/MachOTrie.h
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
Log Message:
-----------
[lldb] Extract Mach-O export trie parsing into MachOTrie.{h,cpp} (NFC) (#202735)
ParseTrieEntries and its TrieEntry helpers were file-local statics in
ObjectFileMachO.cpp, unreachable from tests. Move them into a
self-contained translation unit (depending only on lldbUtility) so the
parser can be exercised in isolation.
Commit: 784836de471a74a45a4f4431974b7c3c588ffa81
https://github.com/llvm/llvm-project/commit/784836de471a74a45a4f4431974b7c3c588ffa81
Author: yebinchon <86588366+yebinchon at users.noreply.github.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/CodeGen/TypeConverter.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/FIRToMemRef.cpp
M flang/test/Fir/convert-to-llvm-invalid.fir
A flang/test/Fir/shape-extents.mlir
A flang/test/Fir/shape-to-llvm.mlir
A flang/test/Transforms/FIRToMemRef/forwarded-shape.mlir
Log Message:
-----------
[FIR] add a fir.shape_extents operation (#199361)
Add fir.shape_extents op. This takes a !fir.shape<n> and unpacks it into
n integer SSA values (one per dimension, row-to-column order). This
supports lowering when extent values are needed but the defining
fir.shape is not visible.
FIRToMemRef now inserts fir.shape_extents when recovering extents from a
shape operand that is not a direct fir.shape / fir.shape_shift /
existing fir.shape_extents result (e.g. block arguments from
fir.select_case).
Also allow live fir.shape values at fir-to-llvm lowering: !fir.shape<n>
maps to an n-field i64 LLVM struct, and live fir.shape ops lower via
llvm.undef + llvm.insertvalue. fir.shape_extents lowers via
llvm.extractvalue (+ cast to index).
In the original path, cg-rewrite still fuses shape-bearing fir.embox /
fir.array_coor into fircg.* forms and shapes remain dead before LLVM
lowering. The new path is for forwarded shapes that survive past memref
lowering.
Tests: adds shape-extents.mlir (op + canonicalize) &
forwarded-shape.mlir (FIRToMemRef fir.shape_extents insertion)
updates convert-to-llvm-invalid.fir (live fir.shape is no longer an
invalid case).
---------
Co-authored-by: Yebin Chon <ychon at nvidia.com>
Commit: 5997a17bdaec757775a71bbe9e390f1f8e737178
https://github.com/llvm/llvm-project/commit/5997a17bdaec757775a71bbe9e390f1f8e737178
Author: Guilherme Lopes <guilhermeglopes at tecnico.ulisboa.pt>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
A llvm/test/Transforms/JumpThreading/lifetime-alloca.ll
Log Message:
-----------
[JumpThreading] Fix lifetime markers when alloca requires SSA renaming (#188147)
JumpThreading can create PHI nodes for alloca values when threading
across blocks. This violates the requirement introduced in #149310 that
lifetime.start/end intrinsics must operate directly on allocas.
After SSA reconstruction, check if any lifetime marker for an alloca now
points to a PHI node. If so, drop all lifetime markers for that alloca.
Fixes #167733
Commit: c4803d71255236d8d8b4ef608011cd7d53c1bda0
https://github.com/llvm/llvm-project/commit/c4803d71255236d8d8b4ef608011cd7d53c1bda0
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/assume.ll
Log Message:
-----------
[InstCombine] Move nonnull assumptions to the base of a gep (#195650)
Alive2 proof: https://alive2.llvm.org/ce/z/2TkRyt
Commit: fb8ec0b096a517c50720dab17ce57ba76e841133
https://github.com/llvm/llvm-project/commit/fb8ec0b096a517c50720dab17ce57ba76e841133
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/unittests/Support/DynamicLibrary/DynamicLibraryTest.cpp
Log Message:
-----------
[test][Support] Disable CFI-icall for DynamicLibrary Overload test (#202446) (#202684)
The test performs manual symbol lookup and calls, which triggers
Control Flow Integrity indirect call checks.
Reland of #202446 reverted with #202550.
Here we are going to use LLVM_NO_SANITIZE.
Commit: c1ff74c4bf50c811f4155d51dc53456b568ca8ba
https://github.com/llvm/llvm-project/commit/c1ff74c4bf50c811f4155d51dc53456b568ca8ba
Author: Weiwei C <weiwei.chen at modular.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/lib/Bytecode/Reader/BytecodeReader.cpp
Log Message:
-----------
[mlir] Don't use shared_ptr reference. (#202703)
`const std::share_ptr<...>&` doesn't increase ref count which can easily
cause downstream user bugs with maintaining the life time of the object.
Remove `&` to kick in ref count.
Commit: d1304bd75f71c0c425d137da36f8d6a29d9aa0a2
https://github.com/llvm/llvm-project/commit/d1304bd75f71c0c425d137da36f8d6a29d9aa0a2
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/OffloadTargetVerifier.cpp
M mlir/test/Dialect/OpenACC/offload-target-verifier.mlir
Log Message:
-----------
[mlir][acc] Offload verifier should print variable names (#202678)
The offload target verifier is used to ensure that all ssa values and
symbols have appropriate OpenACC mapping. When this is not the case, an
error is shown. However, showing variable names is useful and thus add
the functionality since OpenACCSupport has the means to retrieve them.
Commit: e5f4d51418fc2f101282a20aafbce3fa3e80ed51
https://github.com/llvm/llvm-project/commit/e5f4d51418fc2f101282a20aafbce3fa3e80ed51
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/test/Target/SPIRV/decorations-id.mlir
Log Message:
-----------
[mlir][SPIR-V] Enable spirv-val for OpDecorateId decoration tests (NFC) (#202591)
Commit: 087df2c6a34542baf1b3acbf0088074c79769003
https://github.com/llvm/llvm-project/commit/087df2c6a34542baf1b3acbf0088074c79769003
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/test/Transforms/LoopInterchange/complex-inner-latch-condition.ll
Log Message:
-----------
[LoopInterchange] Bail out if inner latch branch cond is not CmpInst (#202726)
The condition argument of the branch instruction in the inner loop latch
is checked during the legality check phase, and the loops are rejected
if the condition argument is in an unsupported form. Previously, this
check ran only when the condition was a `cmp` instruction, so it missed
cases where it was not, e.g., an `and` of two `i1` values.
This patch fixes the issue by simply bailing out if the condition
argument is not a `cmp` instruction. This may be too conservative, but
it is sound, and we can improve the analysis in the future if desired.
Fix #202220.
Commit: 56067875b7d5f44dbc41e8628b39858c421a64a2
https://github.com/llvm/llvm-project/commit/56067875b7d5f44dbc41e8628b39858c421a64a2
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
M mlir/test/Target/SPIRV/linkage-types.mlir
Log Message:
-----------
[mlir][SPIR-V] Add WeakLinkageAMD capability for Weak linkage type (#202590)
Commit: 2f217a67295c120d7b97c1d8d6df71f35ebbd109
https://github.com/llvm/llvm-project/commit/2f217a67295c120d7b97c1d8d6df71f35ebbd109
Author: Changqing Jing <changqing.jing at bmw.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/Utils/WebAssemblyTypeUtilities.cpp
M llvm/lib/Target/WebAssembly/Utils/WebAssemblyTypeUtilities.h
M llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
A llvm/test/CodeGen/WebAssembly/immutable-global-alias.ll
A llvm/test/CodeGen/WebAssembly/imported-const-global.ll
A llvm/test/CodeGen/WebAssembly/invalid-wasm-global-function-alias.ll
A llvm/test/CodeGen/WebAssembly/invalid-wasm-global-symbol.ll
Log Message:
-----------
[WebAssembly] Preserve constness for imported globals (#199507)
This fixes a WebAssembly backend bug where imported `const` globals lose
their
constness during lowering.
For a source like:
```c++
extern "C" {
extern const int [[clang::address_space(1)]] imported_g;
int goo() { return imported_g; }
}
```
In current main branch, the imported_g is lowered to mutable import
global.
```
(module
(type (;0;) (func (result i32)))
(import "env" "imported_g" (global (;0;) (mut i32)))
(func (;0;) (type 0) (result i32)
global.get 0)
(table (;0;) 1 1 funcref)
(memory (;0;) 2)
(export "memory" (memory 0))
(export "goo" (func 0))
(export "__indirect_function_table" (table 0)))
```
The root cause is that wasm global mutability was hard-coded during
symbol
typing, so the backend ignored `GlobalVariable::isConstant()`. This
patch
threads mutability through wasm global symbol typing and derives it from
`!GV->isConstant()`.
Both the asm-printer path and the MCInst-lowering path are updated,
because
either of them may initialize the wasm symbol first.
Commit: 7f5a6d77bac92ca3273bb0a98b8604f4987001ed
https://github.com/llvm/llvm-project/commit/7f5a6d77bac92ca3273bb0a98b8604f4987001ed
Author: hotschmoe <stronggarner66 at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/MC/WinCOFFObjectWriter.cpp
A llvm/test/MC/AArch64/coff-secrel-hi12.s
Log Message:
-----------
[MC][COFF][AArch64] Add helper symbols for large SECREL addends (#199602)
## Summary
Create helper label symbols for ARM64 COFF SECREL HI12/LO12 relocations
when the byte offset cannot fit in the 12-bit instruction addend.
This is the MC-side follow-up to #200060: with LLD now handling small
SECREL_HIGH12A byte addends correctly, this patch only handles the
remaining large-addend case that needs a helper symbol.
Fixes #199581.
AI assistance: Claude (Anthropic), Codex (OpenAI).
## Tests
`llvm/test/MC/AArch64/coff-secrel-hi12.s`, run for both
`aarch64-windows` and `arm64ec-windows`, covers:
- Temporary symbol, offset in range (`.Lsmall`, `.Lsmall+4`): emitted as
a `.bss` section relocation with the offset baked into the imm12; no
helper symbol.
- Temporary symbol, offset out of range (`.Lsmall+16`, `.Llarge`,
`.Llarge+4`): a helper label symbol is created at the exact section
offset and the imm12 is cleared.
- Non-temporary symbol, offset in range (`large`, `large+128`):
relocation against the symbol with the addend in the imm12; no helper
symbol.
`ninja -C build check-llvm-mc`
Commit: 37337d80763e29177dfd87e2fb702f4ea935d002
https://github.com/llvm/llvm-project/commit/37337d80763e29177dfd87e2fb702f4ea935d002
Author: ykhatav <yashasvi.khatavkar at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/Parse/Parser.h
M clang/lib/AST/OpenMPClause.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/OpenMP/interop_prefer_type_brace_ast_print.cpp
A clang/test/OpenMP/interop_prefer_type_brace_messages.cpp
M clang/tools/libclang/CIndex.cpp
Log Message:
-----------
[clang][OpenMP] Add OMP 6.0 prefer_type({fr,attr}) parsing for interop (#198868)
This PR adds parsing support for the OpenMP 6.0 brace-grouped
prefer_type modifier on the init clause of #pragma omp interop, while
preserving the OpenMP 5.1 flat form. Each preference-specification can
now carry an optional
fr(<foreign-runtime-id>) and zero or more attr(<string-literal>...)
selectors, eg:
#pragma omp interop init(prefer_type({fr("sycl"), attr("ompx_propX")}, \
{fr("level_zero")}, \
{attr("ompx_propY")}), targetsync: obj)
Commit: 8c0f84e7a71091df9e20fa06a2c5e67fe0d183f5
https://github.com/llvm/llvm-project/commit/8c0f84e7a71091df9e20fa06a2c5e67fe0d183f5
Author: Susan Tan (ス-ザン タン) <zujunt at nvidia.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/test/Analysis/AliasAnalysis/alias-analysis-regionbranch.mlir
Log Message:
-----------
[flang] Add RegionBranchOpInterface to fir.do_loop (#202418)
`fir.do_loop` lacked RegionBranchOpInterface, causing dataflow analyses
and others to treat host loops as opaque and conservatively block
optimizations.
Implement getSuccessorRegions, getEntrySuccessorOperands, and
getSuccessorInputs on fir.do_loop, and override
getMutableSuccessorOperands on fir.result to customize for accommodating
the occasionally present finalValue in `fir.result`.
As a side effect, alias analysis now resolves pass-through iter-carried
references to MustAlias instead of MayAlias.
Commit: 596e95cc514f33f0b176fcae781824d14c249464
https://github.com/llvm/llvm-project/commit/596e95cc514f33f0b176fcae781824d14c249464
Author: Tom Stellard <tstellar at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M .github/workflows/build-ci-container-tooling.yml
M .github/workflows/containers/github-action-ci-tooling/Dockerfile
Log Message:
-----------
[Github] Add github-automation container (#200704)
There are several jobs that use the pattern:
1. Checkout github-automation.py script.
2. Install dependencies for github-automation.py script.
3. Run the github-automation.py script.
We can consolidate a lot of this logic into the container and simplify
the workflows. This may also speed them up the workflow jobs slightly,
but most of them are already pretty fast, so it may not make a big
difference.
Commit: 003ba404c8b50b367879cad29783d24881a6c1c6
https://github.com/llvm/llvm-project/commit/003ba404c8b50b367879cad29783d24881a6c1c6
Author: Schrodinger ZHU Yifan <yfzhu at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libc/fuzzing/__support/freelist_heap_fuzz.cpp
M libc/src/__support/block.h
M libc/src/__support/freelist.cpp
M libc/src/__support/freelist.h
M libc/src/__support/freelist_heap.h
M libc/src/__support/freestore.h
M libc/src/__support/freetrie.h
M libc/test/src/__support/block_test.cpp
M libc/test/src/__support/freelist_heap_test.cpp
M libc/test/src/__support/freelist_test.cpp
M libc/test/src/__support/freestore_test.cpp
M libc/test/src/__support/freetrie_test.cpp
Log Message:
-----------
[libc] Migrate `Block` to `BlockRef` in baremetal allocator (#201001)
Under C++ object lifetime and strict aliasing rules, accessing typed
objects requires that an object of that type actually exists at the
memory location. Previously, the Block structure stored prev and next
offset values, where the prev field overlapped with the usable space of
the preceding block to save space. When the predecessor was allocated,
user payload was written directly to this overlapping space,
complicating object lifetime management. A key issue arose during
reallocation (like in-place shrinking), where the allocator needed to
manipulate block boundaries (e.g., splitting a block) while user payload
was still actively residing in that memory. This caused undefined
behavior due to accessing typed Block members that collided with the
user's active objects.
This patch eliminates the problem by always treating blocks as raw bytes
accessed through a byte-backed proxy (BlockRef). Instead of constructing
or casting to typed Block structures, metadata is read and written using
aligned byte-copy operations (inline_memcpy). This decouples block
manipulation from C++ object lifetime rules, guaranteeing safe access
without violating strict aliasing.
Assisted-by: AI Tools, checked manually
Commit: d76b85c46e0d319322945283a396f6917444023f
https://github.com/llvm/llvm-project/commit/d76b85c46e0d319322945283a396f6917444023f
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
A llvm/test/CodeGen/X86/dag-maps-huge-region-crash.ll
Log Message:
-----------
[MachineScheduler] Check we don't add self dependency edge when adding barrier (#202743)
Followup to #200945.
When we hit the huge-region limit for both FPExceptions and memory
operations, we'd first set BarrierChain to the current SU in the
FPExceptions path, then again in the memory operations path, and we'd
add the SU itself as a dependency.
Check we're not adding a self dependency when creating a barrier.
Assisted-by: Gemini
Commit: 88fbb4a9eef5ec9f79a4db028e9e1e907a1ae866
https://github.com/llvm/llvm-project/commit/88fbb4a9eef5ec9f79a4db028e9e1e907a1ae866
Author: Anshul Nigham <nigham at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64PassRegistry.def
Log Message:
-----------
[NewPM][AArch64] Port AArch64DAGToDAGISelLegacy to NewPM (#202739)
Adds `AArch64DAGToDAGISelPass`, the NewPM port for AArch64 instruction
selection. Inherits from `SelectionDAGISelPass` and reuses its
implementation, similar to X86 and AMDGPU ports and the Legacy pass
implementation.
Assisted by Gemini
Commit: f6e900184a814b8339c41c764ef13a7aedfc9480
https://github.com/llvm/llvm-project/commit/f6e900184a814b8339c41c764ef13a7aedfc9480
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll
Log Message:
-----------
[AMDGPU] Fix GISel lowering for amdgcn_s_quadmask, amdgcn_s_wqm (#202704)
This change also marks the intrinsics
`amdgcn_s_quadmask` and `amdgcn_s_wqm`
as AlwaysUniform.
Commit: 06f25425e324fdfa79613f5255dfb2c77ae7de6d
https://github.com/llvm/llvm-project/commit/06f25425e324fdfa79613f5255dfb2c77ae7de6d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/transform-narrow-interleave-to-widen-memory.ll
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/cast-induction.ll
M llvm/test/Transforms/LoopVectorize/expand-ptrtoaddr.ll
M llvm/test/Transforms/LoopVectorize/induction-step.ll
M llvm/test/Transforms/LoopVectorize/miniters.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/reduction-minmax-users-and-predicated.ll
M llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
Log Message:
-----------
[VPlan] Also expand integer SCEVAddExpr in expandSCEVExpr. (#200925)
Generalize the SCEVMulExpr handling in expandSCEVExpr to also handle
SCEVAddExpr. Currently limited to integer expressions only. Pointer to
follow separately, as they cannot use Instruction::Add.
Commit: d1330e2e624039c8ee67db4d1f6e686b6d339722
https://github.com/llvm/llvm-project/commit/d1330e2e624039c8ee67db4d1f6e686b6d339722
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes d0a1f86 (#202746)
This fixes d0a1f86e78908ab30d48a9408cc4673c20203422.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 4ed07e26fc00fbfef25b7e9889eace5514a795f0
https://github.com/llvm/llvm-project/commit/4ed07e26fc00fbfef25b7e9889eace5514a795f0
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M compiler-rt/CMakeLists.txt
M compiler-rt/lib/profile/CMakeLists.txt
Log Message:
-----------
Build ROCm profile runtime by default (#202718)
The ROCm profile runtime should get regular build coverage. Keeping it
off by
default lets it regress unless a build enables it explicitly.
Make the option default to on for normal Linux and Windows builds, where
the
runtime is supported. The target still has the existing dependency
checks, and
normal profile links keep using the base profile runtime unless the
driver
selects the ROCm archive for HIP profiling.
Commit: 2bc40691cd99e819fc35a852a33d53a04074458f
https://github.com/llvm/llvm-project/commit/2bc40691cd99e819fc35a852a33d53a04074458f
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/unittests/Support/DynamicLibrary/DynamicLibraryTest.cpp
Log Message:
-----------
Revert "[test][Support] Disable CFI-icall for DynamicLibrary Overload test (#202446)" (#202768)
Reverts llvm/llvm-project#202684
This breaks builds with some gcc versions (at least v14).
```
/home/aidengrossman/llvm-project/llvm/unittests/Support/DynamicLibrary/DynamicLibraryTest.cpp:62:32: error: attributes are not allowed on a function-definition
62 | TEST(DynamicLibrary, Overload) __attribute__((no_sanitize("cfi-icall"))) {
| ^~~~~~~~~~~~~
```
Commit: b9ddb4c4630d39982de676d311ed80e5e1f7f5b2
https://github.com/llvm/llvm-project/commit/b9ddb4c4630d39982de676d311ed80e5e1f7f5b2
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lldb/unittests/ObjectFile/MachO/CMakeLists.txt
A lldb/unittests/ObjectFile/MachO/MachOTrieTest.cpp
Log Message:
-----------
[lldb] Add unit tests for Mach-O export trie parsing (NFC) (#202747)
Add MachOTrieTest covering the well-formed cases of ParseTrieEntries. A
small TrieBuilder lays out well-formed trie bytes to keep the tests
readable.
Assisted-by: Claude
Commit: fc1f754c397b6a1d3e5c7199db81191ec9335faf
https://github.com/llvm/llvm-project/commit/fc1f754c397b6a1d3e5c7199db81191ec9335faf
Author: Daniil Dudkin <unterumarmung at yandex.ru>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/CMakeLists.txt
M clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp
A clang-tools-extra/clang-tidy/readability/RedundantNestedIfCheck.cpp
A clang-tools-extra/clang-tidy/readability/RedundantNestedIfCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/redundant-nested-if.rst
A clang-tools-extra/test/clang-tidy/checkers/readability/Inputs/redundant-nested-if/common.h
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-nested-if-allow-bool-conversion.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-nested-if-cxx17-allow-bool-conversion.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-nested-if-cxx17.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-nested-if-cxx20.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-nested-if-cxx23.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-nested-if-cxx26.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-nested-if-notes.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-nested-if.cpp
Log Message:
-----------
[clang-tidy] Add `readability-redundant-nested-if` check (#181558)
Introduce a readability check that merges nested `if`/`if constexpr`
chains by combining conditions with `&&`.
This resurrects the earlier patch at https://reviews.llvm.org/D130630.
The implementation keeps fix-its conservative around macros,
preprocessor directives, attributes, user-defined bool conversions, and
comment placement in removable nested headers. It also supports C++17
declaration conditions by rewriting them into init-statement form when
safe.
Assisted by Codex in writing tests and some of the code.
Commit: 16f692338cf41c29774e13f96856f040923f5d2c
https://github.com/llvm/llvm-project/commit/16f692338cf41c29774e13f96856f040923f5d2c
Author: Nikita Grivin <neuronspectrelin at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libcxx/docs/ReleaseNotes/23.rst
M libcxx/include/__configuration/availability.h
M libcxx/include/variant
M libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/powerpc-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/powerpc64-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-freebsd.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.noexceptions.nonew.abilist
M libcxx/src/variant.cpp
A libcxx/test/libcxx/utilities/variant/variant.bad_variant_access/good_what_message.pass.cpp
Log Message:
-----------
[libcxx] Enrich message for std::bad_variant_access exception (#196495)
## Summary
`std::bad_variant_access::what()` now returns a more descriptive message
identifying the failing operation (e.g. `std::get: variant is
valueless`)
instead of the generic `bad_variant_access`. Brings libc++ to parity
with
libstdc++, which has provided richer messages for years.
Discussed in:
[RFC](https://discourse.llvm.org/t/rfc-improve-bad-variant-access-what-messages/90716)
Adds an internal derived class of `bad_variant_access` carrying a `const
char*`
message, exported from the dylib with availability annotations. The base
`bad_variant_access` class is unchanged — no ABI flag required, no
layout
change to the existing type. Throw sites in `__generic_get` and
`__throw_if_valueless` instantiate the derived type with the appropriate
literal; user code catching `bad_variant_access const&` picks up the new
`what()` via virtual dispatch.
Distinguishes three failure modes:
- `std::get: wrong alternative for variant`
- `std::get: variant is valueless`
- `std::visit: variant is valueless`
## ABI
Updated
`x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.nonew.abilist`
based on a local Linux build. Other platforms' ABI lists will need
updates
per CI feedback - I don't have access to those toolchains for local
verification.
Commit: a8dda777b681547505be2e0968042f9fe9a18c1a
https://github.com/llvm/llvm-project/commit/a8dda777b681547505be2e0968042f9fe9a18c1a
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/lib/Driver/ToolChains/Arch/RISCV.h
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/riscv-mtune-tune-features.c
M llvm/docs/RISCVUsage.rst
Log Message:
-----------
[Driver][RISCV] Support the new `-mtune` syntax with tuning feature string (#196653)
A follow-up patch for #175063 : now clang supports the new `-mtune`
syntax outlined in the aforementioned PR, guarded behind a switch,
`-mexperimental-mtune-syntax`.
Commit: 4b4d43da80fe66bf668a7b9a00fa5842db5c55d7
https://github.com/llvm/llvm-project/commit/4b4d43da80fe66bf668a7b9a00fa5842db5c55d7
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/utils/sanitizers/ubsan_ignorelist.txt
Log Message:
-----------
[NFC][cfi] Ignore cfi-icall for DiagnosticHandler.h (#202515)
Different callback types for C and C++ cause CFI failures.
At the moment `sanitizer-aarch64-linux-bootstrap-cfi` uses
`-DLLVM_USE_SANITIZER=Undefined`
as some parts are shared with Ubsan. So we use the same ignore list.
Commit: 5e7b35d31eea52d0db2313d38e166a29a6265436
https://github.com/llvm/llvm-project/commit/5e7b35d31eea52d0db2313d38e166a29a6265436
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lldb/source/Plugins/ObjectFile/Mach-O/MachOTrie.cpp
M lldb/unittests/ObjectFile/MachO/MachOTrieTest.cpp
Log Message:
-----------
[lldb] Fix infinite recursion in Mach-O export trie parsing (#202773)
A malformed (or hostile) export trie whose child offset points back to a
node already on the path from the root (a cycle) made ParseTrieEntries
recurse forever and overflow the stack.
Track the node offsets visited during the walk and reject any trie that
revisits one. Add unit tests for a self-cycle and a back-edge cycle.
Commit: 04e06adc44f3c4cd7b7c62fd9d6c828cfe79eee2
https://github.com/llvm/llvm-project/commit/04e06adc44f3c4cd7b7c62fd9d6c828cfe79eee2
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M flang/include/flang/Optimizer/Analysis/AliasAnalysis.h
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-scoped-origins.fir
M flang/test/Analysis/AliasAnalysis/ptr-component.fir
Log Message:
-----------
[flang] Support declarations scoping in FIR AA. (#201216)
Further experimentation with MLIR inlining showed that
FIR AA becomes more conservative once a subprogram is inlined.
For example:
```
subroutine caller(p1,p2)
real, pointer :: p1,p1
call callee(p1,p2)
end
subroutine callee(a1,a2)
real :: a1,a2
a1 = a2
end
```
After `callee` is inlined, FIR AA assumes that `a1` and `a2`
alias at the point of the assignment, because it classifies them
as pointer accesses.
This patch adds a machinery to collect declaration information
for multiple subprogram scopes (as currently defined by
`fir.dummy_scope`),
so that FIR AA can use this information for better disambiguation.
Assisted by Cursor
Commit: 4132e661249fcba4157f2b86acf900c638b2386e
https://github.com/llvm/llvm-project/commit/4132e661249fcba4157f2b86acf900c638b2386e
Author: Alex Langford <alangford at apple.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lldb/unittests/ObjectFile/MachO/TestObjectFileMachO.cpp
Log Message:
-----------
[lldb] Adjust TestObjectFileMachO.cpp for macOS 27 (#202792)
In macOS 27 (and accompanying device OSes), objc_msgSend was moved out
of the libobjc dylib into other system dylibs.
The simplest fix is to use a different symbol from libobjc.
Commit: e6db723ce7b1e43327d265081f7e5818194569a0
https://github.com/llvm/llvm-project/commit/e6db723ce7b1e43327d265081f7e5818194569a0
Author: jimingham <jingham at apple.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTrampolineHandler.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTrampolineHandler.h
Log Message:
-----------
Handle objc_msgSend being a re-export symbol from libobjc.A.dylib. (#202776)
In some cases, objc_msgSend and the objc_msgSendSuper can be re-exported
symbols in libobjc.A.dylib. Handle that case here. There were a number
of failures in the ObjC stepping tests before this was handled, so we
didn't need more tests.
If there isn't a re-exported symbol, we'll fall back to a code symbol.
---------
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
Commit: 0812848fea235364842a626ba19ec1a7804006b7
https://github.com/llvm/llvm-project/commit/0812848fea235364842a626ba19ec1a7804006b7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/Sema/SemaRISCV.cpp
Log Message:
-----------
[RISCV] Remove unnecessary check for Zvfh in SemaRISCV::checkRVVTypeSupport. NFC (#202788)
Zvfh implies Zvfhmin so we only need to check the latter
Commit: fb1e4b1e59d4a7136cd4782a04da0aca189dfafd
https://github.com/llvm/llvm-project/commit/fb1e4b1e59d4a7136cd4782a04da0aca189dfafd
Author: Harald van Dijk <hdijk at accesssoftek.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/DirectX/DXILPrepare.cpp
M llvm/lib/Target/DirectX/DirectX.h
M llvm/lib/Target/DirectX/DirectXIRPasses/CMakeLists.txt
A llvm/lib/Target/DirectX/DirectXIRPasses/DXILAttributes.cpp
A llvm/lib/Target/DirectX/DirectXIRPasses/DXILAttributes.h
M llvm/lib/Target/DirectX/DirectXIRPasses/DXILDebugInfo.cpp
Log Message:
-----------
[DirectX] Move getNonDXILAttributeMask to DirectXIRPasses (#202781)
DXILDebugInfo.cpp uses it and is part of DirectXIRPasses, but
DXILPrepare.cpp defined it and is part of DirectXCodeGen. DirectXCodeGen
has a dependency on DirectXIRPasses, so we cannot also add a dependency
from DirectXIRPasses back on DirectXCodeGen, and we need to move the
definition of getNonDXILAttributeMask() instead.
Fixes: #201336
Commit: cf50b0c966857a2cb9fd708fadb1d4b3f05cd82e
https://github.com/llvm/llvm-project/commit/cf50b0c966857a2cb9fd708fadb1d4b3f05cd82e
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lldb/docs/resources/caveats.md
Log Message:
-----------
[lldb][docs] Drop stale Python 2 note from caveats page (NFC) (#202754)
Remove the Python 2 section from the caveats page. Python 2 has been
end-of-life since 2020 and is no longer shipped with current macOS, so
the xcrun guidance for it and the deprecation note are no longer useful.
As promised in #201256.
Commit: 81cdb52c03fb3a4f3ff2b30b71e3963ed90e2e61
https://github.com/llvm/llvm-project/commit/81cdb52c03fb3a4f3ff2b30b71e3963ed90e2e61
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lldb/source/Plugins/ObjectFile/Mach-O/MachOTrie.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/MachOTrie.h
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/unittests/ObjectFile/MachO/MachOTrieTest.cpp
Log Message:
-----------
[lldb] Drop prefix & offset arguments in ParseTrieEntries (#202805)
I addressed Dave's review feedback locally but forgot to push the fix to
the PR branch. This removes the prefix and offset arguments from the
public API.
Commit: dfab397600fb548e895d2c28832d5eaeea3f8bb1
https://github.com/llvm/llvm-project/commit/dfab397600fb548e895d2c28832d5eaeea3f8bb1
Author: dyung <douglas.yung at sony.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/include/clang/DependencyScanning/DependencyScanningFilesystem.h
M clang/lib/DependencyScanning/DependencyScanningFilesystem.cpp
M clang/unittests/DependencyScanning/CMakeLists.txt
M clang/unittests/DependencyScanning/DependencyScanningFilesystemTest.cpp
M llvm/include/llvm/Support/VirtualFileSystem.h
M llvm/lib/Support/VirtualFileSystem.cpp
M llvm/unittests/Support/VirtualFileSystemTest.cpp
Log Message:
-----------
Revert "[clang][deps] Add in-flight query caching to `DependencyScanningFilesystemSharedCache`" (#202804)
Reverts llvm/llvm-project#199680
Causing a test failure on
https://lab.llvm.org/buildbot/#/builders/46/builds/36362.
Commit: 2350c1f5e01189f7018b12276d0d53a26d3da31e
https://github.com/llvm/llvm-project/commit/2350c1f5e01189f7018b12276d0d53a26d3da31e
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/unittests/Support/DynamicLibrary/DynamicLibraryTest.cpp
Log Message:
-----------
[test][Support] Disable CFI-icall for DynamicLibrary Overload test (#202446) (#202684) (#202794)
The test performs manual symbol lookup and calls, which triggers
Control Flow Integrity indirect call checks.
Reland of #202446 and #202684 reverted with #202550 #202446.
Here we are going to use LLVM_NO_SANITIZE and check `__clang__`.
Commit: e160695032d838fdeb3ff313f99dbffc38f94a7a
https://github.com/llvm/llvm-project/commit/e160695032d838fdeb3ff313f99dbffc38f94a7a
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/HLSLExternalSemaSource.h
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/builtins/InterlockedAdd.hlsl
A clang/test/SemaHLSL/BuiltIns/InterlockedAdd-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/asuint-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/splitdouble-errors.hlsl
M clang/test/SemaHLSL/parameter_modifiers.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/DirectX/InterlockedAdd.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/InterlockedAdd.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/InterlockedAdd_spv_i64.ll
Log Message:
-----------
[HLSL] Add InterlockedAdd HLSL functions (#195742)
This PR adds the `InterlockedAdd` function to HLSL.
For now, only integer references are accepted: resources passed as a
parameter, and this function as a member method to certain resources,
will be addressed in a separate PR.
Addresses https://github.com/llvm/llvm-project/issues/99122
Assisted by: Github Copilot
Commit: 9f30981a2f4c1d3fa808938bf3703e8468be2e55
https://github.com/llvm/llvm-project/commit/9f30981a2f4c1d3fa808938bf3703e8468be2e55
Author: 🍌Shawn <m18824909883 at 163.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M clang/include/clang/Driver/OffloadBundler.h
M clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp
Log Message:
-----------
[clang-offload-bundler] Convert `std::vector` to `llvm::SmallVector` in `OffloadBundlerConfig` (#192259)
Replace `std::vector<std::string>` with `llvm::SmallVector<std::string,
4>`
for TargetNames, InputFileNames, and OutputFileNames to avoid heap
allocation for small number of elements.
Commit: 87e5d3898c2dbc73f9e75aa16be27757e3969f52
https://github.com/llvm/llvm-project/commit/87e5d3898c2dbc73f9e75aa16be27757e3969f52
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lld/MachO/InputFiles.cpp
A lld/test/MachO/compact-unwind-local-label.s
Log Message:
-----------
[lld][MachO] Handle compact unwind entries with no matching symbol (#180009)
Context: This change is to support [MachO basic block hot-cold
splitting](https://discourse.llvm.org/t/rfc-support-fsplit-machine-functions-on-macho-arm64/89739)
- though it's presented below outside of this context.
Compact unwind entries can reference function addresses that have no
corresponding symbol in the object's symbol table (e.g. functions with
temporary local labels). Previously, this would trigger an assertion
failure in assert-enabled builds, or silently drop the unwind entry in
release builds, resulting in missing unwind info at runtime.
Fix this by synthesizing a local `Defined` symbol when no symbol exists
at the target address of a compact unwind entry, so that unwind info is
correctly emitted.
[Assisted-by](https://t.ly/Dkjjk): Cursor IDE + claude-opus-4.6-high +
gpt-5.2-xhigh
Commit: 5e8d4064bc74ba2a0766d7c89ebe0dcf0271a716
https://github.com/llvm/llvm-project/commit/5e8d4064bc74ba2a0766d7c89ebe0dcf0271a716
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/atomic-cmpxchg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-add-sub.ll
M llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/bitreverse-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/calls.ll
M llvm/test/CodeGen/RISCV/GlobalISel/combine-neg-abs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv32.ll
M llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/fastcc-float.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64p.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zba.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/shift.ll
M llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
M llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abds.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/abdu.ll
M llvm/test/CodeGen/RISCV/add-before-shl.ll
M llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
M llvm/test/CodeGen/RISCV/add_shl_constant.ll
M llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll
M llvm/test/CodeGen/RISCV/addcarry.ll
M llvm/test/CodeGen/RISCV/addimm-mulimm.ll
M llvm/test/CodeGen/RISCV/aext-to-sext.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/alu64.ll
M llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll
M llvm/test/CodeGen/RISCV/and-shl.ll
M llvm/test/CodeGen/RISCV/arith-with-overflow.ll
M llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
M llvm/test/CodeGen/RISCV/atomic-rmw.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/RISCV/avgceils.ll
M llvm/test/CodeGen/RISCV/avgceilu.ll
M llvm/test/CodeGen/RISCV/avgfloors.ll
M llvm/test/CodeGen/RISCV/avgflooru.ll
M llvm/test/CodeGen/RISCV/bf16-promote.ll
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bfloat-imm.ll
M llvm/test/CodeGen/RISCV/bfloat-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/bfloat-mem.ll
M llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll
M llvm/test/CodeGen/RISCV/bfloat.ll
M llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll
M llvm/test/CodeGen/RISCV/bitreverse-shift.ll
M llvm/test/CodeGen/RISCV/bittest.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
M llvm/test/CodeGen/RISCV/bswap-known-bits.ll
M llvm/test/CodeGen/RISCV/bswap-shift.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-half.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll
M llvm/test/CodeGen/RISCV/calling-conv-p-ext-vector.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll
M llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
M llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll
M llvm/test/CodeGen/RISCV/calls-cf-branch.ll
M llvm/test/CodeGen/RISCV/calls.ll
M llvm/test/CodeGen/RISCV/clmul.ll
M llvm/test/CodeGen/RISCV/clmulh.ll
M llvm/test/CodeGen/RISCV/clmulr.ll
M llvm/test/CodeGen/RISCV/cmov-branch-opt.ll
M llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
M llvm/test/CodeGen/RISCV/combine-storetomstore.ll
M llvm/test/CodeGen/RISCV/compress.ll
M llvm/test/CodeGen/RISCV/condbinops.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/constpool-known-bits.ll
M llvm/test/CodeGen/RISCV/copyprop.ll
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/csr-first-use-cost.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/di-assignment-tracking-vector.ll
M llvm/test/CodeGen/RISCV/div-by-constant.ll
M llvm/test/CodeGen/RISCV/div-pow2.ll
M llvm/test/CodeGen/RISCV/div.ll
M llvm/test/CodeGen/RISCV/div_minsize.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/double-calling-conv.ll
M llvm/test/CodeGen/RISCV/double-convert-strict.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-mem.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-select-icmp.ll
M llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
M llvm/test/CodeGen/RISCV/double_reduct.ll
M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/fastcc-bf16.ll
M llvm/test/CodeGen/RISCV/fastcc-float.ll
M llvm/test/CodeGen/RISCV/fastcc-half.ll
M llvm/test/CodeGen/RISCV/fastcc-int.ll
M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/fixed-csr.ll
M llvm/test/CodeGen/RISCV/float-arith.ll
M llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
M llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/float-convert-strict.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/float-round-conv.ll
M llvm/test/CodeGen/RISCV/float-select-icmp.ll
M llvm/test/CodeGen/RISCV/fma-combine.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
M llvm/test/CodeGen/RISCV/fold-binop-into-select.ll
M llvm/test/CodeGen/RISCV/fold-masked-merge.ll
M llvm/test/CodeGen/RISCV/fold-mem-offset-zilsd.ll
M llvm/test/CodeGen/RISCV/fold-mem-offset.ll
M llvm/test/CodeGen/RISCV/forced-atomics.ll
M llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll
M llvm/test/CodeGen/RISCV/fp128.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/fpenv.ll
M llvm/test/CodeGen/RISCV/frm-write-in-loop.ll
M llvm/test/CodeGen/RISCV/get-setcc-result-type.ll
M llvm/test/CodeGen/RISCV/ghccc-rv32.ll
M llvm/test/CodeGen/RISCV/ghccc-rv64.ll
M llvm/test/CodeGen/RISCV/ghccc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-nonzero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-zero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize.ll
M llvm/test/CodeGen/RISCV/global-merge.ll
M llvm/test/CodeGen/RISCV/half-arith-strict.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/half-fcmp.ll
M llvm/test/CodeGen/RISCV/half-imm.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/half-mem.ll
M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/half-select-fcmp.ll
M llvm/test/CodeGen/RISCV/half-select-icmp.ll
M llvm/test/CodeGen/RISCV/half-zfa.ll
M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
M llvm/test/CodeGen/RISCV/i64-icmp.ll
M llvm/test/CodeGen/RISCV/iabs.ll
M llvm/test/CodeGen/RISCV/icmp-non-byte-sized.ll
M llvm/test/CodeGen/RISCV/idiv_large.ll
M llvm/test/CodeGen/RISCV/imm.ll
M llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-d-modifier-N.ll
M llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-f-modifier-N.ll
M llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
M llvm/test/CodeGen/RISCV/jump-is-expensive.ll
M llvm/test/CodeGen/RISCV/jumptable-swguarded.ll
M llvm/test/CodeGen/RISCV/jumptable.ll
M llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll
M llvm/test/CodeGen/RISCV/legalize-fneg.ll
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/load-store-pair.ll
M llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
M llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll
M llvm/test/CodeGen/RISCV/lpad.ll
M llvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
M llvm/test/CodeGen/RISCV/machine-cse.ll
M llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll
M llvm/test/CodeGen/RISCV/machinelicm-constant-phys-reg.ll
M llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
M llvm/test/CodeGen/RISCV/mask-variable-shift.ll
M llvm/test/CodeGen/RISCV/mem.ll
M llvm/test/CodeGen/RISCV/mem64.ll
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
M llvm/test/CodeGen/RISCV/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/memcpy.ll
M llvm/test/CodeGen/RISCV/memmove.ll
M llvm/test/CodeGen/RISCV/memset-inline.ll
M llvm/test/CodeGen/RISCV/memset-pattern.ll
M llvm/test/CodeGen/RISCV/min-max.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/mul-expand.ll
M llvm/test/CodeGen/RISCV/mul.ll
M llvm/test/CodeGen/RISCV/musttail-indirect-args.ll
M llvm/test/CodeGen/RISCV/narrow-shl-cst.ll
M llvm/test/CodeGen/RISCV/neg-abs.ll
M llvm/test/CodeGen/RISCV/nomerge.ll
M llvm/test/CodeGen/RISCV/nontemporal.ll
M llvm/test/CodeGen/RISCV/or-is-add.ll
M llvm/test/CodeGen/RISCV/orc-b-patterns.ll
M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
M llvm/test/CodeGen/RISCV/pr135206.ll
M llvm/test/CodeGen/RISCV/pr142004.ll
M llvm/test/CodeGen/RISCV/pr145360.ll
M llvm/test/CodeGen/RISCV/pr148084.ll
M llvm/test/CodeGen/RISCV/pr176001.ll
M llvm/test/CodeGen/RISCV/pr186969.ll
M llvm/test/CodeGen/RISCV/pr190868.ll
M llvm/test/CodeGen/RISCV/pr51206.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr58511.ll
M llvm/test/CodeGen/RISCV/pr63816.ll
M llvm/test/CodeGen/RISCV/pr64645.ll
M llvm/test/CodeGen/RISCV/pr65025.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/pr84653_pr85190.ll
M llvm/test/CodeGen/RISCV/pr90652.ll
M llvm/test/CodeGen/RISCV/pr94145.ll
M llvm/test/CodeGen/RISCV/pr95271.ll
M llvm/test/CodeGen/RISCV/pr95284.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
M llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
M llvm/test/CodeGen/RISCV/reassoc-shl-addi-add.ll
M llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
M llvm/test/CodeGen/RISCV/rem.ll
M llvm/test/CodeGen/RISCV/remat.ll
M llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
M llvm/test/CodeGen/RISCV/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/rv32-inline-asm-pairs.ll
M llvm/test/CodeGen/RISCV/rv32-move-merge.ll
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rv32xandesperf.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv32zbkb.ll
M llvm/test/CodeGen/RISCV/rv32zbs.ll
M llvm/test/CodeGen/RISCV/rv64-double-convert.ll
M llvm/test/CodeGen/RISCV/rv64-float-convert.ll
M llvm/test/CodeGen/RISCV/rv64-half-convert.ll
M llvm/test/CodeGen/RISCV/rv64-inline-asm-pairs.ll
M llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
M llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
M llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
M llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
M llvm/test/CodeGen/RISCV/rv64xtheadba.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zba.ll
M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbs.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll
M llvm/test/CodeGen/RISCV/rvp-narrowing-shift-trunc.ll
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
M llvm/test/CodeGen/RISCV/rvp-unaligned-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-vector-tuple.ll
M llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/buildvec-sext.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/combine-ctpop-to-vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
M llvm/test/CodeGen/RISCV/rvv/combine-vl-vw-macc.ll
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll
M llvm/test/CodeGen/RISCV/rvv/concat-vectors-constant-stride.ll
M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/expand-no-v.ll
M llvm/test/CodeGen/RISCV/rvv/expandload.ll
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/fcanonicalize-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fcanonicalize-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpowi.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-scalarized.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-addsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-merge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmaccbf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverse-float.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-fp-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccsu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvdot4a8i.ll
M llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximumnum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimumnum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
M llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll
M llvm/test/CodeGen/RISCV/rvv/fp4-bitcast.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
M llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl.ll
M llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll
M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/incorrect-extract-subvector-combine.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/insertelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
M llvm/test/CodeGen/RISCV/rvv/intrinsic-vector-match.ll
M llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/llround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/localvar.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/lround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
M llvm/test/CodeGen/RISCV/rvv/masked-sdiv.ll
M llvm/test/CodeGen/RISCV/rvv/masked-srem.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
M llvm/test/CodeGen/RISCV/rvv/masked-udiv.ll
M llvm/test/CodeGen/RISCV/rvv/masked-urem.ll
M llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mixed-float-bf16-arith.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/musttail-indirect-args.ll
M llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
M llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
M llvm/test/CodeGen/RISCV/rvv/partial-reduction-add.ll
M llvm/test/CodeGen/RISCV/rvv/pr104480.ll
M llvm/test/CodeGen/RISCV/rvv/pr125306.ll
M llvm/test/CodeGen/RISCV/rvv/pr165232.ll
M llvm/test/CodeGen/RISCV/rvv/pr52475.ll
M llvm/test/CodeGen/RISCV/rvv/pr61561.ll
M llvm/test/CodeGen/RISCV/rvv/pr83017.ll
M llvm/test/CodeGen/RISCV/rvv/pr88576.ll
M llvm/test/CodeGen/RISCV/rvv/pr88799.ll
M llvm/test/CodeGen/RISCV/rvv/pr90559.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
M llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll
M llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.ll
M llvm/test/CodeGen/RISCV/rvv/remat.ll
M llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare-asm.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/smulo-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/splats-with-mixed-vl.ll
M llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/stack-probing-dynamic.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/stlf.ll
M llvm/test/CodeGen/RISCV/rvv/stores-of-loads-merging.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
M llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
M llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
M llvm/test/CodeGen/RISCV/rvv/vaadd.ll
M llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vadc.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vadd.ll
M llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vand.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vandn.ll
M llvm/test/CodeGen/RISCV/rvv/vasub.ll
M llvm/test/CodeGen/RISCV/rvv/vasubu.ll
M llvm/test/CodeGen/RISCV/rvv/vclmul.ll
M llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu.ll
M llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll
M llvm/test/CodeGen/RISCV/rvv/vector-compress.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-reassociations.ll
M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfirst-byte-compare-index.ll
M llvm/test/CodeGen/RISCV/rvv/vfirst.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd-w-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-bf-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-bf-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-alt.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvtbf16-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmaccbf16-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmul-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmul.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub-w-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-evl-tail-folding.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-live-out.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vle_vid-vfcvt.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in.ll
M llvm/test/CodeGen/RISCV/rvv/vmadc.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmax.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu.ll
M llvm/test/CodeGen/RISCV/rvv/vmerge.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsif.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
M llvm/test/CodeGen/RISCV/rvv/vmsof.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmul.ll
M llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmulh.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.s.x.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vor.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-float.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode-f16.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp-f16.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrem.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vremu.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-valid-elen-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vsext.ll
M llvm/test/CodeGen/RISCV/rvv/vsmul.ll
M llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssub.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsub.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-mask-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub-mask-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxor.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vzext.ll
M llvm/test/CodeGen/RISCV/rvv/xandesvbfhcvt-vfwcvt-s-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-sdnode.ll
M llvm/test/CodeGen/RISCV/sadd_sat.ll
M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/scmp.ll
M llvm/test/CodeGen/RISCV/select-binop-identity.ll
M llvm/test/CodeGen/RISCV/select-cc.ll
M llvm/test/CodeGen/RISCV/select-cond.ll
M llvm/test/CodeGen/RISCV/select-const.ll
M llvm/test/CodeGen/RISCV/select-constant-xor.ll
M llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
M llvm/test/CodeGen/RISCV/select-pseudo-merge-with-stack-adj.ll
M llvm/test/CodeGen/RISCV/select-zbb.ll
M llvm/test/CodeGen/RISCV/select.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/shift-amount-mod.ll
M llvm/test/CodeGen/RISCV/shift-and.ll
M llvm/test/CodeGen/RISCV/shift-masked-shamt.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/shl-cttz.ll
M llvm/test/CodeGen/RISCV/shlimm-addimm.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt-load-atomic-acquire-seq_cst.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt-load.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt-mul.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt-qcloads.ll
M llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll
M llvm/test/CodeGen/RISCV/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/signed-truncation-check.ll
M llvm/test/CodeGen/RISCV/split-offsets.ll
M llvm/test/CodeGen/RISCV/split-store.ll
M llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll
M llvm/test/CodeGen/RISCV/split-urem-by-constant.ll
M llvm/test/CodeGen/RISCV/srem-lkk.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/ssub_sat.ll
M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
M llvm/test/CodeGen/RISCV/stack-clash-prologue.ll
M llvm/test/CodeGen/RISCV/stack-folding.ll
M llvm/test/CodeGen/RISCV/stack-probing-dynamic-nonentry.ll
M llvm/test/CodeGen/RISCV/stack-store-check.ll
M llvm/test/CodeGen/RISCV/switch-width.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/trunc-nsw-nuw.ll
M llvm/test/CodeGen/RISCV/typepromotion-overflow.ll
M llvm/test/CodeGen/RISCV/uadd_sat.ll
M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/ucmp.ll
M llvm/test/CodeGen/RISCV/udiv-const-optimization.ll
M llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
M llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll
M llvm/test/CodeGen/RISCV/urem-lkk.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/usub_sat_plus.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
M llvm/test/CodeGen/RISCV/vscale-demanded-bits.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/RISCV/xcvmem-heuristic.ll
M llvm/test/CodeGen/RISCV/xcvmem.ll
M llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
M llvm/test/CodeGen/RISCV/xqcia.ll
M llvm/test/CodeGen/RISCV/xqciac.ll
M llvm/test/CodeGen/RISCV/xqcibi-redundant-copy-elim.ll
M llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
M llvm/test/CodeGen/RISCV/xqcibm-extract.ll
M llvm/test/CodeGen/RISCV/xqcibm-insbi.ll
M llvm/test/CodeGen/RISCV/xqcibm-insert.ll
M llvm/test/CodeGen/RISCV/xqcicm.ll
M llvm/test/CodeGen/RISCV/xqcics.ll
M llvm/test/CodeGen/RISCV/xqcilia.ll
M llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
M llvm/test/CodeGen/RISCV/xqcisls.ll
M llvm/test/CodeGen/RISCV/xtheadmac.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
M llvm/test/CodeGen/RISCV/xtheadmempair.ll
M llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
M llvm/test/CodeGen/RISCV/zcb-regalloc-hints.ll
M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
M llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
M llvm/test/CodeGen/RISCV/zdinx-spill.ll
M llvm/test/CodeGen/RISCV/zibi.ll
M llvm/test/CodeGen/RISCV/zicond-fp-select-zfinx.ll
M llvm/test/CodeGen/RISCV/zicond-opts.ll
M llvm/test/CodeGen/RISCV/zilsd-spill.ll
M llvm/test/CodeGen/RISCV/zilsd.ll
Log Message:
-----------
[RISCV] Adopt SpacemitX60's scheduling model for `-mtune=generic` (#167008)
Per our discussions in RISC-V roundtable during LLVM Dev Meeting 2025,
there has been a consensus to create a base / generic scheduling model
for the most common performance tuning usages. As the first step, we
agree to use SpacemitX60's scheduling model for that purpose for the
time being, with an expectation to create a standalone generic model
that could evolve independently in the future.
This patch sets `-mtune=generic` to use SpacemitX60's scheduling model,
and documents the rationale behind it, including the roadmap ahead as we
discussed.
Commit: 350f4851d7070757545d65aba54b19b6bfceb6da
https://github.com/llvm/llvm-project/commit/350f4851d7070757545d65aba54b19b6bfceb6da
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/include/clang/ScalableStaticAnalysisFramework/Core/Model/EntityLinkage.h
M clang/lib/ScalableStaticAnalysisFramework/Core/TUSummary/TUSummaryExtractor.cpp
A clang/test/Analysis/Scalable/PointerFlow/external-inline-function-in-multi-tu.test
M clang/unittests/ScalableStaticAnalysisFramework/TUSummaryBuilderTest.cpp
Log Message:
-----------
[SSAF] Let function parameters inherit linkage from their parent functions (#201946)
SSAF treats parameters as entities and may not always associate them
back to their parent functions. Therefore, it needs to identify
parameters of functions with external linkage across different TUs.
Treating them as having no linkage (as in C++) causes the same parameter
in different TUs to be assigned different EntityIDs. As a result, the
behavior of the parameter across multiple TUs cannot be correlated.
rdar://178844032
---------
Co-authored-by: Balázs Benics <benicsbalazs at gmail.com>
Commit: 3c21c3d6095821e78690fc056522f9857c178ad3
https://github.com/llvm/llvm-project/commit/3c21c3d6095821e78690fc056522f9857c178ad3
Author: Alexey Bader <alexey.bader at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/test/OffloadTools/clang-sycl-linker/basic.ll
M clang/test/OffloadTools/clang-sycl-linker/triple.ll
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
Log Message:
-----------
[NFC][clang-sycl-linker] Standardize error messages to LLVM coding style (#202767)
Follow LLVM coding standards for error messages: use lowercase first
letter and no trailing period. This matches the style used throughout
LLVM tools (llvm-objcopy, lld, etc.) and aligns with the official
guidance in llvm/docs/CodingStandards.rst.
Updated corresponding test assertions in basic.ll and triple.ll.
Commit: 0411e39a35866c125750810e59a15e00c9484fc9
https://github.com/llvm/llvm-project/commit/0411e39a35866c125750810e59a15e00c9484fc9
Author: Mingjie Xu <xumingjie.enna1 at bytedance.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/unittests/Analysis/ScalarEvolutionTest.cpp
Log Message:
-----------
[SCEV] Speed up forgetLoop by avoiding def-use walk for loop-header PHIs (#201572)
Every cached SCEV varies with Loop `L` transitively contains an
`AddRec`, and every `AddRec` for the loop is recorded in `LoopUsers[L]`.
`forgetMemoizedResults` already closes this set transitively through
`SCEVUsers` and `ExprValueMap`.
Therefore `forgetLoop` does not need to walk the def-use chain starting
from header PHIs, it only needs to initialize `ToForget` with
`LoopUsers[L]` and explicitly remove each header PHI's entries from
`ValueExprMap` and `ConstantEvolutionLoopExitValue`, push its cached
SCEVs into `ToForget`.
As a side effect, cached SCEVs that reside in the loop body but do not
depend on any `AddRec` for the loop (e.g. a `SCEVUnknown` for an icmp)
are no longer invalidated.
Commit: ef7d2c97b4e5158a230aca54100b15cd3b9fa815
https://github.com/llvm/llvm-project/commit/ef7d2c97b4e5158a230aca54100b15cd3b9fa815
Author: Nico Weber <thakis at chromium.org>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/tools/llvm-readtapi/BUILD.gn
Log Message:
-----------
[gn] port 108b06f1797b3a6 (llvm-readtapi driver_executable) (#202826)
Commit: fb2d6709f289525497cdf731bf32085401c6b962
https://github.com/llvm/llvm-project/commit/fb2d6709f289525497cdf731bf32085401c6b962
Author: Jiahao Guo <eoonguo at gmail.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/utils/TableGen/CIRLoweringEmitter.cpp
Log Message:
-----------
[CIR] Support zero-result ops in clangir TableGen lowering (#202273)
### summary
This is follow-up to https://github.com/llvm/llvm-project/pull/199599
A CIR op can set the llvmOp field to have cir-tblgen auto-generate its
CIR→LLVM lowering instead of using a hand-written pattern.However, the
generated body forwards the result type via op.getType(), which only
compiles for single-result ops. As a result, ops with zero results could
not use this feature.
To fix this, teach CIRLoweringEmitter to emit an empty mlir::TypeRange{}
for zero-result ops. Then switch cir.lifetime.start and cir.lifetime.end
to use llvmOp (dropping their hand-written lowering). The lifetime.cir
test covers the generated path.
Commit: ffb7404d1eb1fa8cca49e2cc800b4c97688f8bab
https://github.com/llvm/llvm-project/commit/ffb7404d1eb1fa8cca49e2cc800b4c97688f8bab
Author: Fangrui Song <i at maskray.me>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang-tools-extra/clangd/index/SymbolID.h
Log Message:
-----------
[clangd] Add missing direct includes for bit.h. NFC (#202840)
This currently compile only because llvm/ADT/Hashing.h transitively
pulls in llvm/Support/SwapByteOrder.h (which includes llvm/ADT/bit.h).
Commit: 45fd70d800b6bdb7cae464bee3e78bd0d898ba5e
https://github.com/llvm/llvm-project/commit/45fd70d800b6bdb7cae464bee3e78bd0d898ba5e
Author: Vladimir Vereschaka <vvereschaka at accesssoftek.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Options/Options.td
A clang/test/CodeGenCXX/cl-pathmap.cpp
A clang/test/Driver/cl-pathmap.c
A clang/test/Preprocessor/cl-pathmap.c
Log Message:
-----------
Reland [clang-cl] Add new option /pathmap:<from>=<to> to replace the path prefix <from> with <to>. (#202830)
This option matches MSVC options and does the path substitution for the
file references in the preprocessor macros, debug and coverage
information.
This option acts as a clang's ``-ffile-prefix-map=value`` and with some
known differences in behavior with original CL's option that do not
affect the functionality:
* nomalizes the macro prefix map pathes -- removes `./` and uses the
target's
platform-specific path separator character when exanding the
preprocessor
macros -- ``-ffile-reproducible`` (but not the debug and coverage prefix
maps).
* does not require ``/experimental:deterministic`` as by MSVC. It needed
for
removing a hostname from a mangling hash gen, but clang-cl does not use
a hostname when generates the hashes.
Known issues:
* does not remap the pathes within PCH/PCM files.
Reland #198664
Commit: fe5c70101ec5ffe4db4b4ee657b341514da9008e
https://github.com/llvm/llvm-project/commit/fe5c70101ec5ffe4db4b4ee657b341514da9008e
Author: Feng Zou <feng.zou at intel.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86FixupSetCC.cpp
M llvm/test/CodeGen/X86/apx/ccmp.ll
M llvm/test/CodeGen/X86/apx/ctest.ll
M llvm/test/CodeGen/X86/apx/setzucc.ll
M llvm/test/CodeGen/X86/fast-isel-fcmp.ll
M llvm/test/CodeGen/X86/fast-isel-select-cmov2.ll
M llvm/test/CodeGen/X86/pr27591.ll
M llvm/test/CodeGen/X86/pr32284.ll
M llvm/test/CodeGen/X86/pr54369.ll
Log Message:
-----------
[X86][APX] Enable PreferLegacySetCC tuning for Novalake and Diamondrapids (#202480)
Performance measurements show legacy SetCC is still good on these platforms.
Commit: 4143eee75d13ce3a10fbf81b56220e1e13b915f1
https://github.com/llvm/llvm-project/commit/4143eee75d13ce3a10fbf81b56220e1e13b915f1
Author: Fangrui Song <i at maskray.me>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/include/llvm/ADT/Hashing.h
Log Message:
-----------
[Hashing] Replace hash_integer_value with splitmix64 finalizer (#199471)
hash_integer_value used a CityHash-era construction: read the uint64_t
value as two endian-normalized 4-byte halves via fetch32, then combine
through hash_16_bytes. Treat the integer as a number instead.
A direct hash_16_bytes(value, seed) has the right shape but inherits a
defect from its Murmur three-multiply chain: the top input bit maps
deterministically to the top output bit. Use the splitmix64 finalizer
(xmxmx) instead -- the same shape xxh3 uses for its 4-8 byte path.
bit-independence bias on eight input classes (sequential/step-aligned
ints, stack-, malloc-, code-segment-shaped pointers, random uint64):
```
// Read https://jonkagstrom.com/bit-mixer-construction/ for columns
bic_mean bic_max
fetch32 + 16_bytes: 0.04-0.14% 7-13%
hash_16_bytes: 0.18% 42%
splitmix64 xmxmx: 0.04% 0.17%
```
This also drops fetch32 and hash_16_bytes from the header; the three
byte-stable out-of-header callers were already moved to file-local
copies.
Depends on #196854
Aided by Claude Opus 4.7
Commit: 5748dcd89b907d3df745069298ad8c93bfde925a
https://github.com/llvm/llvm-project/commit/5748dcd89b907d3df745069298ad8c93bfde925a
Author: juan.vazquez <juvazq at google.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/BreakFalseDeps.cpp
Log Message:
-----------
[CodeGen] Update break-false-deps to track updates to the machine function (#202081)
Commit: 240752e73c97c49890c5d8ddb436ccbc9619bca9
https://github.com/llvm/llvm-project/commit/240752e73c97c49890c5d8ddb436ccbc9619bca9
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
A llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-memintrinsic-asan.ll
Log Message:
-----------
[AMDGPU] Lower mem intrinsics on LDS pointers in AMDGPUSwLowerLDS (#202552)
memcpy/memset/memmove on LDS pointers were left in the local address
space, silently writing into the malloc'ed pointer LDS cell instead of
the global buffer backing the lowered LDS
Collect and translate them to the global pointer like the other LDS
memory operations under asan
Commit: 5868847241e2d761843a3a9bed9f4c3703e2ac2c
https://github.com/llvm/llvm-project/commit/5868847241e2d761843a3a9bed9f4c3703e2ac2c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
M clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
Log Message:
-----------
[RISCV] Add Zvfbfa to RISCVABIInfo::coerceVLSVector checks. (#202812)
Commit: a46c5ee4eb7f5dadc38dabb9481564a9b74687c2
https://github.com/llvm/llvm-project/commit/a46c5ee4eb7f5dadc38dabb9481564a9b74687c2
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Support/GlobPattern.cpp
Log Message:
-----------
[NFC][Support] Refactor bracket parsing in GlobPattern (#202848)
Extract BitVector from Expected before flipping to
prepare for future modifications.
Assisted-by: Gemini
Commit: ac7161671cc3d64e104fa37f75f12c60150bdb1d
https://github.com/llvm/llvm-project/commit/ac7161671cc3d64e104fa37f75f12c60150bdb1d
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUtils.cpp
A llvm/test/Transforms/LoopVectorize/minmax-reduction-unknown-prof.ll
Log Message:
-----------
[LoopUtils] Mark createMinMaxOp's new select with unknown branch weights (#201750)
`createMinMaxOp()` lowers an FP min/max reduction to a freshly built
fcmp+select. That select is not derived from any existing branch, so it
carries no real profile data, and prof-verify reports a "select
annotation missing" failure. Mark the synthesized select's branch
weights as explicitly unknown when the enclosing function is profiled,
guarded by the existing profcheck-disable-metadata-fixes option.
Add a unit test covering the profiled and non-profiled cases.
Commit: d20eca15e888b6f70412792ff63a4de960a3fb2e
https://github.com/llvm/llvm-project/commit/d20eca15e888b6f70412792ff63a4de960a3fb2e
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M orc-rt/include/CMakeLists.txt
A orc-rt/include/orc-rt/sps-ci/CallSPSCI.h
M orc-rt/lib/executor/CMakeLists.txt
A orc-rt/lib/executor/sps-ci/CallSPSCI.cpp
M orc-rt/unittests/CMakeLists.txt
A orc-rt/unittests/CallSPSCITest.cpp
Log Message:
-----------
[orc-rt] Add initial call-function SPS CIs. (#202860)
Adds orc_rt_call_void_void and orc_rt_call_main, which can be used to
call functions with `void(void)` and `int(int, char*[])` signatures,
respectively.
Commit: 3c191d65110b5f54faf68d8438a9d989a1ef133d
https://github.com/llvm/llvm-project/commit/3c191d65110b5f54faf68d8438a9d989a1ef133d
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/test/tools/yaml2obj/ELF/bb-addr-map-pgo-analysis-map.yaml
Log Message:
-----------
[ObjectYAML] Fix yaml2obj crash when BBAddrMap entry has invalid feature (#201729)
Warn and skip the entry instead of dereferencing the Error-holding
Expected returned by Features::decode.
Commit: 55f4ff4306e1c64f08f5ee58164b49cee3d461fc
https://github.com/llvm/llvm-project/commit/55f4ff4306e1c64f08f5ee58164b49cee3d461fc
Author: Himadhith <79003240+Himadhith at users.noreply.github.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/tools/CMakeLists.txt
Log Message:
-----------
[cmake] Add llvm-readobj before lldb (#202715)
After #199152, following CMake error is found when building llvm-lit:
```
CMake Error at cmake/modules/AddLLVM.cmake:2816 (get_target_property):
get_target_property() called with non-existent target "llvm-readobj".
Call Stack (most recent call first):
cmake/modules/AddLLVM.cmake:1513 (get_host_tool_path)
cmake/modules/AddLLVM.cmake:1556 (export_executable_symbols)
tools/llvm-lto2/CMakeLists.txt:27 (export_executable_symbols_for_plugins)
```
Fixed by adding llvm-readobj before lldb. (Similar to
https://github.com/llvm/llvm-project/pull/201648)
Co-authored-by: himadhith <himadhith.v at ibm.com>
Commit: d4d061b85f8579397c1522febbcd25af969f423d
https://github.com/llvm/llvm-project/commit/d4d061b85f8579397c1522febbcd25af969f423d
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/codegen.c
Log Message:
-----------
[clang][bytecode] Fix right shifts greater than bitwidth (#202851)
We're not erroring in C, but we did compute the wrong result.
Commit: 696f4d5628479a828a14aa9999974d48f0aa698f
https://github.com/llvm/llvm-project/commit/696f4d5628479a828a14aa9999974d48f0aa698f
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
Log Message:
-----------
[AMDGPU] Fix immediate parsing for packed types (#202417)
We should use the element, instead of the vector type, to get floating
point Semantics.The issue is not exposed in upstream yet, but still better to
be fixed.
Commit: dac9338f7af15561910137523f73cd93422c575b
https://github.com/llvm/llvm-project/commit/dac9338f7af15561910137523f73cd93422c575b
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/IR/Function.cpp
Log Message:
-----------
[IR] Base attribute queries on Argument::getAttributes() (NFC) (#202686)
Fetch the AttributeSet for the argument and then do queries on that.
This is both less code than going through the function AttributeList,
and avoids redundant AttributeSet fetches in case where multiple
attributes are queried.
Commit: fe298c3006e1866df074aba59e4d0ca667ad341b
https://github.com/llvm/llvm-project/commit/fe298c3006e1866df074aba59e4d0ca667ad341b
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCClassDescriptorV2.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCClassDescriptorV2.h
Log Message:
-----------
[NFC][lldb] Delete dead variables in AppleObjCClassDescriptor (#202542)
Some of those were related to caching of information. However, this
cache is never consulted, making the current code misleading: one may
think we are benefiting from the cache, but we're not.
Commit: 66a0203502d2105c027b8494f6fd6d22cc9b6cfc
https://github.com/llvm/llvm-project/commit/66a0203502d2105c027b8494f6fd6d22cc9b6cfc
Author: Nikita Taranov <nikita.taranov at clickhouse.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M libcxx/include/__hash_table
A libcxx/test/std/containers/unord/unord.map/unord.map.cnstr/exceptions.pass.cpp
Log Message:
-----------
[libc++] Fix exception safety of `__hash_table::__copy_construct` (avoid memory leak) (#201452)
Slightly easier to digest repro: https://godbolt.org/z/ejjs5br5f
Commit: a983a3e76268b449dde64bc23edc8dab6d1d38de
https://github.com/llvm/llvm-project/commit/a983a3e76268b449dde64bc23edc8dab6d1d38de
Author: David Green <david.green at arm.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/sve-fixed-length.ll
Log Message:
-----------
[AArch64] Return basic cost for Sub instructions. (#202561)
This mirrors the cost we return for Add, where the custom lowering
otherwise increases the base cost to 2.
Commit: e7dcdf00efaac9d859f39347ab2e32e19914ab6b
https://github.com/llvm/llvm-project/commit/e7dcdf00efaac9d859f39347ab2e32e19914ab6b
Author: mbhade-amd <mbhade at amd.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/reset-fpenv-mmo.ll
Log Message:
-----------
[X86] LowerRESET_FPENV - use MOLoad for the constant-pool FLDENVm MMO (#201832)
LowerRESET_FPENV builds a MachineMemOperand with the MOStore flag and
attaches it to X86ISD::FLDENVm, which is mayLoad = 1. The direction
contradicts the SDNode, and SelectionDAGISel's memref filter (in
SelectCodeCommon) silently drops the MMO, leaving the final MachineInstr
without any memrefs - no miscompile, but no useful load-side metadata
either.
Sister path LowerGET_FPENV_MEM already flips MOStore -> MOLoad before
attaching its MMO to FLDENVm. Match that here so the MMO survives ISel.
Adds a MIR-trailer regression test asserting FLDENVm carries the
expected `:: (load (s224) from constant-pool, align 4)` memref.
This was found as part of @jlebar's X86 LLVM bug hunt / FuzzX effort:
https://github.com/SemiAnalysisAI/FuzzX/tree/master/x86 :
x86/bugs/014-resetfpenv-mmo-flagged-as-store-on-load
cc @jlebar
Commit: dc352aa211095ddea1292fb99be867bd6ec5f65c
https://github.com/llvm/llvm-project/commit/dc352aa211095ddea1292fb99be867bd6ec5f65c
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/IR/Value.cpp
Log Message:
-----------
[IR] Avoid unnecessary canBeFreed() calls (NFC) (#202685)
Do not call canBeFreed() if the value can't ever be freed (e.g. for
globals) or if there are no known dereferenceable bytes. The check is
relatively expensive.
(The compile-time impact is only visible when enabling deref-at-point
semantics.)
Commit: 2a3342ce298fde653769ab8ecde070078f865012
https://github.com/llvm/llvm-project/commit/2a3342ce298fde653769ab8ecde070078f865012
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M orc-rt/lib/executor/sps-ci/CallSPSCI.cpp
M orc-rt/unittests/CallSPSCITest.cpp
Log Message:
-----------
[orc-rt] Fix off-by-one error in d20eca15e88 (SPS CI for calls). (#202872)
The main-function shaped caller in d20eca15e88 had an off-by-one error
that I missed as I was looking at a stale build folder. This commit
fixes the error, and makes some changes to related unit test variable
names for consistency.
Commit: 1dc53bacd24fb555dfd2ec030a5ee33f5db3fadf
https://github.com/llvm/llvm-project/commit/1dc53bacd24fb555dfd2ec030a5ee33f5db3fadf
Author: SiHuaN <liyongtai at iscas.ac.cn>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
M llvm/test/CodeGen/RISCV/rv32-move-merge.ll
Log Message:
-----------
[RISCV][P-ext] Merge paired pli/plui in RISCVMoveMerger (#202566)
64-bit packed-splat constants are returned as i64, which SelectionDAG
splits into two i32 halves materialized as single-reg
pli.b/pli.h/plui.h. Merge matching pairs writing the two halves of a
GPRPair into the paired pli.db/pli.dh/plui.dh form.
Commit: 2865ba749a8b7612b3b22fdb498b392e814c2e84
https://github.com/llvm/llvm-project/commit/2865ba749a8b7612b3b22fdb498b392e814c2e84
Author: David Green <david.green at arm.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/test/Analysis/CostModel/AArch64/sve-arith-fp.ll
Log Message:
-----------
[AArch64] Add SVE cost tests for fp128 vectors. NFC (#202874)
Commit: 992f140ce80746282fae345abbc655e0db1afb42
https://github.com/llvm/llvm-project/commit/992f140ce80746282fae345abbc655e0db1afb42
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/InstructionSimplify.h
M llvm/lib/Analysis/InstructionSimplify.cpp
Log Message:
-----------
[InstSimplify] Expose simplifyIntrinsic (NFC) (#202577)
With the objective of using it in the constant-folder.
Commit: 81967cfb4ca816c59a1c9719f4aa773730686310
https://github.com/llvm/llvm-project/commit/81967cfb4ca816c59a1c9719f4aa773730686310
Author: ritter-x2a <9519134+ritter-x2a at users.noreply.github.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
Log Message:
-----------
[AMDGPU] Document that only naturally aligned atomics of up to 64 bits are supported by the AMDGPU backend (#200167)
We get an error from AtomicExpandPass if those constraints are not satisfied.
The 64-bit limit is set [here, in AMDGPUISelLowering.cpp](https://github.com/llvm/llvm-project/blob/5cac2751fb9cf3112d16717b278e40d07dd6cfdc/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp#L645).
This patch also introduces a new "Unsupported IR Constructs" section to the AMDGPUUsage doc, where we can document more such cases.
Commit: daa49cfc2e01ff9df3400321ee308ec82b23ff34
https://github.com/llvm/llvm-project/commit/daa49cfc2e01ff9df3400321ee308ec82b23ff34
Author: Peiqi Li <voyager.lpq at gmail.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/UseAfterMoveCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/use-after-move.cpp
Log Message:
-----------
[clang-tidy] Fix false positive in bugprone-use-after-move with std::forward on derived classes (#199905)
The `bugprone-use-after-move` check correctly identified partial moves
when using `std::move` by matching the `ImplicitCastExpr`
(DerivedToBase) as the parent of the call. However, when using
`std::forward<Base>`, the cast occurs inside the argument, causing the
matcher to miss the cast and falsely report a use-after-move.
This patch uses `traverse(TK_AsIs, expr(hasParent(...)))` on the first
argument to navigate bottom-up, reliably capturing the hidden
`ImplicitCastExpr`. This ensures both partial moves and forwards are
consistently recognized, eliminating the false positive.
Assisted by AI to check code.
Fixes #63202
Commit: a424861be0f82ca8e05dd0ae3fb433805a1fec20
https://github.com/llvm/llvm-project/commit/a424861be0f82ca8e05dd0ae3fb433805a1fec20
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M clang/include/clang/Analysis/CallGraph.h
M clang/lib/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphExtractor.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphExtractorTest.cpp
Log Message:
-----------
[clang][ssaf] CallGraph extractor should ignore objc callees for now (#202606)
Ignoring them is better than crashing/asserting on nullptr derefs.
Fixes: rdar://179104950
Commit: 1dcb977d17611721e3b3b51b6557197c45762275
https://github.com/llvm/llvm-project/commit/1dcb977d17611721e3b3b51b6557197c45762275
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M clang/include/clang/Basic/OpenMPKinds.h
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen.cpp
Log Message:
-----------
[clang][OpenMP] Improve loop structure for distributed loops (pt 1: reductions) (#201670)
This is a part of a series of patches that rework OpenMP cross-team
reductions.
This patches wires the existing
`kmp_sched_distr_static_chunk_sched_static_chunkone` to be used by
CodeGen (this patch is restricted to reduction loops).
Example of the intended change of this patch:
```
target teams distribute parallel for reduction(+:s)
for (i = 0; i < N; i++) s += a[i];
```
Before:
```
__kmpc_distribute_static_init(91)
for (team_lb = team*nthreads; team_lb < N; team_lb += nteams*nthreads) {
__kmpc_for_static_init(33)
for (iv = team_lb + tid; iv < team_lb + nthreads; iv += nthreads) {
priv += a[iv];
}
__kmpc_nvptx_parallel_reduce_nowait_v2
}
__kmpc_nvptx_teams_reduce_nowait_v2
```
After:
```
__kmpc_for_static_init(93)
for (iv = team*nthreads + tid;
iv < N;
iv += nteams*nthreads) {
priv += a[iv];
}
__kmpc_nvptx_parallel_reduce_nowait_v2
__kmpc_nvptx_teams_reduce_nowait_v2
```
Performance:
All performance tests can be reproduced with
https://github.com/ro-i/xteam-test @ commit
6025e5afc14dd6e65ee2658e5001c16e9b9245ff. To reproduce, simply create a
`local.mk` file in the cloned directory with a suitable `OFFLOAD_ARCH`
for your machine and `CXX_trunk` + `CXX_trunk_cg` set to the paths of
the clang++ binaries for llvm/main and this patch. (llvm/main should
best be at the commit that is currently the base for this PR. At the
moment, this is 69f7aeb52e71ebb7d264bc9e613bc4bc90cb0c47). Then, run
`make trunk trunk_cg` to build the benchmark binaries for 208 and 10400
teams. Run them with `./run_bench.sh -rq -n10 red_trunk_208
red_trunk_cg_208 red_trunk_10400 red_trunk_cg_10400` to get the avg
performance numbers over 10 rounds. This tests multiple reduction
workloads, including reductions that run in the Generic-SPMD mode, with
208 teams and with 10400 teams, both à 512 threads, and with a reduction
array size of 177,777,777. I tested on a gfx942 and found the following
numbers showing the performance of this patch relative to the baseline:
```
red_comb_sep_arr_32 double change for 208 teams: +0.01% change for 10400 teams: +5.53%
red_sum_arr_32 double change for 208 teams: +570.47% change for 10400 teams: -2.23%
red_comb double change for 208 teams: +350.30% change for 10400 teams: +0.72%
red_comb_sep double change for 208 teams: +4.82% change for 10400 teams: +2.18%
red_dot double change for 208 teams: +202.45% change for 10400 teams: +3.48%
red_indirect double change for 208 teams: +239.33% change for 10400 teams: +4.63%
red_kernel_part double change for 208 teams: +3.30% change for 10400 teams: +3.43%
red_max double change for 208 teams: +273.46% change for 10400 teams: +5.12%
red_mult double change for 208 teams: +239.50% change for 10400 teams: +5.23%
red_sum double change for 208 teams: +239.47% change for 10400 teams: +5.15%
red_pi double change for 208 teams: +90.06% change for 10400 teams: +78.67%
red_comb_sep_arr_32 uint change for 208 teams: -0.16% change for 10400 teams: +26.98%
red_sum_arr_32 uint change for 208 teams: +139.64% change for 10400 teams: -14.55%
red_dot uint change for 208 teams: +202.92% change for 10400 teams: +5.11%
red_max uint change for 208 teams: +221.41% change for 10400 teams: +6.54%
red_sum uint change for 208 teams: +220.83% change for 10400 teams: +7.80%
red_comb_sep_arr_32 ulong change for 208 teams: -0.19% change for 10400 teams: +5.80%
red_sum_arr_32 ulong change for 208 teams: +523.98% change for 10400 teams: -3.17%
red_dot ulong change for 208 teams: +232.14% change for 10400 teams: +3.57%
red_max ulong change for 208 teams: +279.87% change for 10400 teams: +6.17%
red_sum ulong change for 208 teams: +261.54% change for 10400 teams: +5.72%
red_comb_sep_arr_32 Value change for 208 teams: +0.22% change for 10400 teams: +0.04%
red_sum_arr_32 Value change for 208 teams: +423.38% change for 10400 teams: +9.08%
red_dot Value change for 208 teams: +153.87% change for 10400 teams: -2.62%
red_max Value change for 208 teams: +1097.62% change for 10400 teams: +261.16%
red_sum Value change for 208 teams: +358.88% change for 10400 teams: +21.44%
```
Claude assisted with this patch.
Commit: 8da9d925ac73becc1733c6733ffabc2020131912
https://github.com/llvm/llvm-project/commit/8da9d925ac73becc1733c6733ffabc2020131912
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M mlir/include/mlir/Interfaces/MemorySlotInterfaces.td
M mlir/lib/Transforms/Mem2Reg.cpp
M mlir/test/Dialect/LLVMIR/mem2reg-dbginfo.mlir
M mlir/test/Transforms/mem2reg.mlir
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
Log Message:
-----------
[mlir][mem2reg] fix 197158 by moving visitReplacedValues call (#198552)
Fix #197158 and #200844 by moving the `visitReplacedValues` calls
between `promoteInRegion` and `removeBlockingUses` , as well as setting
the insertion point before the replaced store operation before calling
the `PromotableMemOpInterface::getStored` API (instead of setting the
insertion point after).
The action order change is done at the top level. The `promoteInRegion`
are done for all regions in post order, then the `visitReplacedValues`
are done for all regions, and then only the `removeBlockingUses` are
done for all regions in post order. This ensures that any load results
that would happen to be used in a later stored is not deleted by
`removeBlockingUses` before it is used by `visitReplacedValues`.
The insertion point change ensures that the stored values passed to
`visitReplacedValues` dominate the related store operations. Otherwise,
typical `visitReplacedValues` that set insertion points at the store
operation and use the stored values generated invalid IR when
`getStored` generates new IR (like bitcasts for the LLVM dialect
implementation).
Commit: be1f53f568394ee7c1976a9a5785c8127dbcdf39
https://github.com/llvm/llvm-project/commit/be1f53f568394ee7c1976a9a5785c8127dbcdf39
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/MemberPointer.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
Log Message:
-----------
[clang][bytecode] Save a `Type*` in integral pointers instead of a descriptor (#202835)
This way we don't need to allocate a descriptor via the `Program`, which
is for global data.
Commit: e1110dabc49d10c9353d6af7555c56f55fb0cca8
https://github.com/llvm/llvm-project/commit/e1110dabc49d10c9353d6af7555c56f55fb0cca8
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M flang/include/flang/Semantics/openmp-utils.h
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/openmp-utils.cpp
A flang/test/Semantics/OpenMP/target-enter-data-temp-descriptor-omp61.f90
A flang/test/Semantics/OpenMP/target-enter-data-temp-descriptor.f90
Log Message:
-----------
[Flang][OpenMP][Sema] Add OpenMP warning when mapping local descriptors to device on enter without a corresponding exit (#201060)
This PR aims to add a new warning to Flang that will emit when a user
tries to map a local/temporary descriptor to device on an enter
directive without also applying it to a corresponding exit directive.
This problem can cause some pretty unique and difficult to track down
errors in programs as it can result in a user unintentionally locking
into place a stack allocated descriptor that has fallen out of scope,
which can result in a later clash with another stack allocated variable
that's being mapped and just happens to reside in the old descriptor
address range.
So this PR attempts to warn about this problem to prevent users doing
so, it's of note that we handle some of these cases in our
MapInfoFinalization pass, but I believe we should still include these
cases for portability reasons and incase we ever backtrack on our
decision to silently support some of these cases.
Made this warning as it was a suggestion from Michael Klemm and seemed
like a good PR to add to guide users to avoid this pattern (as it
unfortunately seems to be a common one that pops up). I'll perhaps look
into an optimization pass that tries to resolve some of these cases
silently in the future, but this will have to do in the meantime.
Commit: e65b4e7fa233fd15fb1e84a66329b8936a594b2d
https://github.com/llvm/llvm-project/commit/e65b4e7fa233fd15fb1e84a66329b8936a594b2d
Author: flovent <flbven at protonmail.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/DeleteNullPointerCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/readability/delete-null-pointer.cpp
Log Message:
-----------
[clang-tidy] Avoid invalid fixes in `readability-delete-null-pointer` (#202488)
Only provide warnings (not fixits) when `IfStmt` has condition variable
or initializer.
Note that i didn't provide fixit for the situation that conditon
variable is different with the pointer variable being cast to bool
because i think this is rare. (the third newly added testcase)
Closes #202312.
---------
Co-authored-by: Zeyi Xu <zeyi2 at nekoarch.cc>
Commit: 6f2726dc2c03aa78532d60746cdfdff069033cc6
https://github.com/llvm/llvm-project/commit/6f2726dc2c03aa78532d60746cdfdff069033cc6
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M libcxx/include/__type_traits/rank.h
Log Message:
-----------
[libc++] Assume that __array_rank is provided by the compiler (#202511)
All compilers we support have `__array_rank`, so we can remove the
preprocessor branch for supporting compilers which don't provide it.
Commit: 389e924ac7df45d34b613a46d24940abcfeb879d
https://github.com/llvm/llvm-project/commit/389e924ac7df45d34b613a46d24940abcfeb879d
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/Loads.h
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/LICM/scalar-promote.ll
M llvm/test/Transforms/SimplifyCFG/speculate-store.ll
Log Message:
-----------
[LICM][SimplifyCFG] Ignore frees for writable dereferenceability check (#202589)
Both of these places only explicitly check for dereferenceability
because this is required for the `writable` attribute. Actual
dereferenceability has already been established at this point, e.g.
based on a prior access. As such, we can ignore frees here. We only care
that the argument has an appropriately sized `dereferenceable`
attribute.
Commit: caa0f0395f4fb95f1d51cd5fdddfe6fcdef038e9
https://github.com/llvm/llvm-project/commit/caa0f0395f4fb95f1d51cd5fdddfe6fcdef038e9
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
Log Message:
-----------
[LICM] Fix typo in variable name (NFC) (#202889)
Commit: 1a09ed10e5c417b5e71f893e63a21498216dd258
https://github.com/llvm/llvm-project/commit/1a09ed10e5c417b5e71f893e63a21498216dd258
Author: Luke Lau <luke at igalia.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/test/Transforms/LoopVectorize/VPlan/predicator.ll
Log Message:
-----------
[VPlan] Insert VPBlendRecipes in post order. NFC (#201782)
#201783 wants to optimize blend masks by peeking through the contents of
other phi nodes. Currently we eagerly convert phis to blends in reverse
post order, so switch it to post order so that phis at the bottom can
see the phis in their uses.
Commit: 93e03fc2666e10b4e32091bc27d35709f49c9443
https://github.com/llvm/llvm-project/commit/93e03fc2666e10b4e32091bc27d35709f49c9443
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/arm/floatdidf.S
A compiler-rt/lib/builtins/arm/floatdisf.S
A compiler-rt/lib/builtins/arm/floatsidf.S
A compiler-rt/lib/builtins/arm/floatsisf.S
A compiler-rt/lib/builtins/arm/floatundidf.S
A compiler-rt/lib/builtins/arm/floatunsidf.S
A compiler-rt/lib/builtins/arm/floatunsisf.S
A compiler-rt/test/builtins/Unit/floatdidfnew_test.c
A compiler-rt/test/builtins/Unit/floatdisfnew_test.c
A compiler-rt/test/builtins/Unit/floatsidfnew_test.c
A compiler-rt/test/builtins/Unit/floatsisfnew_test.c
A compiler-rt/test/builtins/Unit/floatundidfnew_test.c
A compiler-rt/test/builtins/Unit/floatundisfnew_test.c
A compiler-rt/test/builtins/Unit/floatunsidfnew_test.c
A compiler-rt/test/builtins/Unit/floatunsisfnew_test.c
Log Message:
-----------
[compiler-rt][ARM] Optimized integer -> FP conversions (#179928)
This commit adds a total of 8 new functions, all converting an integer
to a floating-point number, varying in 3 independent choices:
* input integer size (32-bit or 64-bit)
* input integer type (signed or unsigned)
* output float format (32-bit or 64-bit)
The two conversions of 64-bit integer to 32-bit float live in the same
source file, to save code size, since that conversion is one of the more
complicated ones and the two functions can share most of their code,
with only a few instructions differing at the start to handle negative
numbers (or not).
Commit: 851919b9c4e4e9a32b86b4a79853dcb58cbea7be
https://github.com/llvm/llvm-project/commit/851919b9c4e4e9a32b86b4a79853dcb58cbea7be
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/test/Target/SPIRV/struct.mlir
Log Message:
-----------
[mlir][SPIR-V] Serialize BufferBlock struct decoration (#202870)
Add BufferBlock to the no-operand decoration switch
Commit: d602a9343a0e5db98548e360370cebb02bfd421c
https://github.com/llvm/llvm-project/commit/d602a9343a0e5db98548e360370cebb02bfd421c
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M libcxx/include/__configuration/availability.h
M libcxx/test/std/strings/basic.string/string.capacity/over_max_size.pass.cpp
M libcxx/utils/libcxx/test/features/availability.py
M libcxxabi/test/test_demangle.pass.cpp
Log Message:
-----------
[libc++] Fill in Apple availability for LLVM 21 (#202347)
macOS 26.4 and aligned platforms have been released and they are roughly
synchronized to libc++ 21. As a drive-by, also add missing versions for
previous releases.
This also allows reverting #199682 which moved an XFAIL to UNSUPPORTED
to silence CI failures temporarily.
Commit: 1e0a4c7a9154e46ef52a7c5b0ddbca69fbdcfacd
https://github.com/llvm/llvm-project/commit/1e0a4c7a9154e46ef52a7c5b0ddbca69fbdcfacd
Author: Gil Rapaport <gil.rapaport at mobileye.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M mlir/include/mlir/Conversion/ConvertToEmitC/ConvertToEmitCPatternInterface.td
M mlir/include/mlir/Conversion/ConvertToEmitC/ToEmitCInterface.h
M mlir/include/mlir/Conversion/FuncToEmitC/FuncToEmitC.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/lib/Conversion/ArithToEmitC/ArithToEmitC.cpp
M mlir/lib/Conversion/ConvertToEmitC/ConvertToEmitCPass.cpp
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitCPass.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
M mlir/test/Conversion/FuncToEmitC/func-to-emitc-failed.mlir
M mlir/test/Conversion/FuncToEmitC/func-to-emitc.mlir
M mlir/test/Target/Cpp/func.mlir
Log Message:
-----------
[mlir][emitc] Lower multiple results as a struct (#200659)
Previously, func-to-emitc lowering rejected func.{func,call,return} with
more than one result/operand. Such ops are directly handled by the
translator which emits an `std::tuple` packing ther results, but is only
relevant for C++ users. This patch lifts that restriction by packing
multiple return values into an automatically-generated struct, e.g. for
a function returning (i32, i32):
emitc.class struct @return_i32_i32 {
emitc.field @field0 : i32
emitc.field @field1 : i32
}
On return, the operands are packed into a local struct variable which is
then loaded and returned. On call sites, the struct is stored in a local
variable, and each field is extracted to recreate the individual SSA
values of the original results. As with single-result functions,
`emitc.array` return types are not supported.
If a class with that name already exists, it is verified to have exactly
the expected fields with the correct types and no methods. Two functions
with the same return type tuple share a single class definition.
Backward compatibility is maintained by a new lower-to-cpp option which
defaults to `true` (unlike the same flag in memref-to-emitc), in which case
func-to-emitc continues to bail out on multi-return functions.
Assisted-by: Copilot
Commit: 2b201d89bab6d0f4f3c017ed3ab358500c1d8960
https://github.com/llvm/llvm-project/commit/2b201d89bab6d0f4f3c017ed3ab358500c1d8960
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp
A llvm/test/CodeGen/Xtensa/literal.ll
Log Message:
-----------
[Xtensa] Fix literal section emit for ConstantPool entries. (#200132)
Fix literal section switching in XtensaTargetStreamer.
https://github.com/llvm/llvm-project/issues/190204
Commit: 14229de6dfe069ff781b47d3757854f561d79f59
https://github.com/llvm/llvm-project/commit/14229de6dfe069ff781b47d3757854f561d79f59
Author: Folkert de Vries <folkert at folkertdev.nl>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
M llvm/lib/Target/Mips/MipsSEISelLowering.h
M llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
Log Message:
-----------
[MIPS] int <-> `half` conversions with `+msa` (#201897)
Currently these conversions hit an instruction selection failure
https://godbolt.org/z/5YK4T71Wf. The backend marks most operations on
`f16` as `Promote`, but these conversions were (I assume) forgotten.
I've modeled this based on the implementation for s390x, because like
MIPS the `f16` type is storage-only there: you can pass it around etc.
but actual operations are done via promotion to `f32` or `f64`.
https://github.com/llvm/llvm-project/blob/a4e48b5d1a5dc7af00c4adb4076145afd9846739/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp#L7027-L7091
Commit: 0a45515e9e386233970b56b34a65d7442ac37e5f
https://github.com/llvm/llvm-project/commit/0a45515e9e386233970b56b34a65d7442ac37e5f
Author: Mel Chen <mel.chen at sifive.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan][NFC] Simplify reverse access pattern detection in EVL vectorization (#199510)
This PR demonstrates how to decouple the transformation of reverse
accesses during `VPlanTransforms::optimizeEVLMasks` from the reverse
operations of load results or stored values. First, `optimizeEVLMask`
transforms:
```
vptr = vec_end_ptr (ptr, VF)
res = masked.load(vptr, vector.reverse(mask))
-->
vptr = vec_end_ptr (ptr, evl)
load = vp.load(vptr, vp.reverse(mask_w/o_header_mask), evl)
res = splice.left(poison, load, evl)
```
```
vptr = vec_end_ptr (ptr, VF)
masked.store(stored_val, vptr, vector.reverse(mask))
-->
vptr = vec_end_ptr (ptr, evl)
splice = splice.right(store_val, poison, evl)
vp.store(splice, vp.reverse(mask_w/o_header_mask), evl)
```
To maintain cost model consistency, `optimizeEVLMasks` introduces the
following simplification rules to fold splice and vector.reverse to
vp.reverse.
```
vector.reverse(splice.left(poison, v, evl))
-->
vp.reverse(v, true, evl)
splice.right(vector.reverse(v), poison, evl)
-->
vp.reverse(v, true, evl)
```
As a result, the permutations elimination can now take place directly
before the EVL lowering. However, a side effect is that we might
subsequently need to clean up redundant splices after EVL lowering.
Commit: dce55a9f6cfce57e922e0e8f4583da781628e234
https://github.com/llvm/llvm-project/commit/dce55a9f6cfce57e922e0e8f4583da781628e234
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/AssumeBundleBuilder.h
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/Utils/AssumeBundleBuilder.cpp
M llvm/test/Transforms/InstCombine/assume.ll
Log Message:
-----------
[InstCombine] Remove knowledge retention folding (#202890)
The knowledge retention API for simplifying assumes isn't that useful
anymore, since most simplifications done by it are now done
unconditionally directly in InstCombine. It's also known to miscompoile
multiple patterns.
Commit: b000f9032911f32c0e68e373e083ccc90aae0005
https://github.com/llvm/llvm-project/commit/b000f9032911f32c0e68e373e083ccc90aae0005
Author: SiHuaN <liyongtai at iscas.ac.cn>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/riscv_packed_simd.h
A clang/test/CodeGen/RISCV/rvp-intrinsics.c
A cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
Log Message:
-----------
[RISCV] Add riscv_packed_simd.h for P extension intrinsics (#181115)
Add `riscv_packed_simd.h` with initial RISC-V P extension intrinsics, covering:
- Packed Splat
- Packed Addition and Subtraction
- Packed Addition with Scalar
- Packed Saturating Addition and Subtraction
- Packed Shift-Add
- Packed Minimum and Maximum
- Packed Shifts
- Packed Logical Operations
The intrinsics are implemented as thin wrappers over standard C operators
and existing generic builtins (`__builtin_elementwise_add_sat` etc.), letting
the RISC-V backend lower the resulting `<N x iN>` IR to P-ext instructions.
No new clang builtins or `llvm.riscv.*` intrinsics are introduced.
Spec: https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc
Commit: 7087ea37449027cc4c73a375b542cdc397c4474b
https://github.com/llvm/llvm-project/commit/7087ea37449027cc4c73a375b542cdc397c4474b
Author: Tim Besard <tim.besard at gmail.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
A llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_relaxed_printf_string_address_space/multi-function-printf.ll
Log Message:
-----------
[SPIR-V] Look up printf format string type in the correct function (#201523)
addPrintfRequirements() resolved the SPIR-V type of the format string
operand via getSPIRVTypeForVReg() without passing the instruction's
parent MachineFunction, so the lookup defaulted to the registry's CurMF:
whichever function happened to be processed last. Virtual register
numbers are only unique within a function, so in multi-function modules
the check could inspect an unrelated function's type, misreading its
second operand as the format string's storage class (an OpTypeInt's
width immediate, in the added test). For a format string in the constant
address space this spuriously triggered the fatal
"SPV_EXT_relaxed_printf_string_address_space is required" error, or
silently added the unnecessary extension when it was available;
conversely, the requirement could be silently omitted when the colliding
vreg had no recorded type.
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: ee28f5d4a3ed32c2759516983f66988e31ea1824
https://github.com/llvm/llvm-project/commit/ee28f5d4a3ed32c2759516983f66988e31ea1824
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M libcxx/include/__utility/is_pointer_in_range.h
Log Message:
-----------
[libc++] Make __is_less_than_compatable a variable template (#202525)
This makes the code a bit more readable and improves compile times a
bit, since variable templates are faster to instantiate than class
templates.
Commit: d8388a15b33e67fd297a47a0e6ee80c3a5cd947a
https://github.com/llvm/llvm-project/commit/d8388a15b33e67fd297a47a0e6ee80c3a5cd947a
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/predicate-as-counter-phi.ll
Log Message:
-----------
[AArch64] Use PNR rather than PPR register class for aarch64svcount (#202394)
While predicates and predicate-as-counter both use the same underlying
registers, within LLVM they use different register classes (PPR vs PNR).
Mapping aarch64svcount to the PPRRegClass results in some unnecessary
cross register class copies around PHIs, which results in some
unnecessary moves.
Commit: a4c8e3dd883cbaa61c75fef25bf496bb3bd3350a
https://github.com/llvm/llvm-project/commit/a4c8e3dd883cbaa61c75fef25bf496bb3bd3350a
Author: David Spickett <david.spickett at arm.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M lldb/docs/resources/lldbplatformpackets.md
M lldb/docs/resources/overview.md
Log Message:
-----------
[lldb][docs] Document what a Platform is (#202332)
Fixes #201875.
In #201875 a user was understandably confused what a platform even is,
and I had never had to explain it from the conceptual point of view
either.
So I wrote a long explanation
(https://github.com/llvm/llvm-project/issues/201875#issuecomment-4634087717)
specific to what they were trying to do. I don't think we need all that
in the docs and we don't have a great place for it anyway.
My alternative is:
* A high level explanation in the overview, to say what a platform does.
* A link from there to https://lldb.llvm.org/use/remote.html which has a
practical example of using one.
* A note in the platform extensions doc that our platform mode is not
related to gdb's extended remote.
It should be possible to locate all that from website search, and
failing that, lldb experts will be able to find it and link to it in
future discussions.
Commit: 78d49002ce6595237f7702999c8f30b00d7a4302
https://github.com/llvm/llvm-project/commit/78d49002ce6595237f7702999c8f30b00d7a4302
Author: anjenner <161845516+anjenner at users.noreply.github.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
A llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
Log Message:
-----------
AMDGPU/GlobalISel: Implement RegBankLegalize rules for SALUFloat variants of G_INTRINSIC_TRUNC, G_FFLOOR and G_FCEIL. (#187679)
As requested on PR #179954.
Commit: 40457f351f1dd9edda9679a6c63b48c7c73dcb4c
https://github.com/llvm/llvm-project/commit/40457f351f1dd9edda9679a6c63b48c7c73dcb4c
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/BlockInCriticalSectionChecker.cpp
M llvm/include/llvm/ADT/ImmutableList.h
M llvm/unittests/ADT/ImmutableListTest.cpp
Log Message:
-----------
[llvm][ADT] Make ImmutableList conform the fwd iterator concept (#202580)
We missed post increment and a couple of typedefs. This would enable
llvm algorithms like filter_range, etc.
Commit: 51fb7eee9f460c22fe898ea5defcca94290109bb
https://github.com/llvm/llvm-project/commit/51fb7eee9f460c22fe898ea5defcca94290109bb
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
Log Message:
-----------
[SPIR-V] Remove duplicate SPV_INTEL_int4 extension map entry (#202871)
Commit: 0345e7d8edb268dc9318f439cb50bbaff399067a
https://github.com/llvm/llvm-project/commit/0345e7d8edb268dc9318f439cb50bbaff399067a
Author: Aaditya <115080342+easyonaadit at users.noreply.github.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
Log Message:
-----------
[AMDGPU] Support Wave Reduction for i16 types - 1 (#194808)
Supported Ops: `min`, `umin`, `max`, `umax`.
16-bit wave reduce ops are promoted to 32-bit
operations before ISEL. From there they use the
existing implementations for 32-bit reductions.
Assisted by - Claude-sonnet:4.6
Commit: ac0f0407a8b37c7c22ae4b7a0e32ef7df078b1b7
https://github.com/llvm/llvm-project/commit/ac0f0407a8b37c7c22ae4b7a0e32ef7df078b1b7
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M orc-rt/include/orc-rt/NativeDylibManager.h
M orc-rt/lib/executor/NativeDylibManager.cpp
M orc-rt/lib/executor/Unix/NativeDylibAPIs.inc
M orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
M orc-rt/unittests/NativeDylibManagerTest.cpp
Log Message:
-----------
[orc-rt] Treat empty path as "process symbols" in NativeDylibManager. (#202905)
NativeDylibManager::load now handles an empty path by returning the
process's global lookup handle (RTLD_DEFAULT on POSIX) directly,
bypassing dlopen and the shutdown-time dlclose registration. This
matches the behavior of OrcTargetProcess's SimpleExecutorDylibManager.
Commit: e6a70ac8858998edde9c7bdd243ec9d169ae9e45
https://github.com/llvm/llvm-project/commit/e6a70ac8858998edde9c7bdd243ec9d169ae9e45
Author: Gil Rapaport <gil.rapaport at mobileye.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M mlir/include/mlir/Conversion/ConvertToEmitC/ConvertToEmitCPatternInterface.td
M mlir/include/mlir/Conversion/ConvertToEmitC/ToEmitCInterface.h
M mlir/include/mlir/Conversion/FuncToEmitC/FuncToEmitC.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/lib/Conversion/ArithToEmitC/ArithToEmitC.cpp
M mlir/lib/Conversion/ConvertToEmitC/ConvertToEmitCPass.cpp
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitCPass.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
M mlir/test/Conversion/FuncToEmitC/func-to-emitc-failed.mlir
M mlir/test/Conversion/FuncToEmitC/func-to-emitc.mlir
M mlir/test/Target/Cpp/func.mlir
Log Message:
-----------
Revert "[mlir][emitc] Lower multiple results as a struct (#200659)" (#202911)
This reverts commit 1e0a4c7a9154e46ef52a7c5b0ddbca69fbdcfacd.
Failed buildbot:
https://lab.llvm.org/buildbot/#/builders/116/builds/29302
Commit: 651afa86119fd138488490862d1418eb40a43473
https://github.com/llvm/llvm-project/commit/651afa86119fd138488490862d1418eb40a43473
Author: Peter Smith <peter.smith at arm.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M lld/ELF/Relocations.cpp
A lld/test/ELF/aarch64-thunk-bti-overlay-reuse.s
A lld/test/ELF/arm-thunk-overlay-reuse.s
Log Message:
-----------
[LLD][ELF] Do not reuse thunks in OVERLAYs (#200415)
We cannot guarantee that a thunk in an OVERLAY will be in memory at the
same time as the caller if the caller is not in the same output section.
It is safe for a caller in an OVERLAY to reuse a thunk in a non-OVERLAY
section as we know that will be in memory. Thunks that are placed
before their target, are alternative entry points and can also be reused.
Resurrect the isThunkSectionCompatible function that was recently
removed as it served a similar purpose for thunks in different
partitions.
Potentially fixes #199966 which mentions a similar problem for sections
assigned to TCM (Tightly Coupled Memory). It should be possible to model
a TCM as an OVERLAY. If not then there may need to be a command-line
option to inhibit thunk sharing across output sections.
Commit: 322f5d0e2d082f1115c28e66d477aafc2c5e47f9
https://github.com/llvm/llvm-project/commit/322f5d0e2d082f1115c28e66d477aafc2c5e47f9
Author: Aaditya <115080342+easyonaadit at users.noreply.github.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
Log Message:
-----------
[AMDGPU] Support Wave Reduction for i16 types - 2 (#194810)
Supported Ops: `add`, `sub`.
Commit: b7c9fd965dbd24189e3b757e8f74eea985d1edc5
https://github.com/llvm/llvm-project/commit/b7c9fd965dbd24189e3b757e8f74eea985d1edc5
Author: Aaditya <115080342+easyonaadit at users.noreply.github.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
Log Message:
-----------
[AMDGPU] Support Wave Reduction for i16 types - 3 (#194812)
Supported Ops: `and`, `or`, `xor`.
Commit: f7bfc6c256e6a0937cfae569c1bbaaea4ca60d5b
https://github.com/llvm/llvm-project/commit/f7bfc6c256e6a0937cfae569c1bbaaea4ca60d5b
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Log Message:
-----------
[InstCombine][NFC] Drop ignore bundles when iterating the bundles (#202903)
Commit: ce811aacef9a35c0765aa39381340993459fbd33
https://github.com/llvm/llvm-project/commit/ce811aacef9a35c0765aa39381340993459fbd33
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/test/CodeGen/X86/pr53842.ll
Log Message:
-----------
[X86] pr53842.ll - add test coverage for ICMP_SGT/SLT cases (#202906)
Commit: 690b0b0c63125aaf6b517df9d528789bb8c9c08a
https://github.com/llvm/llvm-project/commit/690b0b0c63125aaf6b517df9d528789bb8c9c08a
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
M llvm/test/Transforms/LoopVectorize/RISCV/gather-scatter-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-gather-scatter.ll
M llvm/test/Transforms/LoopVectorize/cast-costs.ll
M llvm/test/Transforms/LoopVectorize/vscale-cost.ll
Log Message:
-----------
[LV] Add initial costs for VPInstructionWithType::computeCost (#198291)
I noticed this was previously always returning a cost of 0
due to fear of triggering the (now deleted) legacy/vplan
cost model assert. Since the assert has now been removed
this should be safe to implement properly. I haven't
filled in the costs for all types yet, since there is
currently no way to expose those code paths. I suspect
for things like VPInstruction::StepVector the recipe is
always in the vector preheader and we never ask for its
cost.
Commit: c2112e925e99d93dff671e2254e3e999dccf25dd
https://github.com/llvm/llvm-project/commit/c2112e925e99d93dff671e2254e3e999dccf25dd
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
Log Message:
-----------
[lldb][Windows] Fix ECHO_TO_FILE/ECHO_APPEND_FILE (#202612)
The Windows recipes for these macros were `printf "%s\n" $(1)`. The
callers wrap content in single quotes (for the POSIX printf), but the
test recipes run under `cmd.exe` on Windows, which keeps the single
quotes literal and word-splits on spaces, and the bundled `printf`
additionally mangles backslashes and spaces. The result is garbage
generated files (e.g. a modulemap whose first line is `'module`, or a
truncated SDK path from a "Program Files" directory).
Write the file with cmd's `echo` after stripping the callers' single
quotes. `echo` runs in the recipe shell, so unlike GNU make's `$(file
...)` it still works after a preceding `MKDIR_P` in the same recipe.
rdar://179218545
Commit: d4445f38fbf35ff11dfeb7870aae5dff2a9baecd
https://github.com/llvm/llvm-project/commit/d4445f38fbf35ff11dfeb7870aae5dff2a9baecd
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCClassDescriptorV2.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCClassDescriptorV2.h
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV1.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV1.h
M lldb/source/Plugins/LanguageRuntime/ObjC/ObjCLanguageRuntime.h
Log Message:
-----------
[lldb][NFC] Use unique ptr in AppleObjCRuntime::GetMetaclass (#202893)
These methods have no reason to return a shared pointer.
Commit: 84285e4b27c7a286e864823904dc4a67aa09cca5
https://github.com/llvm/llvm-project/commit/84285e4b27c7a286e864823904dc4a67aa09cca5
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/DebuggerThread.cpp
M lldb/source/Plugins/Process/Windows/Common/DebuggerThread.h
Log Message:
-----------
[NFC][lldb][Windows] Clean up DebuggerThread (#202719)
- Fix typos in a llvm_unreachable string and a local variable name.
- Replace a C-style downcast to HostProcessWindows with static_cast.
- Drop redundant braces around a single-statement if and add the
namespace-closer comment in the header.
Commit: d1f15d05f73a6f9edbc678055c35ac0232a0f837
https://github.com/llvm/llvm-project/commit/d1f15d05f73a6f9edbc678055c35ac0232a0f837
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/NativeThreadWindows.cpp
Log Message:
-----------
[NFC][lldb][Windows] Clean up NativeThreadWindows (#202723)
- Drop unused #includes lldb/Target/Process.h and lldb/lldb-forward.h.
- Inline the one-shot NativeProcessProtocol& local in DoResume and
modernize GetStopReason's stale legacy log->Printf idiom to LLDB_LOGF.
Commit: 284681ed94060d41cab926ea2b82de309d43c1f8
https://github.com/llvm/llvm-project/commit/284681ed94060d41cab926ea2b82de309d43c1f8
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/TargetThreadWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/TargetThreadWindows.h
Log Message:
-----------
[NFC][lldb][Windows] Clean up TargetThreadWindows (#202722)
- Drop dead `//#include "ForwardDecl.h"` and stale `class HostThread;`
forward declaration.
- Remove redundant `m_thread_reg_ctx_sp()` default-init in the
constructor initializer list.
Commit: e518b414496154af21569ceadd14bd473d22110b
https://github.com/llvm/llvm-project/commit/e518b414496154af21569ceadd14bd473d22110b
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Log Message:
-----------
[InstCombine][NFC] Don't try non-bundle folds on assumes with bundles (#202914)
Commit: 53ae585a95aeff1c86ebd1943bdb9206dfa0837f
https://github.com/llvm/llvm-project/commit/53ae585a95aeff1c86ebd1943bdb9206dfa0837f
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
A llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16-fake16.txt
R llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
Log Message:
-----------
[AMDGPU][NFC] Templatise and roundtrip gfx11_asm_vop3_dpp16.s (#202721)
I tried to make sure this covers all important cases from asm/disasm
tests here upstream and the true16 branch downstream.
This will resolve ~4k lines of differences vs the true16 branch.
Commit: e63f9bec814bde36f0aa13cd01c1a9abb8527c83
https://github.com/llvm/llvm-project/commit/e63f9bec814bde36f0aa13cd01c1a9abb8527c83
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaType.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p3-generic-lambda-1y.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p5.cpp
M clang/test/CXX/dcl/dcl.fct/p17.cpp
M clang/test/CXX/drs/cwg6xx.cpp
M clang/test/Parser/cxx1z-decomposition.cpp
M clang/test/SemaCXX/crash-GH173943.cpp
M clang/test/SemaCXX/deduced-return-type-cxx14.cpp
Log Message:
-----------
[Clang] Accept auto parameters pre-C++20 as an extension (#200670)
GCC already accepts auto parameters as an extenion.
Commit: 80460f175cc1db1faa7bfe851139817b8a51e91d
https://github.com/llvm/llvm-project/commit/80460f175cc1db1faa7bfe851139817b8a51e91d
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M mlir/lib/Dialect/SPIRV/IR/CastOps.cpp
M mlir/test/Dialect/SPIRV/IR/cast-ops.mlir
Log Message:
-----------
[mlir][SPIR-V] Fix ConvertUToPtr verifier error message (NFC) (#202899)
Commit: 7b1dc59f476e86a616cd3343a066fdad29d7341d
https://github.com/llvm/llvm-project/commit/7b1dc59f476e86a616cd3343a066fdad29d7341d
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve2-histcnt-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/narrow-to-single-scalar-widen-gep-scalable.ll
M llvm/test/Transforms/LoopVectorize/widen-gep-all-indices-invariant.ll
M llvm/test/Transforms/PhaseOrdering/ARM/arm_var_q31.ll
Log Message:
-----------
[VPlan] Simplify WidenGEP::execute (#193543)
WidenGEP::execute is currently dependent on whether or not a given
operand is defined outside loop regions, but it loop-invariant operands
are not guaranteed to be hoisted outside the loop, and neither are
single-scalar operands guaranteed to be maximally narrowed to
single-scalars. Use the vputils::isSingleScalar helper to analyze the
single-scalar status of each operand and the result instead, simplifying
the execute, while also leading to some improvements.
Commit: 3e470fc2f368d2a11146ef014daac09f360bc35d
https://github.com/llvm/llvm-project/commit/3e470fc2f368d2a11146ef014daac09f360bc35d
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
A clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN div_fixup builtins (#197468)
Adds codegen for the following AMDGCN division fixup builtins:
- __builtin_amdgcn_div_fixup (double)
- __builtin_amdgcn_div_fixupf (float)
- __builtin_amdgcn_div_fixuph (half)
These are lowered to the corresponding `llvm.amdgcn.div.fixup` intrinsic.
Commit: 49affe5954453474ba9f1b2b7aec82c28d03e54d
https://github.com/llvm/llvm-project/commit/49affe5954453474ba9f1b2b7aec82c28d03e54d
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
Log Message:
-----------
Document the warn_unused attribute (#201881)
Basically, this attribute is useful for getting -Wunused-variable
diagnostics from class types with a nontrivial constructor or
destructor.
Commit: 14a9660dc371c1ed7778890a6c3eb22352cc6620
https://github.com/llvm/llvm-project/commit/14a9660dc371c1ed7778890a6c3eb22352cc6620
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/pr53842.ll
Log Message:
-----------
[X86] combineConcatVectorOps - add 512-bit PCMPEQ/PCMPGT handling (#202928)
If we can freely concatenate both operands, then its worth replacing
with a VPCMP+VPMOVM2 pair
Managed to notice this while triaging #198162 - and the AVX512DQ SGT
test shows another vpmovq2m+vpmovm2q pair codegen issue :(
Commit: c838b5d66bc1db15de84a8e4692905cbda293672
https://github.com/llvm/llvm-project/commit/c838b5d66bc1db15de84a8e4692905cbda293672
Author: lntue <lntue at google.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
A libc/shared/math/check/exp.h
A libc/shared/math_check_exceptions.h
A libc/src/__support/math/check/exp_exceptions.h
M libc/test/shared/CMakeLists.txt
A libc/test/shared/shared_math_check_exp_test.cpp
Log Message:
-----------
[libc][math] Add shared functions to check exceptions for exp* functions. (#202503)
To be used inside LLVM and other projects.
Commit: 10060098acf4e02677328128b8bbae6142ddc2f5
https://github.com/llvm/llvm-project/commit/10060098acf4e02677328128b8bbae6142ddc2f5
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
M llvm/test/Transforms/LoopVectorize/RISCV/gather-scatter-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-gather-scatter.ll
M llvm/test/Transforms/LoopVectorize/cast-costs.ll
M llvm/test/Transforms/LoopVectorize/vscale-cost.ll
Log Message:
-----------
Revert "[LV] Add initial costs for VPInstructionWithType::computeCost (#198291)" (#202933)
This reverts commit 690b0b0c63125aaf6b517df9d528789bb8c9c08a.
Fixes buildbot failure:
https://lab.llvm.org/buildbot/#/builders/132/builds/6656
Commit: 6ec2261fa29de72fe9520192a3e8b2f5f2082b67
https://github.com/llvm/llvm-project/commit/6ec2261fa29de72fe9520192a3e8b2f5f2082b67
Author: Peter Smith <peter.smith at arm.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M lld/ELF/Relocations.cpp
Log Message:
-----------
[ARM][LLD] Fix buildbot failure due to ununsed variable [NFC] (#202925)
The variable was used in an assert, have altered the code to use in an a
non-assert context.
Commit: e00f23b3db8b5f8387c78d58144c50915fe2bbf2
https://github.com/llvm/llvm-project/commit/e00f23b3db8b5f8387c78d58144c50915fe2bbf2
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M llvm/lib/IR/Verifier.cpp
M llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll
Log Message:
-----------
[AMDGPU] Reject invalid flags immarg for amdgcn.cs.chain (#202708)
The flags operand must be 0 or 1
Commit: ebc076e8d856c8e834d94f0553bacef8ecb48aa7
https://github.com/llvm/llvm-project/commit/ebc076e8d856c8e834d94f0553bacef8ecb48aa7
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-10 (Wed, 10 Jun 2026)
Changed paths:
M .ci/compute_projects.py
M .github/workflows/bazel-checks.yml
M .github/workflows/build-ci-container-tooling.yml
M .github/workflows/containers/github-action-ci-tooling/Dockerfile
M .github/workflows/containers/github-action-ci-windows/Dockerfile
M .github/workflows/containers/github-action-ci/Dockerfile
R .github/workflows/issue-subscriber.yml
M .github/workflows/libc-shared-tests.yml
R .github/workflows/pr-subscriber.yml
M .github/workflows/release-binaries.yml
M .github/workflows/release-documentation.yml
M .github/workflows/release-doxygen.yml
M .github/workflows/release-tasks.yml
A .github/workflows/subscriber.yml
M bolt/docs/CMakeLists.txt
M bolt/docs/doxygen.cfg.in
M clang-tools-extra/clang-tidy/bugprone/UseAfterMoveCheck.cpp
M clang-tools-extra/clang-tidy/modernize/MacroToEnumCheck.cpp
M clang-tools-extra/clang-tidy/readability/CMakeLists.txt
M clang-tools-extra/clang-tidy/readability/DeleteNullPointerCheck.cpp
M clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp
A clang-tools-extra/clang-tidy/readability/RedundantNestedIfCheck.cpp
A clang-tools-extra/clang-tidy/readability/RedundantNestedIfCheck.h
M clang-tools-extra/clangd/CompileCommands.cpp
M clang-tools-extra/clangd/index/SymbolID.h
M clang-tools-extra/clangd/unittests/CompileCommandsTests.cpp
M clang-tools-extra/docs/CMakeLists.txt
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/redundant-nested-if.rst
M clang-tools-extra/docs/doxygen.cfg.in
M clang-tools-extra/test/.gitattributes
M clang-tools-extra/test/clang-tidy/checkers/altera/id-dependent-backward-branch.cpp
M clang-tools-extra/test/clang-tidy/checkers/bugprone/use-after-move.cpp
A clang-tools-extra/test/clang-tidy/checkers/modernize/Inputs/macro-to-enum/crlf.cpp
A clang-tools-extra/test/clang-tidy/checkers/modernize/Inputs/macro-to-enum/crlf.cpp.expected
A clang-tools-extra/test/clang-tidy/checkers/modernize/macro-to-enum-crlf.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/Inputs/redundant-nested-if/common.h
M clang-tools-extra/test/clang-tidy/checkers/readability/delete-null-pointer.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-nested-if-allow-bool-conversion.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-nested-if-cxx17-allow-bool-conversion.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-nested-if-cxx17.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-nested-if-cxx20.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-nested-if-cxx23.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-nested-if-cxx26.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-nested-if-notes.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/redundant-nested-if.cpp
M clang/docs/CMakeLists.txt
M clang/docs/ClangSYCLLinker.rst
M clang/docs/LanguageExtensions.rst
M clang/docs/Multilib.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/SafeStack.rst
M clang/docs/doxygen.cfg.in
M clang/include/clang/AST/Expr.h
M clang/include/clang/AST/FormatString.h
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h
M clang/include/clang/Analysis/CallGraph.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/CodeGenOptions.h
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/OpenMPKinds.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Driver/OffloadBundler.h
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Options/Options.td
M clang/include/clang/Parse/Parser.h
M clang/include/clang/ScalableStaticAnalysisFramework/Core/Model/EntityLinkage.h
M clang/include/clang/Sema/HLSLExternalSemaSource.h
M clang/include/clang/Sema/SemaAMDGPU.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Context.h
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/InterpFrame.h
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/MemberPointer.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ByteCode/State.cpp
M clang/lib/AST/ByteCode/State.h
M clang/lib/AST/Expr.cpp
M clang/lib/AST/ExprClassification.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/FormatString.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/AST/OpenMPClause.cpp
M clang/lib/AST/PrintfFormatString.cpp
M clang/lib/AST/ScanfFormatString.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/CodeGen/CGCoroutine.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.h
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/lib/Driver/ToolChains/Arch/RISCV.h
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
M clang/lib/Driver/ToolChains/HIPSPV.cpp
M clang/lib/Driver/ToolChains/HIPSPV.h
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/lib/Driver/ToolChains/PS4CPU.h
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/__clang_hip_runtime_wrapper.h
A clang/lib/Headers/riscv_packed_simd.h
M clang/lib/Lex/Lexer.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphExtractor.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/EntityPointerLevel/EntityPointerLevel.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowExtractor.cpp
M clang/lib/ScalableStaticAnalysisFramework/Core/TUSummary/TUSummaryExtractor.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaRISCV.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/StaticAnalyzer/Checkers/BlockInCriticalSectionChecker.cpp
M clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/codegen.c
M clang/test/AST/ByteCode/codegen.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ByteCode/intap.cpp
M clang/test/AST/ByteCode/unions.cpp
A clang/test/AST/dependent-assignment-classification.cpp
A clang/test/Analysis/Scalable/PointerFlow/external-inline-function-in-multi-tu.test
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/data-element-not-object.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/data-entry-missing-data.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/data-entry-missing-summary-name.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/data-not-array.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/duplicate-entity-id-in-data-map.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/duplicate-entity.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/duplicate-summary-name.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/entity-data-element-not-object.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/entity-data-missing-entity-id.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/entity-data-missing-entity-summary.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/entity-id-not-uint64.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/entity-name-missing-suffix.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/entity-name-missing-usr.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/id-table-element-not-object.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/id-table-entry-id-not-uint64.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/id-table-entry-missing-id.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/id-table-entry-missing-name.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/id-table-not-array.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/invalid-kind.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/invalid-syntax.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-duplicate-id.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-element-not-object.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-entry-id-not-uint64.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-entry-linkage-invalid-type.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-entry-linkage-missing-type.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-entry-missing-id.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-entry-missing-linkage.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-extra-id.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-missing-id.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/linkage-table-not-array.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/missing-data.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/missing-id-table.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/missing-kind.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/missing-linkage-table.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/missing-name.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/missing-tu-namespace.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/not-json-extension.txt
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/not-object.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/pairs-element-not-object.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/pairs-invalid-first-field.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/pairs-invalid-pairs-field-type.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/pairs-invalid-second-field.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/pairs-missing-first-field.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/pairs-missing-pairs-field.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/pairs-missing-second-field.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/read-entity-summary-no-format-info.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/rt-empty-data-entry.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/rt-empty.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/rt-link-unit.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/rt-linkage-external.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/rt-linkage-internal.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/rt-linkage-multiple.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/rt-linkage-none.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/Inputs/rt-two-summary-types.json
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/id-table.test
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/io.test
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/linkage.test
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/permissions.test
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/round-trip.test
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/summary-data.test
A clang/test/Analysis/Scalable/ssaf-format/TUSummary/top-level.test
M clang/test/Analysis/cstring-uninitread-notes.c
M clang/test/Analysis/placement-new.cpp
M clang/test/Analysis/std-c-library-functions-arg-constraints-tracking-notes.c
M clang/test/Analysis/std-c-library-functions-arg-constraints.c
M clang/test/Analysis/uninit-const.c
M clang/test/Analysis/uninit-vals.m
A clang/test/CIR/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p3-generic-lambda-1y.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p5.cpp
M clang/test/CXX/dcl/dcl.fct/p17.cpp
M clang/test/CXX/drs/cwg6xx.cpp
A clang/test/CXX/lex/lex.header/p2.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
M clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
A clang/test/CodeGen/RISCV/rvp-intrinsics.c
M clang/test/CodeGen/amdgpu-builtin-is-invocable.c
M clang/test/CodeGen/amdgpu-builtin-processor-is.c
A clang/test/CodeGen/attr-counted-by-issue200014.c
M clang/test/CodeGen/epilog-unwind.c
M clang/test/CodeGen/link-builtin-bitcode.c
A clang/test/CodeGen/prefetch-poison-arg.c
M clang/test/CodeGen/target-builtin-noerror.c
M clang/test/CodeGen/unique-internal-linkage-names.c
M clang/test/CodeGen/unique-internal-linkage-names.cpp
A clang/test/CodeGen/winx64-eh-unwind-egpr.c
M clang/test/CodeGen/zero-call-used-regs.c
A clang/test/CodeGenCXX/aarch64-mangle-sme-attrs-ms.cpp
A clang/test/CodeGenCXX/cl-pathmap.cpp
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
A clang/test/CodeGenCoroutines/coro-cwg2935.cpp
A clang/test/CodeGenHIP/offload-pgo-sections.hip
A clang/test/CodeGenHLSL/builtins/InterlockedAdd.hlsl
A clang/test/CodeGenOpenCL/builtins-amdgcn-global-load-store.cl
R clang/test/CodeGenSYCL/filescope_asm.c
A clang/test/CodeGenSYCL/filescope_asm.cpp
A clang/test/Driver/Inputs/multilib_msvc_tree/bin/.keep
A clang/test/Driver/Inputs/multilib_msvc_tree/include/x86_64-pc-windows-msvc/.keep
A clang/test/Driver/Inputs/multilib_msvc_tree/include/x86_64-pc-windows-msvc/debug/.keep
A clang/test/Driver/Inputs/multilib_msvc_tree/include/x86_64-pc-windows-msvc/noexcept/.keep
A clang/test/Driver/Inputs/multilib_msvc_tree/include/x86_64-pc-windows-msvc/release/.keep
M clang/test/Driver/amdgpu-openmp-sanitize-options.c
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/cl-options.c
A clang/test/Driver/cl-pathmap.c
A clang/test/Driver/driverkit26-boundary.c
M clang/test/Driver/fsanitize-realtime.c
M clang/test/Driver/hip-binding.hip
M clang/test/Driver/hip-device-compile.hip
M clang/test/Driver/hip-offload-compress-zlib.hip
M clang/test/Driver/hip-offload-compress-zstd.hip
M clang/test/Driver/hip-phases.hip
A clang/test/Driver/hip-profile-rocm-runtime.hip
M clang/test/Driver/hip-rdc-device-only.hip
M clang/test/Driver/hip-sanitize-options.hip
M clang/test/Driver/hip-save-temps.hip
M clang/test/Driver/hip-spirv-backend-bindings.c
M clang/test/Driver/hip-spirv-backend-opt.c
M clang/test/Driver/hip-spirv-backend-phases.c
M clang/test/Driver/hip-spirv-linker-crash.c
M clang/test/Driver/hip-target-id.hip
M clang/test/Driver/hip-toolchain-device-only.hip
M clang/test/Driver/hip-toolchain-no-rdc.hip
M clang/test/Driver/hip-toolchain-rdc-flto-partitions.hip
M clang/test/Driver/hip-toolchain-rdc-separate.hip
M clang/test/Driver/hip-toolchain-rdc-static-lib.hip
M clang/test/Driver/hip-toolchain-rdc.hip
M clang/test/Driver/hip-unbundle-preproc.hipi
M clang/test/Driver/hipspv-toolchain-rdc-separate.hip
M clang/test/Driver/hipspv-toolchain-rdc.hip
M clang/test/Driver/hipspv-toolchain.hip
A clang/test/Driver/msvc-multilib.yaml
M clang/test/Driver/offload-target.c
M clang/test/Driver/openmp-offload-gpu.c
M clang/test/Driver/print-multi-selection-flags.c
M clang/test/Driver/ps4-ps5-toolchain.c
A clang/test/Driver/riscv-mtune-tune-features.c
A clang/test/Driver/simple-darwin.c
M clang/test/Driver/spirv-amd-toolchain.c
M clang/test/Driver/spirv-openmp-toolchain.c
M clang/test/Driver/sycl.cpp
A clang/test/Driver/winx64-eh-unwind.c
M clang/test/Driver/x86-march.c
A clang/test/Frontend/sycl-c-input-error.cpp
M clang/test/Frontend/x86-target-cpu.c
M clang/test/Headers/__cpuidex_conflict.c
A clang/test/Headers/hip-constexpr-cmath.hip
M clang/test/Misc/target-invalid-cpu-note/x86.c
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper-hip-no-rdc.c
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper.c
M clang/test/OffloadTools/clang-sycl-linker/basic.ll
M clang/test/OffloadTools/clang-sycl-linker/link.ll
M clang/test/OffloadTools/clang-sycl-linker/split-mode.ll
M clang/test/OffloadTools/clang-sycl-linker/triple.ll
A clang/test/OpenMP/critical-dso-local.cpp
M clang/test/OpenMP/critical_codegen.cpp
M clang/test/OpenMP/critical_codegen_attr.cpp
A clang/test/OpenMP/interop_prefer_type_brace_ast_print.cpp
A clang/test/OpenMP/interop_prefer_type_brace_messages.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen.cpp
M clang/test/Parser/cxx1z-decomposition.cpp
A clang/test/Preprocessor/cl-pathmap.c
M clang/test/Preprocessor/predefined-arch-macros.c
M clang/test/Sema/Inputs/lifetime-analysis.h
A clang/test/Sema/format-strings-decimal.c
A clang/test/Sema/safestack-deprecated-builtins.c
M clang/test/Sema/warn-alloc-size.c
M clang/test/Sema/warn-lifetime-safety.cpp
M clang/test/SemaCXX/attr-section.cpp
M clang/test/SemaCXX/crash-GH173943.cpp
M clang/test/SemaCXX/deduced-return-type-cxx14.cpp
A clang/test/SemaHIP/amdgpu-av-load-store.hip
A clang/test/SemaHLSL/BuiltIns/InterlockedAdd-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/asuint-errors.hlsl
M clang/test/SemaHLSL/BuiltIns/splitdouble-errors.hlsl
M clang/test/SemaHLSL/parameter_modifiers.hlsl
A clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-error.cl
A clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-target-error.cl
M clang/test/SemaSPIRV/BuiltIns/generic_cast_to_ptr_explicit.c
M clang/test/SemaSPIRV/BuiltIns/ids_and_ranges.c
M clang/test/SemaSPIRV/BuiltIns/subgroup-errors.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-nvlink-wrapper/CMakeLists.txt
M clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp
M clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp
M clang/tools/clang-sycl-linker/CMakeLists.txt
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
M clang/tools/clang-sycl-linker/SYCLLinkOpts.td
M clang/tools/libclang/CIndex.cpp
M clang/unittests/Frontend/CompilerInvocationTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphExtractorTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/PointerFlow/PointerFlowTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Analyses/UnsafeBufferUsage/UnsafeBufferUsageTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/Serialization/JSONFormatTest/TUSummaryTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/TUSummaryBuilderTest.cpp
M clang/utils/TableGen/CIRLoweringEmitter.cpp
M cmake/Modules/HandleDoxygen.cmake
M compiler-rt/CMakeLists.txt
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
M compiler-rt/cmake/base-config-ix.cmake
M compiler-rt/cmake/caches/AMDGPU.cmake
M compiler-rt/cmake/caches/NVPTX.cmake
M compiler-rt/cmake/caches/SPIRV64.cmake
M compiler-rt/cmake/config-ix.cmake
M compiler-rt/include/CMakeLists.txt
A compiler-rt/include/sanitizer/safestack_interface.h
M compiler-rt/lib/asan/CMakeLists.txt
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/arm/floatdidf.S
A compiler-rt/lib/builtins/arm/floatdisf.S
A compiler-rt/lib/builtins/arm/floatsidf.S
A compiler-rt/lib/builtins/arm/floatsisf.S
A compiler-rt/lib/builtins/arm/floatundidf.S
A compiler-rt/lib/builtins/arm/floatunsidf.S
A compiler-rt/lib/builtins/arm/floatunsisf.S
M compiler-rt/lib/builtins/cpu_model/x86.c
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/profile/CMakeLists.txt
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/safestack/CMakeLists.txt
M compiler-rt/lib/safestack/safestack.cpp
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/tsd_shared.h
M compiler-rt/test/builtins/CMakeLists.txt
A compiler-rt/test/builtins/Unit/floatdidfnew_test.c
A compiler-rt/test/builtins/Unit/floatdisfnew_test.c
A compiler-rt/test/builtins/Unit/floatsidfnew_test.c
A compiler-rt/test/builtins/Unit/floatsisfnew_test.c
A compiler-rt/test/builtins/Unit/floatundidfnew_test.c
A compiler-rt/test/builtins/Unit/floatundisfnew_test.c
A compiler-rt/test/builtins/Unit/floatunsidfnew_test.c
A compiler-rt/test/builtins/Unit/floatunsisfnew_test.c
M compiler-rt/test/builtins/Unit/lit.cfg.py
M compiler-rt/test/rtsan/lit.cfg.py
M compiler-rt/test/safestack/sigaltstack.c
M compiler-rt/test/ubsan_minimal/CMakeLists.txt
A cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M flang-rt/lib/runtime/edit-input.cpp
M flang-rt/unittests/Runtime/InputExtensions.cpp
M flang/docs/CMakeLists.txt
M flang/docs/Extensions.md
M flang/docs/doxygen.cfg.in
M flang/include/flang/Lower/OpenACC.h
M flang/include/flang/Optimizer/Analysis/AliasAnalysis.h
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Optimizer/HLFIR/Passes.td
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/openmp-utils.h
M flang/include/flang/Semantics/symbol.h
M flang/include/flang/Semantics/tools.h
M flang/include/flang/Semantics/type.h
M flang/lib/Evaluate/type.cpp
M flang/lib/Lower/ConvertType.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/CodeGen/TypeConverter.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
M flang/lib/Optimizer/HLFIR/Transforms/CMakeLists.txt
A flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRCopy.cpp
R flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRCopyIn.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/FIRToMemRef.cpp
M flang/lib/Parser/Fortran-parsers.cpp
M flang/lib/Parser/program-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/openmp-utils.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Semantics/symbol.cpp
M flang/lib/Semantics/tools.cpp
M flang/lib/Semantics/type.cpp
M flang/test/Analysis/AliasAnalysis/alias-analysis-regionbranch.mlir
A flang/test/Analysis/AliasAnalysis/alias-analysis-scoped-origins.fir
M flang/test/Analysis/AliasAnalysis/ptr-component.fir
M flang/test/Driver/omp-driver-offload.f90
M flang/test/Fir/convert-to-llvm-invalid.fir
A flang/test/Fir/shape-extents.mlir
A flang/test/Fir/shape-to-llvm.mlir
M flang/test/HLFIR/assign-bufferize.fir
M flang/test/HLFIR/associate-codegen.fir
M flang/test/HLFIR/bufferize01.fir
M flang/test/HLFIR/extents-of-shape-of.f90
R flang/test/HLFIR/inline-hlfir-copy-in.fir
A flang/test/HLFIR/inline-hlfir-copy.fir
M flang/test/HLFIR/mul_transpose.f90
M flang/test/HLFIR/shapeof-lowering.fir
A flang/test/Lower/OpenACC/acc-declare-use-associated-allocatable.f90
M flang/test/Lower/OpenACC/acc-declare.f90
A flang/test/Parser/enumeration-type.f90
M flang/test/Semantics/OpenMP/allocate03.f90
M flang/test/Semantics/OpenMP/allocators02.f90
M flang/test/Semantics/OpenMP/assumed-size-array-dsa.f90
M flang/test/Semantics/OpenMP/copyprivate04.f90
M flang/test/Semantics/OpenMP/copyprivate05.f90
M flang/test/Semantics/OpenMP/cray-pointer-usage.f90
M flang/test/Semantics/OpenMP/declare-target01.f90
M flang/test/Semantics/OpenMP/detach01.f90
M flang/test/Semantics/OpenMP/firstprivate02.f90
M flang/test/Semantics/OpenMP/from-clause-v45.f90
M flang/test/Semantics/OpenMP/from-clause-v51.f90
M flang/test/Semantics/OpenMP/in-reduction.f90
M flang/test/Semantics/OpenMP/lastprivate01.f90
M flang/test/Semantics/OpenMP/lastprivate03.f90
M flang/test/Semantics/OpenMP/linear-clause-array-section.f90
M flang/test/Semantics/OpenMP/name-conflict.f90
M flang/test/Semantics/OpenMP/named-constants.f90
M flang/test/Semantics/OpenMP/parallel-private01.f90
M flang/test/Semantics/OpenMP/parallel-private02.f90
M flang/test/Semantics/OpenMP/parallel-private03.f90
M flang/test/Semantics/OpenMP/parallel-private04.f90
M flang/test/Semantics/OpenMP/parallel-sections01.f90
M flang/test/Semantics/OpenMP/parallel-shared01.f90
M flang/test/Semantics/OpenMP/parallel-shared02.f90
M flang/test/Semantics/OpenMP/parallel-shared03.f90
M flang/test/Semantics/OpenMP/parallel-shared04.f90
M flang/test/Semantics/OpenMP/reduction-assumed.f90
M flang/test/Semantics/OpenMP/reduction04.f90
M flang/test/Semantics/OpenMP/reduction16.f90
M flang/test/Semantics/OpenMP/resolve01.f90
A flang/test/Semantics/OpenMP/target-enter-data-temp-descriptor-omp61.f90
A flang/test/Semantics/OpenMP/target-enter-data-temp-descriptor.f90
M flang/test/Semantics/OpenMP/task-reduction.f90
M flang/test/Semantics/OpenMP/threadprivate01.f90
M flang/test/Semantics/OpenMP/to-clause-v45.f90
M flang/test/Semantics/OpenMP/to-clause-v51.f90
A flang/test/Transforms/FIRToMemRef/forwarded-shape.mlir
M libc/fuzzing/__support/freelist_heap_fuzz.cpp
M libc/include/math.yaml
A libc/shared/math/check/exp.h
A libc/shared/math_check_exceptions.h
M libc/src/__support/block.h
M libc/src/__support/freelist.cpp
M libc/src/__support/freelist.h
M libc/src/__support/freelist_heap.h
M libc/src/__support/freestore.h
M libc/src/__support/freetrie.h
A libc/src/__support/math/check/exp_exceptions.h
M libc/src/__support/math/cos.h
M libc/src/__support/math/sin.h
M libc/test/shared/CMakeLists.txt
A libc/test/shared/shared_math_check_exp_test.cpp
M libc/test/src/__support/block_test.cpp
M libc/test/src/__support/freelist_heap_test.cpp
M libc/test/src/__support/freelist_test.cpp
M libc/test/src/__support/freestore_test.cpp
M libc/test/src/__support/freetrie_test.cpp
M libcxx/docs/ReleaseNotes/23.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__bit_reference
M libcxx/include/__configuration/availability.h
M libcxx/include/__exception/nested_exception.h
M libcxx/include/__format/range_formatter.h
M libcxx/include/__hash_table
M libcxx/include/__iterator/wrap_iter.h
R libcxx/include/__type_traits/dependent_type.h
M libcxx/include/__type_traits/rank.h
M libcxx/include/__utility/is_pointer_in_range.h
M libcxx/include/module.modulemap.in
M libcxx/include/variant
M libcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/i686-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/powerpc-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/powerpc64-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-apple-darwin.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-linux-android23.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-freebsd.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.nonew.abilist
M libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.noexceptions.nonew.abilist
M libcxx/src/variant.cpp
A libcxx/test/libcxx/containers/sequences/vector.bool/nodiscard.iterator.verify.cpp
A libcxx/test/libcxx/containers/sequences/vector/nodiscard.iterator.verify.cpp
A libcxx/test/libcxx/utilities/variant/variant.bad_variant_access/good_what_message.pass.cpp
A libcxx/test/std/containers/unord/unord.map/unord.map.cnstr/exceptions.pass.cpp
M libcxx/test/std/containers/views/views.span/enable_borrowed_range.compile.pass.cpp
M libcxx/test/std/containers/views/views.span/range_concept_conformance.compile.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/array.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/assign.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/copy.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/deduct.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/default.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/initializer_list.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/iterator_len.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/iterator_len.verify.cpp
M libcxx/test/std/containers/views/views.span/span.cons/iterator_sentinel.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/iterator_sentinel.verify.cpp
M libcxx/test/std/containers/views/views.span/span.cons/range.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/span.dtor.compile.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/span.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/span.verify.cpp
M libcxx/test/std/containers/views/views.span/span.cons/stdarray.pass.cpp
M libcxx/test/std/containers/views/views.span/span.elem/at.pass.cpp
M libcxx/test/std/containers/views/views.span/span.elem/back.pass.cpp
M libcxx/test/std/containers/views/views.span/span.elem/data.pass.cpp
M libcxx/test/std/containers/views/views.span/span.elem/front.pass.cpp
M libcxx/test/std/containers/views/views.span/span.elem/op_idx.pass.cpp
M libcxx/test/std/containers/views/views.span/span.iterators/begin.pass.cpp
M libcxx/test/std/containers/views/views.span/span.iterators/end.pass.cpp
M libcxx/test/std/containers/views/views.span/span.iterators/iterator.pass.cpp
M libcxx/test/std/containers/views/views.span/span.iterators/iterator_concept_conformance.compile.pass.cpp
M libcxx/test/std/containers/views/views.span/span.iterators/rbegin.pass.cpp
M libcxx/test/std/containers/views/views.span/span.iterators/rend.pass.cpp
M libcxx/test/std/containers/views/views.span/span.objectrep/as_bytes.pass.cpp
M libcxx/test/std/containers/views/views.span/span.objectrep/as_writable_bytes.pass.cpp
M libcxx/test/std/containers/views/views.span/span.obs/empty.nodiscard.verify.cpp
M libcxx/test/std/containers/views/views.span/span.obs/empty.pass.cpp
M libcxx/test/std/containers/views/views.span/span.obs/size.pass.cpp
M libcxx/test/std/containers/views/views.span/span.obs/size_bytes.pass.cpp
M libcxx/test/std/containers/views/views.span/trivially_copyable.compile.pass.cpp
M libcxx/test/std/containers/views/views.span/types.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/offset_range.pass.cpp
M libcxx/test/std/strings/basic.string/string.capacity/over_max_size.pass.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtset/format.functions.tests.h
M libcxx/test/std/utilities/format/format.range/format.range.formatter/format.functions.tests.h
M libcxx/utils/ci/docker/docker-compose.yml
M libcxx/utils/libcxx/test/features/availability.py
M libcxxabi/test/test_demangle.pass.cpp
M libsycl/CMakeLists.txt
A libsycl/cmake/Modules/AddUnitTest.cmake
M libsycl/docs/index.rst
M libsycl/src/CMakeLists.txt
M libsycl/src/detail/device_kernel_info.hpp
M libsycl/src/detail/program_manager.cpp
M libsycl/src/detail/program_manager.hpp
A libsycl/unittests/CMakeLists.txt
A libsycl/unittests/common/device_images.hpp
A libsycl/unittests/mock/CMakeLists.txt
A libsycl/unittests/mock/helpers.cpp
A libsycl/unittests/mock/helpers.hpp
A libsycl/unittests/mock/mock.cpp
A libsycl/unittests/platform/CMakeLists.txt
A libsycl/unittests/platform/get_platforms.cpp
A libsycl/unittests/program_manager/CMakeLists.txt
A libsycl/unittests/program_manager/register_and_unregister.cpp
A libsycl/unittests/queue/CMakeLists.txt
A libsycl/unittests/queue/queue.cpp
M lld/ELF/Relocations.cpp
M lld/MachO/ConcatOutputSection.cpp
M lld/MachO/ConcatOutputSection.h
M lld/MachO/Driver.cpp
M lld/MachO/InputFiles.cpp
M lld/docs/ReleaseNotes.rst
A lld/test/ELF/aarch64-thunk-bti-overlay-reuse.s
A lld/test/ELF/arm-thunk-overlay-reuse.s
A lld/test/MachO/arm64-thunk-stubs-multi-text.s
A lld/test/MachO/arm64-thunk-stubs.s
M lld/test/MachO/arm64-thunks.s
A lld/test/MachO/compact-unwind-local-label.s
R lld/test/MachO/lc-linker-option-order.ll
A lld/test/MachO/lc-linker-option-postprocess.ll
A lld/test/MachO/lc-linker-option-sort.ll
M lldb/CMakeLists.txt
M lldb/docs/CMakeLists.txt
M lldb/docs/doxygen.cfg.in
M lldb/docs/resources/caveats.md
M lldb/docs/resources/lldbgdbremote.md
M lldb/docs/resources/lldbplatformpackets.md
M lldb/docs/resources/overview.md
M lldb/include/lldb/API/SBModule.h
M lldb/include/lldb/API/SBModuleSpec.h
M lldb/include/lldb/Core/Module.h
M lldb/include/lldb/Host/ProcessLaunchInfo.h
M lldb/include/lldb/Host/windows/PseudoConsole.h
M lldb/include/lldb/Symbol/SymbolFile.h
M lldb/include/lldb/Symbol/SymbolFileOnDemand.h
M lldb/include/lldb/Utility/StringExtractorGDBRemote.h
M lldb/packages/Python/lldbsuite/test/decorators.py
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/source/API/SBModule.cpp
M lldb/source/API/SBModuleSpec.cpp
M lldb/source/Core/Module.cpp
M lldb/source/Expression/DWARFExpression.cpp
M lldb/source/Host/common/ProcessLaunchInfo.cpp
M lldb/source/Host/windows/PseudoConsole.cpp
M lldb/source/Plugins/Language/CPlusPlus/CxxStringTypes.cpp
M lldb/source/Plugins/Language/CPlusPlus/GenericBitset.cpp
M lldb/source/Plugins/Language/CPlusPlus/GenericOptional.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxMap.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxUnorderedMap.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibStdcpp.cpp
M lldb/source/Plugins/Language/ObjC/CF.cpp
M lldb/source/Plugins/Language/ObjC/Cocoa.cpp
M lldb/source/Plugins/Language/ObjC/NSSet.cpp
M lldb/source/Plugins/Language/ObjC/ObjCLanguage.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCClassDescriptorV2.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCClassDescriptorV2.h
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV1.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV1.h
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTrampolineHandler.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCTrampolineHandler.h
M lldb/source/Plugins/LanguageRuntime/ObjC/ObjCLanguageRuntime.h
M lldb/source/Plugins/ObjectFile/Mach-O/CMakeLists.txt
A lldb/source/Plugins/ObjectFile/Mach-O/MachOTrie.cpp
A lldb/source/Plugins/ObjectFile/Mach-O/MachOTrie.h
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Process/Windows/Common/DebuggerThread.cpp
M lldb/source/Plugins/Process/Windows/Common/DebuggerThread.h
M lldb/source/Plugins/Process/Windows/Common/NativeThreadWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/TargetThreadWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/TargetThreadWindows.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.h
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.h
M lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilderClang.cpp
M lldb/source/Utility/StringExtractorGDBRemote.cpp
M lldb/test/API/commands/platform/connect/TestPlatformConnect.py
M lldb/test/API/functionalities/breakpoint/breakpoint_command/TestBreakpointCommand.py
M lldb/test/API/functionalities/breakpoint/breakpoint_locations/TestBreakpointLocations.py
M lldb/test/API/functionalities/breakpoint/delayed_breakpoints/TestDelayedBreakpoint.py
M lldb/test/API/functionalities/scripted_frame_provider/circular_dependency/TestFrameProviderCircularDependency.py
M lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py
A lldb/test/API/python_api/sbmodule/SeperateDebugInfo/Makefile
A lldb/test/API/python_api/sbmodule/SeperateDebugInfo/TestSBModuleSeparateDebugInfo.py
A lldb/test/API/python_api/sbmodule/SeperateDebugInfo/bar.cpp
A lldb/test/API/python_api/sbmodule/SeperateDebugInfo/main.cpp
A lldb/test/Shell/SymbolFile/DWARF/x86/DW_OP_impilict_value.s
A lldb/test/Shell/SymbolFile/NativePDB/invalid-type-refs.yaml
M lldb/tools/lldb-dap/JSONUtils.cpp
M lldb/unittests/Expression/DWARFExpressionTest.cpp
M lldb/unittests/ObjectFile/MachO/CMakeLists.txt
A lldb/unittests/ObjectFile/MachO/MachOTrieTest.cpp
M lldb/unittests/ObjectFile/MachO/TestObjectFileMachO.cpp
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CMakeLists.txt
M llvm/docs/ProgrammersManual.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/doxygen.cfg.in
M llvm/include/llvm/ADT/Hashing.h
M llvm/include/llvm/ADT/ImmutableList.h
M llvm/include/llvm/ADT/StringMap.h
M llvm/include/llvm/Analysis/InstructionSimplify.h
M llvm/include/llvm/Analysis/Loads.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/CodeGen/MachineFrameInfo.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
R llvm/include/llvm/Frontend/Offloading/ArchiveLinker.h
M llvm/include/llvm/IR/BundleAttributes.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/Module.h
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/MC/MCRegisterInfo.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/MC/MCWin64EH.h
M llvm/include/llvm/MC/MCWinEH.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/include/llvm/SandboxIR/Use.h
M llvm/include/llvm/Support/CodeGen.h
M llvm/include/llvm/Target/Target.td
M llvm/include/llvm/TargetParser/Host.h
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/TargetParser/X86TargetParser.h
M llvm/include/llvm/Transforms/Utils/AssumeBundleBuilder.h
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/MemDerefPrinter.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/BreakFalseDeps.cpp
M llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
M llvm/lib/CodeGen/MachineFrameInfo.cpp
M llvm/lib/CodeGen/MachineOperand.cpp
M llvm/lib/CodeGen/PrologEpilogInserter.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/VirtRegMap.cpp
R llvm/lib/Frontend/Offloading/ArchiveLinker.cpp
M llvm/lib/Frontend/Offloading/CMakeLists.txt
M llvm/lib/IR/BundleAttributes.cpp
M llvm/lib/IR/Function.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Module.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MC/MCWin64EH.cpp
M llvm/lib/MC/WinCOFFObjectWriter.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/GlobPattern.cpp
M llvm/lib/Support/StringMap.cpp
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
M llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
M llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUBarrierLatency.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/ARC/ARCISelLowering.cpp
M llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
M llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp
M llvm/lib/Target/BPF/BPFSelectionDAGInfo.h
M llvm/lib/Target/BPF/BTFDebug.cpp
M llvm/lib/Target/BPF/BTFDebug.h
M llvm/lib/Target/CSKY/CSKYISelLowering.cpp
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/DirectX/DXILPrepare.cpp
M llvm/lib/Target/DirectX/DirectX.h
M llvm/lib/Target/DirectX/DirectXIRPasses/CMakeLists.txt
A llvm/lib/Target/DirectX/DirectXIRPasses/DXILAttributes.cpp
A llvm/lib/Target/DirectX/DirectXIRPasses/DXILAttributes.h
M llvm/lib/Target/DirectX/DirectXIRPasses/DXILDebugInfo.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp
M llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h
M llvm/lib/Target/Lanai/LanaiISelLowering.cpp
M llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp
M llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/M68k/M68kISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
M llvm/lib/Target/Mips/MipsSEISelLowering.h
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVBaseInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
A llvm/lib/Target/SPIRV/SPIRVAuxDataHandler.cpp
A llvm/lib/Target/SPIRV/SPIRVAuxDataHandler.h
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
M llvm/lib/Target/SPIRV/SPIRVTypeInst.cpp
M llvm/lib/Target/SPIRV/SPIRVTypeInst.h
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
M llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h
M llvm/lib/Target/WebAssembly/Utils/WebAssemblyTypeUtilities.cpp
M llvm/lib/Target/WebAssembly/Utils/WebAssemblyTypeUtilities.h
M llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.h
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/CMakeLists.txt
M llvm/lib/Target/X86/X86.h
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86FixupSetCC.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86MCInstLower.cpp
A llvm/lib/Target/X86/X86ScheduleC864GM4.td
A llvm/lib/Target/X86/X86ScheduleC864GM7.td
M llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
M llvm/lib/Target/X86/X86SelectionDAGInfo.h
M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86WinEHUnwindV2.cpp
A llvm/lib/Target/X86/X86WinEHUnwindV3.cpp
M llvm/lib/Target/XCore/XCoreISelLowering.cpp
M llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp
M llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
M llvm/lib/Transforms/IPO/StripSymbols.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
M llvm/lib/Transforms/Scalar/AlignmentFromAssumptions.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Utils/AssumeBundleBuilder.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/test/Analysis/CostModel/AArch64/sve-arith-fp.ll
M llvm/test/Analysis/CostModel/AArch64/sve-fixed-length.ll
M llvm/test/Analysis/CostModel/ARM/memcpy.ll
M llvm/test/Analysis/LoopAccessAnalysis/early-exit-runtime-checks.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll
M llvm/test/Analysis/ValueTracking/assume.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-and.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/GlobalISel/opt-overlapping-and-postlegalize.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combine-ptr-add-chain.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-hoist-same-hands.mir
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/ldexp.ll
M llvm/test/CodeGen/AArch64/ldst-opt-umov-fpr-store.mir
A llvm/test/CodeGen/AArch64/misched-fusion-aes-post-ra.mir
M llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
A llvm/test/CodeGen/AArch64/powi-ldexp-promote-libcall-error.ll
A llvm/test/CodeGen/AArch64/predicate-as-counter-phi.ll
A llvm/test/CodeGen/AArch64/sve-multivector-fold-imms.ll
M llvm/test/CodeGen/AArch64/zero-call-used-regs.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-memintrinsic-asan.ll
M llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/ds_gws_align.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
A llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
A llvm/test/CodeGen/AMDGPU/si-fold-operands-bundle.mir
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
A llvm/test/CodeGen/BPF/BTF/func-nocall-all-dead.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-bool-arg.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-const-arg.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-const-no-shift.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-dead-arg.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-dead-type-mismatch.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-decl-tag.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-mixed-types.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-multi-dead.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-no-dead-arg.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-stack-arg-i64.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-stack-arg.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-stack-homed-arg.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-undef-dead-arg.ll
A llvm/test/CodeGen/BPF/BTF/func-nocall-void-return.ll
A llvm/test/CodeGen/DirectX/InterlockedAdd.ll
M llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
M llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
M llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
M llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll
M llvm/test/CodeGen/PowerPC/spe.ll
M llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll
M llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/atomic-cmpxchg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-add-sub.ll
M llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
M llvm/test/CodeGen/RISCV/GlobalISel/bitreverse-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/calls.ll
M llvm/test/CodeGen/RISCV/GlobalISel/combine-neg-abs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv32.ll
M llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/fastcc-float.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64p.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zba.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/shift.ll
M llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
M llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abds.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/abdu.ll
M llvm/test/CodeGen/RISCV/add-before-shl.ll
M llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
M llvm/test/CodeGen/RISCV/add_shl_constant.ll
M llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll
M llvm/test/CodeGen/RISCV/addcarry.ll
M llvm/test/CodeGen/RISCV/addimm-mulimm.ll
M llvm/test/CodeGen/RISCV/aext-to-sext.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/alu64.ll
M llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll
M llvm/test/CodeGen/RISCV/and-shl.ll
M llvm/test/CodeGen/RISCV/arith-with-overflow.ll
M llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
M llvm/test/CodeGen/RISCV/atomic-rmw.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/RISCV/avgceils.ll
M llvm/test/CodeGen/RISCV/avgceilu.ll
M llvm/test/CodeGen/RISCV/avgfloors.ll
M llvm/test/CodeGen/RISCV/avgflooru.ll
M llvm/test/CodeGen/RISCV/bf16-promote.ll
M llvm/test/CodeGen/RISCV/bfloat-arith.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bfloat-imm.ll
M llvm/test/CodeGen/RISCV/bfloat-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/bfloat-mem.ll
M llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll
M llvm/test/CodeGen/RISCV/bfloat.ll
M llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll
M llvm/test/CodeGen/RISCV/bitreverse-shift.ll
M llvm/test/CodeGen/RISCV/bittest.ll
M llvm/test/CodeGen/RISCV/branch-on-zero.ll
M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
M llvm/test/CodeGen/RISCV/bswap-known-bits.ll
M llvm/test/CodeGen/RISCV/bswap-shift.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-half.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll
M llvm/test/CodeGen/RISCV/calling-conv-p-ext-vector.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll
M llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
M llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll
M llvm/test/CodeGen/RISCV/calls-cf-branch.ll
M llvm/test/CodeGen/RISCV/calls.ll
M llvm/test/CodeGen/RISCV/clmul.ll
M llvm/test/CodeGen/RISCV/clmulh.ll
M llvm/test/CodeGen/RISCV/clmulr.ll
M llvm/test/CodeGen/RISCV/cmov-branch-opt.ll
M llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
M llvm/test/CodeGen/RISCV/combine-storetomstore.ll
M llvm/test/CodeGen/RISCV/compress.ll
M llvm/test/CodeGen/RISCV/condbinops.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/constpool-known-bits.ll
M llvm/test/CodeGen/RISCV/copyprop.ll
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/csr-first-use-cost.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/di-assignment-tracking-vector.ll
M llvm/test/CodeGen/RISCV/div-by-constant.ll
M llvm/test/CodeGen/RISCV/div-pow2.ll
M llvm/test/CodeGen/RISCV/div.ll
M llvm/test/CodeGen/RISCV/div_minsize.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/double-calling-conv.ll
M llvm/test/CodeGen/RISCV/double-convert-strict.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-mem.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-select-icmp.ll
M llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
M llvm/test/CodeGen/RISCV/double_reduct.ll
M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll
M llvm/test/CodeGen/RISCV/fastcc-bf16.ll
M llvm/test/CodeGen/RISCV/fastcc-float.ll
M llvm/test/CodeGen/RISCV/fastcc-half.ll
M llvm/test/CodeGen/RISCV/fastcc-int.ll
M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/fixed-csr.ll
M llvm/test/CodeGen/RISCV/float-arith.ll
M llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
M llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
M llvm/test/CodeGen/RISCV/float-convert-strict.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/float-round-conv.ll
M llvm/test/CodeGen/RISCV/float-select-icmp.ll
M llvm/test/CodeGen/RISCV/fma-combine.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
M llvm/test/CodeGen/RISCV/fold-binop-into-select.ll
M llvm/test/CodeGen/RISCV/fold-masked-merge.ll
M llvm/test/CodeGen/RISCV/fold-mem-offset-zilsd.ll
M llvm/test/CodeGen/RISCV/fold-mem-offset.ll
M llvm/test/CodeGen/RISCV/forced-atomics.ll
M llvm/test/CodeGen/RISCV/fp-fcanonicalize.ll
M llvm/test/CodeGen/RISCV/fp128.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/fpenv.ll
M llvm/test/CodeGen/RISCV/frame.ll
M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
M llvm/test/CodeGen/RISCV/frm-write-in-loop.ll
M llvm/test/CodeGen/RISCV/get-setcc-result-type.ll
M llvm/test/CodeGen/RISCV/ghccc-rv32.ll
M llvm/test/CodeGen/RISCV/ghccc-rv64.ll
M llvm/test/CodeGen/RISCV/ghccc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-nonzero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-zero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize.ll
M llvm/test/CodeGen/RISCV/global-merge.ll
M llvm/test/CodeGen/RISCV/half-arith-strict.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/half-fcmp.ll
M llvm/test/CodeGen/RISCV/half-imm.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-maximum-minimum.ll
M llvm/test/CodeGen/RISCV/half-mem.ll
M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/half-select-fcmp.ll
M llvm/test/CodeGen/RISCV/half-select-icmp.ll
M llvm/test/CodeGen/RISCV/half-zfa.ll
M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
M llvm/test/CodeGen/RISCV/i64-icmp.ll
M llvm/test/CodeGen/RISCV/iabs.ll
M llvm/test/CodeGen/RISCV/icmp-non-byte-sized.ll
M llvm/test/CodeGen/RISCV/idiv_large.ll
M llvm/test/CodeGen/RISCV/imm.ll
M llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-d-modifier-N.ll
M llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
M llvm/test/CodeGen/RISCV/inline-asm-f-modifier-N.ll
M llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
M llvm/test/CodeGen/RISCV/ipra.ll
M llvm/test/CodeGen/RISCV/jump-is-expensive.ll
M llvm/test/CodeGen/RISCV/jumptable-swguarded.ll
M llvm/test/CodeGen/RISCV/jumptable.ll
M llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll
M llvm/test/CodeGen/RISCV/large-stack.ll
M llvm/test/CodeGen/RISCV/legalize-fneg.ll
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/load-store-pair.ll
M llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
M llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
M llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll
M llvm/test/CodeGen/RISCV/lpad.ll
M llvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
M llvm/test/CodeGen/RISCV/machine-cse.ll
M llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll
M llvm/test/CodeGen/RISCV/machinelicm-constant-phys-reg.ll
M llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
M llvm/test/CodeGen/RISCV/mask-variable-shift.ll
M llvm/test/CodeGen/RISCV/mem.ll
M llvm/test/CodeGen/RISCV/mem64.ll
M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
M llvm/test/CodeGen/RISCV/memcmp.ll
M llvm/test/CodeGen/RISCV/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/memcpy.ll
M llvm/test/CodeGen/RISCV/memmove.ll
M llvm/test/CodeGen/RISCV/memset-inline.ll
M llvm/test/CodeGen/RISCV/memset-pattern.ll
M llvm/test/CodeGen/RISCV/min-max.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/mul-expand.ll
M llvm/test/CodeGen/RISCV/mul.ll
M llvm/test/CodeGen/RISCV/musttail-indirect-args.ll
M llvm/test/CodeGen/RISCV/narrow-shl-cst.ll
M llvm/test/CodeGen/RISCV/neg-abs.ll
M llvm/test/CodeGen/RISCV/nomerge.ll
M llvm/test/CodeGen/RISCV/nontemporal.ll
M llvm/test/CodeGen/RISCV/or-is-add.ll
M llvm/test/CodeGen/RISCV/orc-b-patterns.ll
M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
M llvm/test/CodeGen/RISCV/pr135206.ll
M llvm/test/CodeGen/RISCV/pr142004.ll
M llvm/test/CodeGen/RISCV/pr145360.ll
M llvm/test/CodeGen/RISCV/pr148084.ll
M llvm/test/CodeGen/RISCV/pr176001.ll
M llvm/test/CodeGen/RISCV/pr186969.ll
M llvm/test/CodeGen/RISCV/pr190868.ll
M llvm/test/CodeGen/RISCV/pr51206.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/pr58511.ll
M llvm/test/CodeGen/RISCV/pr63816.ll
M llvm/test/CodeGen/RISCV/pr64645.ll
M llvm/test/CodeGen/RISCV/pr65025.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/pr84653_pr85190.ll
M llvm/test/CodeGen/RISCV/pr90652.ll
M llvm/test/CodeGen/RISCV/pr94145.ll
M llvm/test/CodeGen/RISCV/pr95271.ll
M llvm/test/CodeGen/RISCV/pr95284.ll
A llvm/test/CodeGen/RISCV/prefer-sp-over-fp-with-v.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
M llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
M llvm/test/CodeGen/RISCV/reassoc-shl-addi-add.ll
M llvm/test/CodeGen/RISCV/redundant-copy-from-tail-duplicate.ll
M llvm/test/CodeGen/RISCV/rem.ll
M llvm/test/CodeGen/RISCV/remat.ll
M llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
M llvm/test/CodeGen/RISCV/rotl-rotr.ll
M llvm/test/CodeGen/RISCV/rv32-inline-asm-pairs.ll
M llvm/test/CodeGen/RISCV/rv32-move-merge.ll
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rv32xandesperf.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv32zbkb.ll
M llvm/test/CodeGen/RISCV/rv32zbs.ll
M llvm/test/CodeGen/RISCV/rv64-double-convert.ll
M llvm/test/CodeGen/RISCV/rv64-float-convert.ll
M llvm/test/CodeGen/RISCV/rv64-half-convert.ll
M llvm/test/CodeGen/RISCV/rv64-inline-asm-pairs.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
M llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
M llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
M llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
M llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
M llvm/test/CodeGen/RISCV/rv64xtheadba.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zba.ll
M llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbs.ll
M llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll
M llvm/test/CodeGen/RISCV/rvp-narrowing-shift-trunc.ll
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
M llvm/test/CodeGen/RISCV/rvp-unaligned-load-store.ll
M llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-vector-tuple.ll
M llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/buildvec-sext.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/combine-ctpop-to-vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
M llvm/test/CodeGen/RISCV/rvv/combine-vl-vw-macc.ll
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll
M llvm/test/CodeGen/RISCV/rvv/concat-vectors-constant-stride.ll
M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/expand-no-v.ll
M llvm/test/CodeGen/RISCV/rvv/expandload.ll
M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/fcanonicalize-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fcanonicalize-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpowi.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lround.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-scalarized.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-addsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-merge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmaccbf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverse-float.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-fp-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccsu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvdot4a8i.ll
M llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximumnum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimumnum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
M llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll
M llvm/test/CodeGen/RISCV/rvv/fp4-bitcast.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
M llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl.ll
M llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll
M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
M llvm/test/CodeGen/RISCV/rvv/incorrect-extract-subvector-combine.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/insertelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
M llvm/test/CodeGen/RISCV/rvv/intrinsic-vector-match.ll
M llvm/test/CodeGen/RISCV/rvv/known-never-zero.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/llround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/localvar.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/lround-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
M llvm/test/CodeGen/RISCV/rvv/masked-sdiv.ll
M llvm/test/CodeGen/RISCV/rvv/masked-srem.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
M llvm/test/CodeGen/RISCV/rvv/masked-udiv.ll
M llvm/test/CodeGen/RISCV/rvv/masked-urem.ll
M llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll
M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/mixed-float-bf16-arith.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/musttail-indirect-args.ll
M llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
M llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
M llvm/test/CodeGen/RISCV/rvv/partial-reduction-add.ll
M llvm/test/CodeGen/RISCV/rvv/pr104480.ll
M llvm/test/CodeGen/RISCV/rvv/pr125306.ll
M llvm/test/CodeGen/RISCV/rvv/pr165232.ll
M llvm/test/CodeGen/RISCV/rvv/pr52475.ll
M llvm/test/CodeGen/RISCV/rvv/pr61561.ll
M llvm/test/CodeGen/RISCV/rvv/pr83017.ll
M llvm/test/CodeGen/RISCV/rvv/pr88576.ll
M llvm/test/CodeGen/RISCV/rvv/pr88799.ll
M llvm/test/CodeGen/RISCV/rvv/pr90559.ll
M llvm/test/CodeGen/RISCV/rvv/pr95865.ll
M llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll
M llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.ll
M llvm/test/CodeGen/RISCV/rvv/remat.ll
M llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare-asm.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll
M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/smulo-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/splats-with-mixed-vl.ll
M llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/stack-probing-dynamic.ll
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
M llvm/test/CodeGen/RISCV/rvv/stlf.ll
M llvm/test/CodeGen/RISCV/rvv/stores-of-loads-merging.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
M llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
M llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
M llvm/test/CodeGen/RISCV/rvv/vaadd.ll
M llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vadc.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vadd.ll
M llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vand.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vandn.ll
M llvm/test/CodeGen/RISCV/rvv/vasub.ll
M llvm/test/CodeGen/RISCV/rvv/vasubu.ll
M llvm/test/CodeGen/RISCV/rvv/vclmul.ll
M llvm/test/CodeGen/RISCV/rvv/vclmulh.ll
M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu.ll
M llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll
M llvm/test/CodeGen/RISCV/rvv/vector-compress.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-reassociations.ll
M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcmps-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfirst-byte-compare-index.ll
M llvm/test/CodeGen/RISCV/rvv/vfirst.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd-w-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-bf-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-bf-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-alt.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwcvtbf16-f-f.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmaccbf16-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmul-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwmul.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub-w-bf.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-evl-tail-folding.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-live-out.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vle_vid-vfcvt.ll
M llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in.ll
M llvm/test/CodeGen/RISCV/rvv/vmadc.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmax.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu.ll
M llvm/test/CodeGen/RISCV/rvv/vmerge.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsif.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
M llvm/test/CodeGen/RISCV/rvv/vmsof.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmul.ll
M llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vmulh.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
M llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.s.x.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll
M llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vor.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-reverse-load.ll
M llvm/test/CodeGen/RISCV/rvv/vp-combine-store-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-float.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
M llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode-f16.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp-f16.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrem.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vremu.ll
M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
M llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vrsub.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vsbc.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-valid-elen-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vsext.ll
M llvm/test/CodeGen/RISCV/rvv/vsmul.ll
M llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssub.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu.ll
M llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsub.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-mask-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwmul.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulsu.ll
M llvm/test/CodeGen/RISCV/rvv/vwmulu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub-mask-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.ll
M llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.ll
M llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll
M llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vxor.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vzext.ll
M llvm/test/CodeGen/RISCV/rvv/xandesvbfhcvt-vfwcvt-s-bf16.ll
M llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-sdnode.ll
M llvm/test/CodeGen/RISCV/sadd_sat.ll
M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/scmp.ll
M llvm/test/CodeGen/RISCV/select-binop-identity.ll
M llvm/test/CodeGen/RISCV/select-cc.ll
M llvm/test/CodeGen/RISCV/select-cond.ll
M llvm/test/CodeGen/RISCV/select-const.ll
M llvm/test/CodeGen/RISCV/select-constant-xor.ll
M llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
M llvm/test/CodeGen/RISCV/select-pseudo-merge-with-stack-adj.ll
M llvm/test/CodeGen/RISCV/select-zbb.ll
M llvm/test/CodeGen/RISCV/select.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/shift-amount-mod.ll
M llvm/test/CodeGen/RISCV/shift-and.ll
M llvm/test/CodeGen/RISCV/shift-masked-shamt.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/shl-cttz.ll
M llvm/test/CodeGen/RISCV/shlimm-addimm.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt-load-atomic-acquire-seq_cst.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt-load.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt-mul.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt-qcloads.ll
M llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll
M llvm/test/CodeGen/RISCV/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/signed-truncation-check.ll
M llvm/test/CodeGen/RISCV/split-offsets.ll
M llvm/test/CodeGen/RISCV/split-store.ll
M llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll
M llvm/test/CodeGen/RISCV/split-urem-by-constant.ll
M llvm/test/CodeGen/RISCV/srem-lkk.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/ssub_sat.ll
M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
M llvm/test/CodeGen/RISCV/stack-clash-prologue.ll
M llvm/test/CodeGen/RISCV/stack-folding.ll
M llvm/test/CodeGen/RISCV/stack-probing-dynamic-nonentry.ll
M llvm/test/CodeGen/RISCV/stack-store-check.ll
M llvm/test/CodeGen/RISCV/switch-width.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/trunc-nsw-nuw.ll
M llvm/test/CodeGen/RISCV/typepromotion-overflow.ll
M llvm/test/CodeGen/RISCV/uadd_sat.ll
M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/ucmp.ll
M llvm/test/CodeGen/RISCV/udiv-const-optimization.ll
M llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
M llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll
M llvm/test/CodeGen/RISCV/urem-lkk.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/usub_sat_plus.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/varargs-with-fp-and-second-adj.ll
M llvm/test/CodeGen/RISCV/vscale-demanded-bits.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/RISCV/xcvmem-heuristic.ll
M llvm/test/CodeGen/RISCV/xcvmem.ll
M llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
M llvm/test/CodeGen/RISCV/xqcia.ll
M llvm/test/CodeGen/RISCV/xqciac.ll
M llvm/test/CodeGen/RISCV/xqcibi-redundant-copy-elim.ll
M llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
M llvm/test/CodeGen/RISCV/xqcibm-extract.ll
M llvm/test/CodeGen/RISCV/xqcibm-insbi.ll
M llvm/test/CodeGen/RISCV/xqcibm-insert.ll
M llvm/test/CodeGen/RISCV/xqcicm.ll
M llvm/test/CodeGen/RISCV/xqcics.ll
M llvm/test/CodeGen/RISCV/xqcilia.ll
M llvm/test/CodeGen/RISCV/xqcilsm-memset.ll
M llvm/test/CodeGen/RISCV/xqcisls.ll
M llvm/test/CodeGen/RISCV/xtheadmac.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
M llvm/test/CodeGen/RISCV/xtheadmempair.ll
M llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll
M llvm/test/CodeGen/RISCV/zcb-regalloc-hints.ll
M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll
M llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll
M llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll
M llvm/test/CodeGen/RISCV/zdinx-spill.ll
M llvm/test/CodeGen/RISCV/zibi.ll
M llvm/test/CodeGen/RISCV/zicond-fp-select-zfinx.ll
M llvm/test/CodeGen/RISCV/zicond-opts.ll
M llvm/test/CodeGen/RISCV/zilsd-spill.ll
M llvm/test/CodeGen/RISCV/zilsd.ll
A llvm/test/CodeGen/SPIRV/concat-vectors.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_relaxed_printf_string_address_space/multi-function-printf.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-all-function-attributes.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-all-function-metadata-debug.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-all-function-metadata.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-auxdata-requires-extension.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-auxdata.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-gv-attributes.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-gv-metadata.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_vector_bfloat16_amd.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/InterlockedAdd.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/InterlockedAdd_spv_i64.ll
A llvm/test/CodeGen/SPIRV/linkage/available-externally-function.ll
A llvm/test/CodeGen/SPIRV/linkage/available-externally-global.ll
M llvm/test/CodeGen/SPIRV/linkage/linkage-types.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/logical-memcpy.inline.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/memcpy.align.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/memcpy.inline.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/memmove.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll
A llvm/test/CodeGen/SPIRV/pointers/getelementptr-empty-struct.ll
A llvm/test/CodeGen/SPIRV/ptrmask-logical.ll
A llvm/test/CodeGen/SPIRV/ptrmask-vec.ll
A llvm/test/CodeGen/SPIRV/ptrmask32.ll
A llvm/test/CodeGen/SPIRV/ptrmask64-32.ll
A llvm/test/CodeGen/SPIRV/ptrmask64.ll
M llvm/test/CodeGen/SPIRV/transcoding/atomic-load-store-unsupported.ll
A llvm/test/CodeGen/SPIRV/transcoding/store-atomic-ptr.ll
A llvm/test/CodeGen/WebAssembly/immutable-global-alias.ll
A llvm/test/CodeGen/WebAssembly/imported-const-global.ll
A llvm/test/CodeGen/WebAssembly/invalid-wasm-global-function-alias.ll
A llvm/test/CodeGen/WebAssembly/invalid-wasm-global-symbol.ll
A llvm/test/CodeGen/WebAssembly/multivalue-do-not-stackify.ll
M llvm/test/CodeGen/WebAssembly/multivalue-stackify.ll
M llvm/test/CodeGen/WebAssembly/multivalue.ll
M llvm/test/CodeGen/WebAssembly/multivalue_libcall.ll
M llvm/test/CodeGen/WebAssembly/wide-arithmetic.ll
M llvm/test/CodeGen/X86/apx/ccmp.ll
M llvm/test/CodeGen/X86/apx/ctest.ll
A llvm/test/CodeGen/X86/apx/push2-pop2-cfi-seh-v3.ll
M llvm/test/CodeGen/X86/apx/push2-pop2-cfi-seh.ll
M llvm/test/CodeGen/X86/apx/setzucc.ll
M llvm/test/CodeGen/X86/bypass-slow-division-64.ll
M llvm/test/CodeGen/X86/cmp16.ll
A llvm/test/CodeGen/X86/cpus-hygon.ll
A llvm/test/CodeGen/X86/dag-maps-huge-region-crash.ll
M llvm/test/CodeGen/X86/fast-isel-fcmp.ll
M llvm/test/CodeGen/X86/fast-isel-select-cmov2.ll
M llvm/test/CodeGen/X86/pr27591.ll
M llvm/test/CodeGen/X86/pr32284.ll
M llvm/test/CodeGen/X86/pr53842.ll
M llvm/test/CodeGen/X86/pr54369.ll
M llvm/test/CodeGen/X86/pr57673.ll
M llvm/test/CodeGen/X86/rdpru.ll
A llvm/test/CodeGen/X86/reset-fpenv-mmo.ll
M llvm/test/CodeGen/X86/slow-unaligned-mem.ll
M llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
M llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll
A llvm/test/CodeGen/X86/win64-eh-unwindv3-egpr-required.ll
A llvm/test/CodeGen/X86/win64-eh-unwindv3-funclet-prolog.ll
A llvm/test/CodeGen/X86/win64-eh-unwindv3-push2pop2.ll
A llvm/test/CodeGen/X86/win64-eh-unwindv3-split.ll
A llvm/test/CodeGen/X86/win64-eh-unwindv3-too-many-epilog-ops.mir
A llvm/test/CodeGen/X86/win64-eh-unwindv3-too-many-prolog-ops.mir
A llvm/test/CodeGen/X86/win64-eh-unwindv3.ll
M llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
M llvm/test/CodeGen/X86/zero-call-used-regs.ll
A llvm/test/CodeGen/Xtensa/literal.ll
M llvm/test/DebugInfo/COFF/apx-egpr.ll
M llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
A llvm/test/Instrumentation/InstrProfiling/amdgpu-instrumentation.ll
A llvm/test/Instrumentation/InstrProfiling/amdgpu-profc-arrays.ll
A llvm/test/Instrumentation/InstrProfiling/gpu-weak.ll
A llvm/test/MC/AArch64/coff-secrel-hi12.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
A llvm/test/MC/ARM/bf-invalid-target.s
M llvm/test/MC/AsmParser/seh-directive-errors.s
A llvm/test/MC/COFF/seh-unwindv3-error.s
A llvm/test/MC/COFF/seh-unwindv3-inheritance.s
A llvm/test/MC/COFF/seh-unwindv3-large.s
A llvm/test/MC/COFF/seh-unwindv3-nonmirror.s
A llvm/test/MC/COFF/seh-unwindv3-pool-sharing.s
A llvm/test/MC/COFF/seh-unwindv3.s
A llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16-fake16.txt
R llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
M llvm/test/MC/RISCV/rvv/invalid.s
M llvm/test/MC/RISCV/rvv/vsetvl-alt.s
M llvm/test/MC/RISCV/rvv/vsetvl-invalid.s
M llvm/test/MC/RISCV/rvv/zvfbdota32f-invalid.s
M llvm/test/MC/X86/x86_long_nop.s
M llvm/test/TableGen/ConcatenatedSubregs.td
M llvm/test/TableGen/RegisterClassCopyCost.td
M llvm/test/TableGen/RegisterInfoEmitter-errors.td
M llvm/test/TableGen/switch.td
M llvm/test/TableGen/target-mem-intrinsic-attrs.td
M llvm/test/Transforms/AlignmentFromAssumptions/simple.ll
A llvm/test/Transforms/IndVarSimplify/exit-value-safe-udiv.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
M llvm/test/Transforms/InstCombine/addrspacecast.ll
M llvm/test/Transforms/InstCombine/assume-align.ll
M llvm/test/Transforms/InstCombine/assume.ll
M llvm/test/Transforms/InstCombine/frexp.ll
A llvm/test/Transforms/InstCombine/issue173148-sext-phi-select-infloop.ll
M llvm/test/Transforms/InstCombine/powi.ll
M llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll
M llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
M llvm/test/Transforms/InstSimplify/bitcast-vector-fold.ll
A llvm/test/Transforms/JumpThreading/lifetime-alloca.ll
M llvm/test/Transforms/LICM/hoist-deref-load.ll
M llvm/test/Transforms/LICM/scalar-promote.ll
A llvm/test/Transforms/LoopInterchange/complex-inner-latch-condition.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/transform-narrow-interleave-to-widen-memory.ll
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/single-scalar-cast.ll
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/sve2-histcnt-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
M llvm/test/Transforms/LoopVectorize/VPlan/predicator.ll
A llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-reductions-tail-folded.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-step.ll
M llvm/test/Transforms/LoopVectorize/as_cast.ll
M llvm/test/Transforms/LoopVectorize/cast-costs.ll
M llvm/test/Transforms/LoopVectorize/cast-induction.ll
M llvm/test/Transforms/LoopVectorize/early-exit-calls.ll
M llvm/test/Transforms/LoopVectorize/expand-ptrtoaddr.ll
M llvm/test/Transforms/LoopVectorize/expand-scev-after-invoke.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/induction-step.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleave-with-i65-induction.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/miniters.ll
A llvm/test/Transforms/LoopVectorize/minmax-reduction-unknown-prof.ll
M llvm/test/Transforms/LoopVectorize/narrow-to-single-scalar-widen-gep-scalable.ll
M llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/preserve-inbounds-gep-with-pointer-casts.ll
M llvm/test/Transforms/LoopVectorize/reduction-minmax-users-and-predicated.ll
M llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
M llvm/test/Transforms/LoopVectorize/widen-gep-all-indices-invariant.ll
A llvm/test/Transforms/PGOProfile/amdgpu-disable-value-profiling.ll
M llvm/test/Transforms/PhaseOrdering/ARM/arm_var_q31.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/masked-loads-side-effects-after-vec.ll
A llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-non-scheduled-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-vectorized-later.ll
M llvm/test/Transforms/SimplifyCFG/speculate-store.ll
M llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll
M llvm/test/Verifier/assume-bundles.ll
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-adx.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-aes.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-avx1.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-avx2.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-bmi1.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-bmi2.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-clflushopt.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-clzero.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-cmov.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-cmpxchg.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-f16c.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-fma.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-fsgsbase.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-lea.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-lzcnt.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-mmx.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-movbe.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-mwaitx.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-pclmul.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-popcnt.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-prefetchw.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-rdrand.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-rdseed.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sha.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse1.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse2.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse3.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse41.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse42.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse4a.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-ssse3.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-x86_32.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-x86_64.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-x87.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-xsave.s
A llvm/test/tools/llvm-mca/X86/C864GM4/zero-idioms.s
A llvm/test/tools/llvm-mca/X86/C864GM7/independent-load-stores.s
A llvm/test/tools/llvm-mca/X86/C864GM7/partially-overlapping-group-resources.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-adx.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-aes.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx1.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx2.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bitalg.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bitalgvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bw.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bwvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512cd.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512cdvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512dq.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512dqvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512gfni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512gfnivl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512ifma.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512ifmavl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vaes.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vaesvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi2.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi2vl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmivl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vnni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vnnivl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vp2intersect.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vp2intersectvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpclmulqdq.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpclmulqdqvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpopcntdq.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpopcntdqvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avxgfni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avxvnni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-bmi1.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-bmi2.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-clflushopt.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-clwb.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-cmov.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-cmpxchg.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-f16c.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-fma.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-fsgsbase.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-gfni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-lea.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-lzcnt.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-mmx.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-movbe.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-mwaitx.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-pclmul.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-popcnt.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-prefetchw.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-rdrand.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-rdseed.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sha.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse1.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse2.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse3.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse41.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse42.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse4a.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-ssse3.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-vaes.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-vpclmulqdq.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-x86_32.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-x86_64.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-x87.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-xsave.s
A llvm/test/tools/llvm-mca/X86/C864GM7/zero-idioms.s
M llvm/test/tools/llvm-objdump/MachO/function-starts.test
M llvm/test/tools/yaml2obj/ELF/bb-addr-map-pgo-analysis-map.yaml
M llvm/tools/CMakeLists.txt
M llvm/tools/llvm-exegesis/lib/Assembler.h
M llvm/unittests/ADT/ImmutableListTest.cpp
M llvm/unittests/ADT/StringMapTest.cpp
M llvm/unittests/Analysis/ScalarEvolutionTest.cpp
M llvm/unittests/CodeGen/MachineInstrTest.cpp
M llvm/unittests/MC/CMakeLists.txt
A llvm/unittests/MC/WODRoundTripTest.cpp
M llvm/unittests/ObjectYAML/DXContainerYAMLTest.cpp
M llvm/unittests/Support/DynamicLibrary/DynamicLibraryTest.cpp
M llvm/unittests/Support/DynamicLibrary/PipSqueak.h
M llvm/unittests/TargetParser/TripleTest.cpp
M llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
M llvm/utils/TableGen/Common/InfoByHwMode.h
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
M llvm/utils/gdb-scripts/prettyprinters.py
M llvm/utils/gn/secondary/bolt/unittests/Profile/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/StaticAnalyzer/BUILD.gn
M llvm/utils/gn/secondary/compiler-rt/include/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Windows/Common/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Target/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Frontend/Offloading/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-readtapi/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Target/AArch64/BUILD.gn
M llvm/utils/release/build-docs.sh
M llvm/utils/release/build_llvm_release.bat
M llvm/utils/sanitizers/ubsan_ignorelist.txt
M mlir/docs/CMakeLists.txt
M mlir/docs/doxygen.cfg.in
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationTypeInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgEnums.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
A mlir/include/mlir/Dialect/SPIRV/IR/SPIRVExperimentalMLOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.td
M mlir/include/mlir/Dialect/XeGPU/Transforms/Transforms.h
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
M mlir/include/mlir/Interfaces/MemorySlotInterfaces.td
M mlir/lib/Bytecode/Reader/BytecodeReader.cpp
M mlir/lib/Conversion/MemRefToSPIRV/MemRefToSPIRV.cpp
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
M mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp
M mlir/lib/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationDialect.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
M mlir/lib/Dialect/OpenACC/Transforms/OffloadTargetVerifier.cpp
M mlir/lib/Dialect/SPIRV/IR/CastOps.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/lib/Transforms/Mem2Reg.cpp
M mlir/test/Conversion/MemRefToSPIRV/atomic.mlir
M mlir/test/Conversion/SPIRVToLLVM/cast-ops-to-llvm.mlir
A mlir/test/Conversion/SPIRVToLLVM/cl-ops-to-llvm.mlir
M mlir/test/Conversion/SPIRVToLLVM/gl-ops-to-llvm.mlir
M mlir/test/Conversion/SPIRVToLLVM/logical-ops-to-llvm.mlir
A mlir/test/Conversion/XeGPUToXeVM/loadstore_nd_transpose.mlir
M mlir/test/Dialect/Affine/SuperVectorize/vector_utils.mlir
M mlir/test/Dialect/Affine/SuperVectorize/vectorize_1d.mlir
M mlir/test/Dialect/Affine/SuperVectorize/vectorize_2d.mlir
A mlir/test/Dialect/Affine/SuperVectorize/vectorize_2d_inbounds.mlir
M mlir/test/Dialect/Affine/SuperVectorize/vectorize_affine_apply.mlir
M mlir/test/Dialect/Affine/SuperVectorize/vectorize_reduction.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-non-module-bufferize.mlir
A mlir/test/Dialect/Bufferization/Transforms/test-one-shot-module-bufferize.mlir
M mlir/test/Dialect/LLVMIR/mem2reg-dbginfo.mlir
M mlir/test/Dialect/LLVMIR/nvvm.mlir
M mlir/test/Dialect/Linalg/roundtrip-morphism-linalg-category-ops.mlir
M mlir/test/Dialect/Linalg/specialize-generic-ops.mlir
M mlir/test/Dialect/NVGPU/invalid.mlir
M mlir/test/Dialect/OpenACC/invalid-cg.mlir
M mlir/test/Dialect/OpenACC/offload-target-verifier.mlir
M mlir/test/Dialect/OpenACC/ops-cg.mlir
M mlir/test/Dialect/SPIRV/IR/cast-ops.mlir
A mlir/test/Dialect/SPIRV/IR/experimental-ml-ops.mlir
M mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_3d_gemm.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_3d_mxfp_gemm.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm.mlir
M mlir/test/Target/LLVMIR/nvvm/barrier.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp4x2.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp6x2.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp8x2.mlir
M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
M mlir/test/Target/SPIRV/decorations-id.mlir
A mlir/test/Target/SPIRV/experimental-ml-ops.mlir
M mlir/test/Target/SPIRV/linkage-types.mlir
M mlir/test/Target/SPIRV/struct.mlir
M mlir/test/Transforms/mem2reg.mlir
M mlir/test/lib/Dialect/Bufferization/TestOneShotModuleBufferize.cpp
M mlir/test/lib/Dialect/Bufferization/TestTensorCopyInsertion.cpp
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
M mlir/test/lib/Dialect/Test/TestTypes.cpp
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
M offload/plugins-nextgen/level_zero/src/L0Queue.cpp
M openmp/docs/CMakeLists.txt
M openmp/docs/doxygen.cfg.in
M openmp/runtime/src/i18n/en_US.txt
M openmp/runtime/src/kmp_ftn_entry.h
A openmp/runtime/test/api/omp_nteams_api_restriction.c
M orc-rt/include/CMakeLists.txt
M orc-rt/include/orc-rt/NativeDylibManager.h
A orc-rt/include/orc-rt/sps-ci/CallSPSCI.h
M orc-rt/lib/executor/CMakeLists.txt
M orc-rt/lib/executor/NativeDylibManager.cpp
M orc-rt/lib/executor/Unix/NativeDylibAPIs.inc
A orc-rt/lib/executor/sps-ci/CallSPSCI.cpp
M orc-rt/unittests/CMakeLists.txt
A orc-rt/unittests/CallSPSCITest.cpp
M orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
M orc-rt/unittests/NativeDylibManagerTest.cpp
M polly/docs/CMakeLists.txt
M polly/docs/doxygen.cfg.in
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/kparzysz/resolve-declare-target
Compare: https://github.com/llvm/llvm-project/compare/be8f015c9fcb...ebc076e8d856
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list