[all-commits] [llvm/llvm-project] eac7bb: [AMDGPU] Set SGPR spill stack IDs when creating sp...

[woruyu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: eac7bb457352bad9d630c057b6336b7168eb9e7b
      https://github.com/llvm/llvm-project/commit/eac7bb457352bad9d630c057b6336b7168eb9e7b
  Author: woruyu <1214539920 at qq.com>
  Date:   2026-06-09 (Tue, 09 Jun 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineFrameInfo.h
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/include/llvm/Target/Target.td
    M llvm/lib/CodeGen/MachineFrameInfo.cpp
    M llvm/lib/CodeGen/PrologEpilogInserter.cpp
    M llvm/lib/CodeGen/RegAllocFast.cpp
    M llvm/lib/CodeGen/VirtRegMap.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    A llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
    M llvm/test/TableGen/RegisterInfoEmitter-errors.td
    M llvm/unittests/CodeGen/MachineInstrTest.cpp
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
    M llvm/utils/TableGen/Common/CodeGenRegisters.h
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [AMDGPU] Set SGPR spill stack IDs when creating spill slots (#197628)

### Summary
This PR resolves https://github.com/llvm/llvm-project/issues/195092. 

Teach register classes to describe the StackID to use for their spill
slots, and use it when creating spill frame objects. This lets AMDGPU
SGPR spill slots be marked as TargetStackID::SGPRSpill at construction
time instead of patching the frame object later while emitting spill
instructions.

Also handle SGPR callee-saved spill slots created directly by
SILowerSGPRSpills, which bypass the generic PEI spill slot creation
path. Without this, late SGPR scavenging can see an SGPR spill pseudo
using a default-stack frame index and trip the SGPRSpill assertion.



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