[all-commits] [llvm/llvm-project] edfcac: [clang][bytecode] Refactor backtrace param printin...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Tue Jun 9 08:03:33 PDT 2026
Branch: refs/heads/users/vitalybuka/spr/nfccfi-ignore-cfi-icall-for-diagnostichandlerh
Home: https://github.com/llvm/llvm-project
Commit: edfcac6a5a4c63ee7b7414956031ad87ca635ae8
https://github.com/llvm/llvm-project/commit/edfcac6a5a4c63ee7b7414956031ad87ca635ae8
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Context.h
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
Log Message:
-----------
[clang][bytecode] Refactor backtrace param printing (#202325)
Instead of `classify()`ing the parameter types here, just use the saved
`PrimType` in the `ParamDescriptor`.
This also fixed an oddity with `interp::Context`: `Pointer::toRValue()`
takes an `interp::Context`, but some call sites passed an `ASTContext`
instead, which worked because of the implicit constructor. Make it
explicit.
Commit: 391cbd232dfded7d9af778f9a1fdb04982a15a42
https://github.com/llvm/llvm-project/commit/391cbd232dfded7d9af778f9a1fdb04982a15a42
Author: Garvit Gupta <garvgupt at qti.qualcomm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
Log Message:
-----------
Reland [RISCV] Check SP-relative offset in needsFrameBaseReg when FP offset overflows (#202499)
When a frame pointer is present, needsFrameBaseReg previously only
checked the FP-relative offset to decide if a virtual base register was
needed. If the worst-case FP offset exceeded the 12-bit immediate range,
a base register was always materialized, even when the SP-relative
offset would fit.
Since getFrameIndexReference can now select SP over FP when the offset
fits in the compressed instruction immediate range, also check the
SP-relative offset before deciding a base register is needed. This
avoids unnecessary base register materialization and results in some
code size savings.
Reland of b5d577d3faef.
Commit: eb954b0bb91f3a9374a00279650e1a0977871062
https://github.com/llvm/llvm-project/commit/eb954b0bb91f3a9374a00279650e1a0977871062
Author: ritter-x2a <9519134+ritter-x2a at users.noreply.github.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
Log Message:
-----------
[AMDGPU] Drop docs for invalid load-release and store-acquire operations (#202338)
The LangRef says "release and acq_rel orderings are not valid on load
instructions" [for loads](https://llvm.org/docs/LangRef.html#load-instruction)
and "acquire and acq_rel orderings aren't valid on store instructions"
[for stores](https://llvm.org/docs/LangRef.html#store-instruction).
Providing them in textual IR is diagnosed with an error.
Therefore, we should not define semantics for these invalid constructs.
Part of LCOMPILER-2273.
Commit: fc9bf89cfd9aa312bc5f1a855c76d04cf715d868
https://github.com/llvm/llvm-project/commit/fc9bf89cfd9aa312bc5f1a855c76d04cf715d868
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libcxx/include/CMakeLists.txt
R libcxx/include/__type_traits/dependent_type.h
M libcxx/include/module.modulemap.in
M libcxx/include/variant
Log Message:
-----------
[libc++] Simplify some meta programming in <variant> (#201538)
Specifically, this avoids `__dependent_type` and `__type_identity`
instantiations, reducing compile times a bit.
Commit: 188c0486bd8db4ac51afe1b986228fafe1bdf21b
https://github.com/llvm/llvm-project/commit/188c0486bd8db4ac51afe1b986228fafe1bdf21b
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/test/Analysis/LoopAccessAnalysis/early-exit-runtime-checks.ll
M llvm/test/Transforms/LoopVectorize/early-exit-calls.ll
Log Message:
-----------
[LAA] Don't check for free in evaluatePtrAddRecAtMaxBTCWillNotWrap() (#202341)
The fact that an object of a certain size existed at the the location at
some point is sufficient to prove the desired nowrap fact. Whether the
object still exists there doesn't matter in this context.
Commit: 1ad448f48b3ea8c79e3246dff691d41449db562d
https://github.com/llvm/llvm-project/commit/1ad448f48b3ea8c79e3246dff691d41449db562d
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
Log Message:
-----------
[InstCombine] Don't reuse a sibling binop with extra flags via demanded elts (#199782) (#201545)
SimplifyDemandedVectorElts can replace a vector binop with a sibling
binop. But if the sibling carries a flag the original lacked, it could
produce a result the original never would. E.g.
Reusing `sub nuw` could make the result poison on wrap.
Reusing `fmul nsz` could flip the sign of a zero.
Reusing `fdiv arcp` could make the result less accurate.
Fix by only reusing the sibling when its flags are a subset of the
replaced binop's.
https://alive2.llvm.org/ce/z/9yEaG7
Fixes #199782.
Commit: ae85794cf3a2a6a2742940609be64c1a4f4a60b7
https://github.com/llvm/llvm-project/commit/ae85794cf3a2a6a2742940609be64c1a4f4a60b7
Author: Jiahao Guo <eoonguo at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[CIR][AArch64] Lower NEON vpmax intrinsics (#201495)
### summary
part of : https://github.com/llvm/llvm-project/issues/185382
Adds ClangIR support for all AArch64 NEON pairwise-maximum intrinsics
(vpmax*) in
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#pairwise-maximum
Also enables the scalar pairwise reductions vpmaxs_f32, vpmaxqd_f64,
vpmaxnms_f32, and vpmaxnmqd_f64 by routing them through the common NEON
SISD path (fmaxv / fmaxnmv).
Commit: 6b90b6b4a38d4692d321c03684de6853622c59ea
https://github.com/llvm/llvm-project/commit/6b90b6b4a38d4692d321c03684de6853622c59ea
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/cxx20.cpp
Log Message:
-----------
[clang][bytecode] Check Ptr primtype in Store op (#202314)
Commit: 69215c5e4f03253d78218bf5ac55f81b90118082
https://github.com/llvm/llvm-project/commit/69215c5e4f03253d78218bf5ac55f81b90118082
Author: Jakob Koschel <jakobkoschel at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/docs/SafeStack.rst
M clang/lib/Sema/SemaChecking.cpp
A clang/test/Sema/safestack-deprecated-builtins.c
M compiler-rt/include/CMakeLists.txt
A compiler-rt/include/sanitizer/safestack_interface.h
M compiler-rt/lib/safestack/CMakeLists.txt
M compiler-rt/lib/safestack/safestack.cpp
M compiler-rt/test/safestack/sigaltstack.c
Log Message:
-----------
[SafeStack] Introduce public interface header and deprecate builtins (#198292)
Introduce `sanitizer/safestack_interface.h` to expose SafeStack utility
functions as a public interface, similar to other sanitizers.
Exposed functions:
* `__safestack_get_unsafe_stack_ptr`
* `__safestack_get_unsafe_stack_bottom`
* `__safestack_get_unsafe_stack_top`
Deprecate the existing `__builtin___get_unsafe_stack_*` builtins and
emit warnings suggesting the new `__safestack_` equivalents.
Runtime compatibility aliases `__get_unsafe_stack_*` are maintained.
Commit: c04c945d2563297ca75baf13050594e2bd3dcec5
https://github.com/llvm/llvm-project/commit/c04c945d2563297ca75baf13050594e2bd3dcec5
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/LICM/hoist-deref-load.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/masked-loads-side-effects-after-vec.ll
Log Message:
-----------
[ValueTracking] Handle chain of single-pred blocks in willNotFreeBetween() (#202308)
willNotFreeBetween() currently handles the case where both instructions
are in the same block, or one is in the single predecessor of the other.
This patch extends this to handle a chain of single predecessor blocks.
The budget now applies to all checked instructions, rather than per
block. Also increase the budget by a factor of two (which means that new
budget interpretation should never regress relative to the previous).
Commit: 19250eb71a32aafd540b5f9b03eea6be8121b2d2
https://github.com/llvm/llvm-project/commit/19250eb71a32aafd540b5f9b03eea6be8121b2d2
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/IR/BundleAttributes.h
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/IR/BundleAttributes.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Analysis/ValueTracking/assume.ll
M llvm/test/Transforms/InstCombine/assume.ll
M llvm/test/Verifier/assume-bundles.ll
Log Message:
-----------
[InstCombine] Drop zero size dereferenceable assumptions (#202411)
Commit: e12a55706f77052a20cf315d0d8c83a910b360fb
https://github.com/llvm/llvm-project/commit/e12a55706f77052a20cf315d0d8c83a910b360fb
Author: Yexuan Xiao <bizwen at nykz.org>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGCoroutine.cpp
A clang/test/CodeGenCoroutines/coro-cwg2935.cpp
Log Message:
-----------
[Clang][CodeGen][Coroutines] Make coroutine startup exception-safe (C… (#202279)
…WG2935)
This patch attempts to implement the solution I proposed for [CWG2935
(Github)](https://github.com/cplusplus/CWG/issues/575), aligning Clang's
behavior with GCC and MSVC instead of leaving it undefined. When
`initial_suspend` (as well as `ready` and `suspend`) throws an
exception, Clang fails to destroy the task even though the task has
already been initialized (see https://godbolt.org/z/E4Y4bEn54).
This patch updates CGCoroutine.cpp to clean up the coroutine return
value after an exception is thrown when it is constructed in place,
addressing CWG2935.
I would like to hear more opinions on the solution and seek help to fix
Clang.
Commit: cbffca291f395f8b8055396a417ee7620f6582b9
https://github.com/llvm/llvm-project/commit/cbffca291f395f8b8055396a417ee7620f6582b9
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/InterpFrame.h
Log Message:
-----------
[clang][bytecode] Only save frame offset in debug builds (#202294)
We only ever use this value to verify that a frame has cleaned up after
itself, i.e. in assertions.
Commit: c30ea28015bf0c2899b485c3bf531d7c7e61f518
https://github.com/llvm/llvm-project/commit/c30ea28015bf0c2899b485c3bf531d7c7e61f518
Author: Vaisman <vasili.svirski at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/test/Dialect/NVGPU/invalid.mlir
Log Message:
-----------
[mlir][nvgpu] Add negative tests for warpgroup MMA accumulator ops (#202516)
Add verifier tests for warpgroup MMA accumulator initialization
and store operations.
The tests cover invalid accumulator shapes, unsupported non-f32
store results, and mismatched store destination shapes.
The verifier logic for these cases exists in
WarpgroupMmaInitAccumulatorOp::verify() and
WarpgroupMmaStoreOp::verify(), but lacked explicit negative test
coverage in invalid.mlir.
Commit: bccd1b9cb744e5dd96ee59baa4bf4583457feea3
https://github.com/llvm/llvm-project/commit/bccd1b9cb744e5dd96ee59baa4bf4583457feea3
Author: Fangrui Song <i at maskray.me>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/ADT/StringMap.h
M llvm/lib/Transforms/IPO/StripSymbols.cpp
M llvm/unittests/ADT/StringMapTest.cpp
Log Message:
-----------
[StringMap] Invalidate iterators in remove() (#202520)
erase() bumps the epoch to invalidate iterators (#202237), but the
lower-level remove() — which detaches an entry without destroying it,
used
by ValueSymbolTable via Value::setName() — did not. Move the
incrementEpoch() into remove() so remove-while-iterating fails fast
under
LLVM_ENABLE_ABI_BREAKING_CHECKS too.
Aided by Claude Opus 4.8
Commit: 239a898a235ff81e6208be31670ef143435506c8
https://github.com/llvm/llvm-project/commit/239a898a235ff81e6208be31670ef143435506c8
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
Log Message:
-----------
[AArch64][GlobalISel] Fix post-legalizer observer notifications (#202376)
Assisted-by: codex
Commit: 6a18bd7be02b5f2f663018a5ab30ac12b2d3a00e
https://github.com/llvm/llvm-project/commit/6a18bd7be02b5f2f663018a5ab30ac12b2d3a00e
Author: A. Jiang <de34 at live.cn>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libcxx/include/__format/range_formatter.h
M libcxx/test/std/utilities/format/format.range/format.range.fmtset/format.functions.tests.h
M libcxx/test/std/utilities/format/format.range/format.range.formatter/format.functions.tests.h
Log Message:
-----------
[libc++][format] Propagate `m` when formatting range elements (#94562)
As per
[[tab:formatter.range.type]](https://eel.is/c++draft/tab:formatter.range.type),
the effects of the `m` option need to be propagated to the formatter of
range elements.
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Commit: c155183957c7d4a0a53cf781c266b02dd6f1a377
https://github.com/llvm/llvm-project/commit/c155183957c7d4a0a53cf781c266b02dd6f1a377
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
A llvm/test/CodeGen/AArch64/sve-multivector-fold-imms.ll
Log Message:
-----------
[AArch64][SVE] Select immediate offsets for multi-vector instructions (#201637)
This handles multi-vector intrinsics in getMemVTFromNode() and
implements the missing ISEL patterns needed to select the immediate
(mul vl) offsets.
Commit: 2990f95ae247808e5c0f413d9e91658302ea5b6f
https://github.com/llvm/llvm-project/commit/2990f95ae247808e5c0f413d9e91658302ea5b6f
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
Log Message:
-----------
[SPIR-V] Deduplicate createVariable and createExitVariable helpers into SPIRVUtils (#202512)
Commit: 620cdfb1d1000e9de4cdeb35dfa60ff0299d925e
https://github.com/llvm/llvm-project/commit/620cdfb1d1000e9de4cdeb35dfa60ff0299d925e
Author: Access <ShootingStarDragons at protonmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang-tools-extra/clangd/CompileCommands.cpp
M clang-tools-extra/clangd/unittests/CompileCommandsTests.cpp
Log Message:
-----------
[clangd][Mangler] Drop unknown compile options (#200001)
this pr remove the options that not work for clang, which will make
compile failed for clang++, and this will make modules completions of
clangd work. And we will also log the unsupported options
Commit: 99f6a20075abd71b4dd64b073c6159e507495cd2
https://github.com/llvm/llvm-project/commit/99f6a20075abd71b4dd64b073c6159e507495cd2
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/test/AST/ByteCode/codegen.cpp
Log Message:
-----------
[clang][bytecode] Check floating-point semantics in `Memcpy` op (#202204)
We shouldn't try to do the memcpy if the semantics don't match.
Commit: 7f6f60f8325aa724331a768a589e2c22b19f0416
https://github.com/llvm/llvm-project/commit/7f6f60f8325aa724331a768a589e2c22b19f0416
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/lib/Conversion/MemRefToSPIRV/MemRefToSPIRV.cpp
M mlir/test/Conversion/MemRefToSPIRV/atomic.mlir
Log Message:
-----------
[mlir][SPIR-V] Support floating-point atomic_rmw addf in MemRefToSPIRV (#202330)
Commit: 95c24830265cba8c4844dda3384025bac0bf96b4
https://github.com/llvm/llvm-project/commit/95c24830265cba8c4844dda3384025bac0bf96b4
Author: Diego Novillo <dnovillo at nvidia.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Options/Options.td
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/CodeGenHLSL/preserve-interface-dce.hlsl
A clang/test/CodeGenHLSL/preserve-interface.hlsl
A clang/test/Driver/dxc_fspv_preserve_interface.hlsl
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/test/CodeGen/SPIRV/preserve-interface-dce.ll
A llvm/test/CodeGen/SPIRV/preserve-interface.ll
Log Message:
-----------
[clang][SPIR-V] Implement -fspv-preserve-interface (#196404)
This flag, originally implemented in DXC, prevents GlobalDCE from
removing entry-point interface variables, even if they are unreferenced
after inlining.
This adds `HLSLSpvPreserveInterface` to `LangOptions.def` and
`Options.td`. In `CGHLSLRuntime::finishCodeGen()`, it adds all
`addrspace(7)` and `addrspace(8)` globals to `llvm.compiler.used`.
In `processGlobalValue()`, it extends the condition that emits
`spv_unref_global` to fire for globals whose only uses come from
`llvm.compiler.used` or `llvm.used`.
Fixes https://github.com/llvm/llvm-project/issues/136936
Commit: 8b4902300521d4a0980d9d35210c02b405f0df86
https://github.com/llvm/llvm-project/commit/8b4902300521d4a0980d9d35210c02b405f0df86
Author: Garvit Gupta <garvgupt at qti.qualcomm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M compiler-rt/test/builtins/Unit/lit.cfg.py
Log Message:
-----------
[Compiler-rt][test] Fix circular link dependency between builtins and libc (#199482)
Currently, the link order is `libclang_rt.builtins.a -lc -lm`. Builtins
are scanned first after which symbols like `abort` are unresolved
references that are resolved through libc.a. However, resolving the
references to these symbols further lead to undefined references to
`_aeabi_uldivmod` etc. that can only resolved through builtins.
Reversing the order also wont fix the issue because `libc.a` introduces
`__aeabi_uldivmod` which is resolved by builtins but it introduces
`abort` which can only be resolved libc.a.
This patch fixes this by wrapping the archives in a linker group
(--start-group/--end-group), which instructs the linker to rescan all
archives in the group until no new symbols can be resolved.
This error is exposed only when bfd like linkers are used.
Commit: ab31c28892a9ad5e016e94500861c93018736e7b
https://github.com/llvm/llvm-project/commit/ab31c28892a9ad5e016e94500861c93018736e7b
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Target/LLVMIR/nvvm/convert_fp4x2.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp6x2.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp8x2.mlir
M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
Log Message:
-----------
[MLIR][NVVM] Add support for narrow-fp to bf16x2 conversions (#200157)
This change adds the following NVVM Ops to support narrow-fp to bf16x2
conversions:
- `nvvm.convert.f6x2.to.bf16x2`
- `nvvm.convert.f4x2.to.bf16x2`
- `nvvm.convert.f8x2.to.bf16x2` (updated to allow `E4M3FN` and `E5M2`
types)
Also removes unnecessary verifiers for narrow-fp to `f16x2` conversions
to instead use `TypeAttrOf` to validate the source type in the ODS
definition.
Commit: c3d13ceb8a894312211c88bf2ef947708442a855
https://github.com/llvm/llvm-project/commit/c3d13ceb8a894312211c88bf2ef947708442a855
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization.ll
Log Message:
-----------
[AMDGPU] Use alloc size for array stride in LowerBufferFatPointers (#202530)
Array elements are laid out at multiples of getTypeAllocSize, not
getTypeStoreSize
LLVM memory model lays out array element `i` at `i * allocSize`
(reflected in `DataLayout::getTypeAllocSize`), apply it for fat pointers
to prevent miscompile
Commit: 3fec9c702b597e1a0204ff30137ae8d1557e395c
https://github.com/llvm/llvm-project/commit/3fec9c702b597e1a0204ff30137ae8d1557e395c
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/test/Conversion/SPIRVToLLVM/cast-ops-to-llvm.mlir
A mlir/test/Conversion/SPIRVToLLVM/cl-ops-to-llvm.mlir
M mlir/test/Conversion/SPIRVToLLVM/gl-ops-to-llvm.mlir
M mlir/test/Conversion/SPIRVToLLVM/logical-ops-to-llvm.mlir
Log Message:
-----------
[mlir][SPIR-V] Add SPIRVToLLVM direct conversions for cast, CL, GL and logical ops (#202506)
Lower the OpenCL extended instruction set math ops, GL math ops (Trunc,
Asin, Acos, Atan), logical Ordered/Unordered, and the pointer cast ops
to their LLVM dialect equivalents
Commit: 6bf8d4b059bd5cd4b660be6063769a9f162e5ec0
https://github.com/llvm/llvm-project/commit/6bf8d4b059bd5cd4b660be6063769a9f162e5ec0
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-step.ll
M llvm/test/Transforms/LoopVectorize/expand-scev-after-invoke.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleave-with-i65-induction.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
Log Message:
-----------
[VPlan] Look through BCast when folding live-ins (#202527)
This gives us some minor improvements.
Commit: bf860889a8ff3fea28dbace895cd633ccbe79608
https://github.com/llvm/llvm-project/commit/bf860889a8ff3fea28dbace895cd633ccbe79608
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/unittests/Support/DynamicLibrary/DynamicLibraryTest.cpp
Log Message:
-----------
Revert "[test][Support] Disable CFI-icall for DynamicLibrary Overload test" (#202550)
Reverts llvm/llvm-project#202446
Commit: 383db8a1ddc9f8db49c8305e463b3a80b7cd8638
https://github.com/llvm/llvm-project/commit/383db8a1ddc9f8db49c8305e463b3a80b7cd8638
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M .ci/compute_projects.py
Log Message:
-----------
[CI][Offload] Fix offload depends on openmp (#202541)
It appears that Offload depends on OpenMP. Thus, enable OpenMP as a
runtime to test when offload has changes.
Commit: 08636d456502fb7404e632598e16f3698367a6f7
https://github.com/llvm/llvm-project/commit/08636d456502fb7404e632598e16f3698367a6f7
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
A mlir/include/mlir/Dialect/SPIRV/IR/SPIRVExperimentalMLOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.td
A mlir/test/Dialect/SPIRV/IR/experimental-ml-ops.mlir
A mlir/test/Target/SPIRV/experimental-ml-ops.mlir
Log Message:
-----------
[mlir][spirv] Add Arm.ExperimentalMLOperations.1 extended inst set (#202283)
This instruction set provides a mechanism to encode experimental ML
operations in SPIR-V modules. Such instructions are encoded via the
single CALL operator in the instruction set by specifying an op_code and
customized inputs values.
Reference:
https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extended/Arm.ExperimentalMLOperations.asciidoc
Signed-off-by: Niklas Lithammer <niklas.lithammer at arm.com>
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: 514f5b766667c4c696b260f783403e8b41bc8798
https://github.com/llvm/llvm-project/commit/514f5b766667c4c696b260f783403e8b41bc8798
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/test/Transforms/InstSimplify/bitcast-vector-fold.ll
Log Message:
-----------
[ConstantFolding] Fix dropped bits in non-integer-ratio bitcast with undef lane (#202282)
When constant-folding a vector bitcast(e.g. <4 x i24> -> <3 x i32>), an
undef source element inserted a DstBitSize-wide zero placeholder into
the bit buffer. This could clobber defined source element, producing a
wrong result on big-endian targets.
Fix by inserting SrcBitSize-wide zero instead.
Alive2 proof:
before (unsound): https://alive2.llvm.org/ce/z/R_ZQ75
after (verified): https://alive2.llvm.org/ce/z/VuV3mz
Commit: 6746898d2bfc086947d86715e065f8dbf74e9690
https://github.com/llvm/llvm-project/commit/6746898d2bfc086947d86715e065f8dbf74e9690
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Options/Options.td
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
R clang/test/CodeGenHLSL/preserve-interface-dce.hlsl
R clang/test/CodeGenHLSL/preserve-interface.hlsl
R clang/test/Driver/dxc_fspv_preserve_interface.hlsl
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
R llvm/test/CodeGen/SPIRV/preserve-interface-dce.ll
R llvm/test/CodeGen/SPIRV/preserve-interface.ll
Log Message:
-----------
Revert "[clang][SPIR-V] Implement -fspv-preserve-interface (#196404)" (#202558)
This reverts commit 95c24830265cba8c4844dda3384025bac0bf96b4.
Fail log:
https://lab.llvm.org/buildbot/#/builders/226/builds/9015/steps/7/logs/stdio
```
FAILED: lib/libLLVMFrontendHLSL.so.23.0git
: && /opt/rh/gcc-toolset-13/root/usr/bin/c++ -fPIC -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror=date-time -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wno-uninitialized -Wno-nonnull -Wno-class-memaccess -Wno-dangling-reference -Wno-redundant-move -Wno-pessimizing-move -Wno-array-bounds -Wno-stringop-overread -Wno-dangling-pointer -Wno-noexcept-type -Wdelete-non-virtual-dtor -Wsuggest-override -Wno-comment -Wno-misleading-indentation -Wctad-maybe-unsupported -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -DNDEBUG -Wl,-z,defs -Wl,-z,nodelete -Wl,-rpath-link,/home/botworker/bbot/amdgpu-offload-build-only/build/./lib -Wl,--gc-sections -shared -Wl,-soname,libLLVMFrontendHLSL.so.23.0git -o lib/libLLVMFrontendHLSL.so.23.0git lib/Frontend/HLSL/CMakeFiles/LLVMFrontendHLSL.dir/CBuffer.cpp.o lib/Frontend/HLSL/CMakeFiles/LLVMFrontendHLSL.dir/HLSLBinding.cpp.o lib/Frontend/HLSL/CMakeFiles/LLVMFrontendHLSL.dir/HLSLResource.cpp.o lib/Frontend/HLSL/CMakeFiles/LLVMFrontendHLSL.dir/HLSLRootSignature.cpp.o lib/Frontend/HLSL/CMakeFiles/LLVMFrontendHLSL.dir/RootSignatureMetadata.cpp.o lib/Frontend/HLSL/CMakeFiles/LLVMFrontendHLSL.dir/RootSignatureValidations.cpp.o -Wl,-rpath,"\$ORIGIN/../lib:\$ORIGIN/../lib/x86_64-unknown-linux-gnu:/home/botworker/bbot/amdgpu-offload-build-only/build/lib:" lib/libLLVMCore.so.23.0git lib/libLLVMBinaryFormat.so.23.0git lib/libLLVMSupport.so.23.0git -Wl,-rpath-link,/home/botworker/bbot/amdgpu-offload-build-only/build/lib && :
/opt/rh/gcc-toolset-13/root/usr/libexec/gcc/x86_64-redhat-linux/13/ld: lib/Frontend/HLSL/CMakeFiles/LLVMFrontendHLSL.dir/CBuffer.cpp.o: in function `llvm::hlsl::CBufferMetadata::removeCBufferGlobalsFromUseList(llvm::Module&)':
CBuffer.cpp:(.text._ZN4llvm4hlsl15CBufferMetadata31removeCBufferGlobalsFromUseListERNS_6ModuleE+0xce): undefined reference to `llvm::removeFromUsedLists(llvm::Module&, llvm::function_ref<bool (llvm::Constant*)>)'
collect2: error: ld returned 1 exit status
```
Commit: a172eb9fcdebc93ad123b1f9d8b3ba953b904e7d
https://github.com/llvm/llvm-project/commit/a172eb9fcdebc93ad123b1f9d8b3ba953b904e7d
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
Log Message:
-----------
[GlobalISel][AMDGPU] Emit proper diagnostic when inline asm register allocation fails (#201380)
Replace the silent fallback return with a DiagnosticInfoInlineAsm error
and undef result values, so the failure is reported to the user instead
of relying on -global-isel-abort
discussed in https://github.com/llvm/llvm-project/pull/200771
Commit: 944284fe6329eb133bdbf9af77af6fa0cd280070
https://github.com/llvm/llvm-project/commit/944284fe6329eb133bdbf9af77af6fa0cd280070
Author: Matthias Springer <me at m-sp.org>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
Log Message:
-----------
[mlir][Interfaces] Document completeness requirement of `RegionBranchOpInterface` (#202018)
Document that interface implementations must report all possible control
flow edges. Failure to report a possible edge may break
analyses/transformations/APIs such as
`RegionBranchOpInterface::isRepetitiveRegion`.
Commit: 0f6f15a59f3f774a7f055f9754fe97c088390c4e
https://github.com/llvm/llvm-project/commit/0f6f15a59f3f774a7f055f9754fe97c088390c4e
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
A llvm/test/Transforms/IndVarSimplify/exit-value-safe-udiv.ll
Log Message:
-----------
[SCEVExpander] Don't expand a UDiv with a possibly-poison divisor (#202378)
SCEVExpander::isSafeToExpand only check divisor isKnownNonZero, which
ignore the possibility of poison. For the following divisor:
```
%ct = call i32 @llvm.cttz.i32(i32 %x, i1 true)
%divisor = add i32 %ct, 1
...
%rem = urem i32 1, %divisor
```
The urem may be hoisted unsafely.
Fix by also check divisor isGuaranteedNotToBePoison.
Fixes https://github.com/llvm/llvm-project/issues/202028
Commit: 96a263602fa6a8130cf9f67723bddb27787b7d97
https://github.com/llvm/llvm-project/commit/96a263602fa6a8130cf9f67723bddb27787b7d97
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/InterpFrame.h
Log Message:
-----------
[clang][bytecode] Remove `InterpFrame::ThisPointerOffset` (#202322)
Replace it with a `uint8_t` representing some bool flags about the
function. This reduces the size of a frame from 88 to 80 bytes.
Commit: 09b451f1e7f7715b5cf994c24ef698b2a8579dbc
https://github.com/llvm/llvm-project/commit/09b451f1e7f7715b5cf994c24ef698b2a8579dbc
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libcxx/include/__bit_reference
A libcxx/test/libcxx/containers/sequences/vector.bool/nodiscard.iterator.verify.cpp
Log Message:
-----------
[libc++][vector] Apply `[[nodiscard]]` to `vector<bool>::iterator` (#202265)
Towards #172124
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Commit: c4f4206ff3ab97db9577f11bb2dabd40896bcca9
https://github.com/llvm/llvm-project/commit/c4f4206ff3ab97db9577f11bb2dabd40896bcca9
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
A libcxx/test/libcxx/containers/sequences/vector/nodiscard.iterator.verify.cpp
Log Message:
-----------
[libc++][vector] Test `[[nodiscard]]` applied to `vector::iterator` (#202262)
Adds test coverage.
`[[nodicard]]` applied in:
- #198489
- #198492
Towards #172124
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Commit: 01d3932364bee33f8e861d5664c2983cc855124f
https://github.com/llvm/llvm-project/commit/01d3932364bee33f8e861d5664c2983cc855124f
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/Headers/__clang_hip_runtime_wrapper.h
A clang/test/Headers/hip-constexpr-cmath.hip
Log Message:
-----------
[Clang][HIP] Include `__clang_cuda_math_forward_declares.h` before `<cmath>` (#201563)
In HIP, `constexpr` functions are treated as both `__host__` and
`__device__`.
A new version of the MS STL shipped with the build tools version
14.51.36231 has `constexpr` definitions for some `cmath` functions when
the
compiler in use is Clang (this gets worse when C++23 is in use).
These definitions conflict with the `__device__` declarations we provide
in the header wrappers.
There is a workaround for this: We do not mark `constexpr`
functions [_that are defined in a system
header_](https://github.com/llvm/llvm-project/blob/03127a03860b9d8cb440fe8f51c00647f45eb8be/clang/lib/Sema/SemaCUDA.cpp#L877)
as
`__host__` and `__device__` if there is a previous `__device__`
declaration.
By moving `__clang_cuda_math_forward_declares.h` before `<cmath>` is
included we're able to benefit from this behavior.
This fixes error like this one
https://github.com/ggml-org/llama.cpp/issues/22570
even for recent versions of C++.
This patch should address C++23 concerns where more functions are marked
as `constexpr`.
However, we should still figure out how to provide `__device__
constexpr` versions for those functions, or not provide ours and use the
system's if they exist.
This patch replaces https://github.com/llvm/llvm-project/pull/200395
Commit: d7d9601c182889ec5e25492fb94d22a70c03fc2b
https://github.com/llvm/llvm-project/commit/d7d9601c182889ec5e25492fb94d22a70c03fc2b
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/Loads.h
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/MemDerefPrinter.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/MachineOperand.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
Log Message:
-----------
[Loads] Migrate isDereferenceable APIs to SimplifyQuery (#202553)
These take the usual set of analysis parameters, so we can encapsulate
them using SimplifyQuery.
Commit: 0e9ff9805decab9896068f37c18a713a68e53f93
https://github.com/llvm/llvm-project/commit/0e9ff9805decab9896068f37c18a713a68e53f93
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M offload/plugins-nextgen/level_zero/src/L0Queue.cpp
Log Message:
-----------
[OFFLOAD][L0] Add wait events for AsyncQueue memFill (#202287)
Fix an issue where memFill operations were not chained properly with respect prior operations.
Commit: 9ac836b3ddff45ebd9f4d23cae3e573991c7f64c
https://github.com/llvm/llvm-project/commit/9ac836b3ddff45ebd9f4d23cae3e573991c7f64c
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/intap.cpp
Log Message:
-----------
[clang][bytecode] Fix shifting by negative IntAP values (#202505)
The negation of a negative value didn't necessarily result in a positive
value. Fix that by giving it one more bit of precision.
Commit: 96480b2880838fe3fb3f3120347beb1ed1560d37
https://github.com/llvm/llvm-project/commit/96480b2880838fe3fb3f3120347beb1ed1560d37
Author: Andrei Golubev <andrey.golubev at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationTypeInterfaces.td
M mlir/lib/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationDialect.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-non-module-bufferize.mlir
A mlir/test/Dialect/Bufferization/Transforms/test-one-shot-module-bufferize.mlir
M mlir/test/lib/Dialect/Bufferization/TestOneShotModuleBufferize.cpp
M mlir/test/lib/Dialect/Bufferization/TestTensorCopyInsertion.cpp
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
M mlir/test/lib/Dialect/Test/TestTypes.cpp
Log Message:
-----------
[mlir][bufferization] Drop TensorLikeType::getBufferType() (#201350)
Replace TensorLikeType::getBufferType() with
options.unknownTypeConverterFn() hook. Make the hook work with
tensor-like and buffer-like types (instead of builtins) to maintain the
same behaviour at the API boundary level and still allow user types to
be properly supported.
Historically, an attempt to support user types within the one-shot
bufferization framework was made. As part of it,
TensorLikeType::getBufferType() was introduced to allow user-provided
types to customize bufferization. However, the whole affair proved to be
overly complex: there is an interface with customization points for
user-provided tensors, and options-based (not sufficient) implementation
for builtin tensors. On top of this, there was always a
function-specific hook to customize function-level behaviour further. As
a result of this, users would need to implement two different mechanisms
on their end: interface implementation + option hooks.
It seems more reasonable at this stage to thus drop the interface part
and just allow unknown type conversion hook to be used directly. That
way, users would only need to supply that hook themselves (with the
caveat of having to perform a type dispatch inside of the hook).
As a drive by, multiple tests that exercise the usage of custom tensor
type (e.g. !test.test_tensor) are moved to work on top of a test pass.
Default memory space inference hook is also updated to work on top of
tensor-like type to align the signature to the unknown type conversion.
Note for LLVM integration:
* Implementation(s) of `TensorLikeType::getBufferType()` for
(user-provided) tensor types should now be moved into a user-specified
`BufferizationOptions::unknownTypeConverterFn()` hook
* In case upstream one-shot-bufferization pass was used to bufferize IR
with user types, such a setup would likely fail now, since a fallback to
type-based bufferization can now only be set through bufferization
options, and cannot be configured at the upstream pass level. One needs
to create a new pass that sets up the necessary bufferization hooks and
calls one-shot-bufferization infrastructure manually.
Commit: f704a92281ee2ff741fa94048970ac6dea19a1b6
https://github.com/llvm/llvm-project/commit/f704a92281ee2ff741fa94048970ac6dea19a1b6
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/test/CodeGenHLSL/ArrayAssignable.hlsl
M clang/test/CodeGenHLSL/ArrayAssignable.logicalptr.hlsl
M clang/test/CodeGenHLSL/cbuffer-matrix-layout-keyword.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer-empty-struct-array.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_and_namespaces.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_with_packoffset.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_with_static_global_and_function.hlsl
M clang/test/CodeGenHLSL/resources/default_cbuffer.hlsl
M clang/test/CodeGenHLSL/resources/default_cbuffer_with_layout.hlsl
M llvm/include/llvm/Frontend/HLSL/CBuffer.h
M llvm/lib/Frontend/HLSL/CBuffer.cpp
M llvm/lib/Target/DirectX/DXILCBufferAccess.cpp
M llvm/lib/Target/SPIRV/SPIRVCBufferAccess.cpp
R llvm/test/CodeGen/DirectX/cbuffer_global_elim.ll
R llvm/test/CodeGen/SPIRV/cbuffer_global_elim.ll
Log Message:
-----------
Revert "[HLSL] Set visibility of cbuffer global variables to internal" (#202538)
Reverts llvm/llvm-project#200312
Breaks several buildbots, e.g.,
https://lab.llvm.org/buildbot/#/builders/203/builds/48531
Co-authored-by: Nikolas Klauser <nikolasklauser at berlin.de>
Commit: 00e3e6f4cbbba60ddfcd648269dd5f2e8d799cbc
https://github.com/llvm/llvm-project/commit/00e3e6f4cbbba60ddfcd648269dd5f2e8d799cbc
Author: Xiaomeng Zhang <zhangxiaomeng at hygon.cn>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/Basic/Targets/X86.cpp
M clang/test/CodeGen/target-builtin-noerror.c
M clang/test/Driver/x86-march.c
M clang/test/Frontend/x86-target-cpu.c
M clang/test/Misc/target-invalid-cpu-note/x86.c
M clang/test/Preprocessor/predefined-arch-macros.c
M compiler-rt/lib/builtins/cpu_model/x86.c
M llvm/include/llvm/TargetParser/Host.h
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/TargetParser/X86TargetParser.h
M llvm/lib/Target/X86/X86.td
A llvm/lib/Target/X86/X86ScheduleC864GM4.td
A llvm/lib/Target/X86/X86ScheduleC864GM7.td
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/test/CodeGen/X86/bypass-slow-division-64.ll
M llvm/test/CodeGen/X86/cmp16.ll
A llvm/test/CodeGen/X86/cpus-hygon.ll
M llvm/test/CodeGen/X86/rdpru.ll
M llvm/test/CodeGen/X86/slow-unaligned-mem.ll
M llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
M llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll
M llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
M llvm/test/MC/X86/x86_long_nop.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-adx.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-aes.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-avx1.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-avx2.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-bmi1.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-bmi2.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-clflushopt.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-clzero.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-cmov.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-cmpxchg.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-f16c.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-fma.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-fsgsbase.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-lea.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-lzcnt.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-mmx.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-movbe.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-mwaitx.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-pclmul.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-popcnt.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-prefetchw.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-rdrand.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-rdseed.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sha.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse1.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse2.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse3.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse41.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse42.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse4a.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-ssse3.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-x86_32.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-x86_64.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-x87.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-xsave.s
A llvm/test/tools/llvm-mca/X86/C864GM4/zero-idioms.s
A llvm/test/tools/llvm-mca/X86/C864GM7/independent-load-stores.s
A llvm/test/tools/llvm-mca/X86/C864GM7/partially-overlapping-group-resources.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-adx.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-aes.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx1.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx2.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bitalg.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bitalgvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bw.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bwvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512cd.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512cdvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512dq.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512dqvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512gfni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512gfnivl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512ifma.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512ifmavl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vaes.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vaesvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi2.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi2vl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmivl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vnni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vnnivl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vp2intersect.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vp2intersectvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpclmulqdq.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpclmulqdqvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpopcntdq.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpopcntdqvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avxgfni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avxvnni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-bmi1.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-bmi2.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-clflushopt.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-clwb.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-cmov.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-cmpxchg.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-f16c.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-fma.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-fsgsbase.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-gfni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-lea.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-lzcnt.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-mmx.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-movbe.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-mwaitx.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-pclmul.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-popcnt.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-prefetchw.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-rdrand.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-rdseed.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sha.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse1.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse2.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse3.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse41.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse42.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse4a.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-ssse3.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-vaes.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-vpclmulqdq.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-x86_32.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-x86_64.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-x87.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-xsave.s
A llvm/test/tools/llvm-mca/X86/C864GM7/zero-idioms.s
Log Message:
-----------
[X86] Hygon Processors Initial enablement (#187622)
This patch adds initial support for several Hygon architectures.
The Hygon architectures include:
- c86-4g-m4
- c86-4g-m6
- c86-4g-m7
This patch includes:
- Added Hygon architectures CPU targets recognition in Clang and LLVM
- Added Hygon architectures to target parser and host CPU detection
- Updated compiler-rt CPU model detection for Hygon architectures
- Added Hygon architectures to various optimizer tests
- Added scheduler models for Hygon architectures CPU targets
Commit: 11cf29581486565b04767ce313602312824d0109
https://github.com/llvm/llvm-project/commit/11cf29581486565b04767ce313602312824d0109
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/tools/llvm-exegesis/lib/Assembler.h
Log Message:
-----------
Revert "[NFC][llvm-exegesis] Disable CFI-icall for JIT-executed function" (#202571)
Reverts llvm/llvm-project#202472
Commit: a1c1cdd44b372c08125d2b6a4aa445620cd284a3
https://github.com/llvm/llvm-project/commit/a1c1cdd44b372c08125d2b6a4aa445620cd284a3
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/AlignmentFromAssumptions.cpp
M llvm/test/Transforms/AlignmentFromAssumptions/simple.ll
Log Message:
-----------
[AlignmentFromAssumes] Skip huge alignment (#202567)
Fixes https://github.com/llvm/llvm-project/issues/202043
Though `align` on huge alignment is not supported, the case below
confirms we allow huge alignment in `assume`:
https://github.com/llvm/llvm-project/blob/c4f4206ff3ab97db9577f11bb2dabd40896bcca9/llvm/test/Transforms/InstCombine/assume.ll#L71
In this case, we should skip huge alignment in AlignmentFromAssumes.
Commit: 0f8a3b23f1e1ffe69d6d49576347ea967ec611be
https://github.com/llvm/llvm-project/commit/0f8a3b23f1e1ffe69d6d49576347ea967ec611be
Author: Anshul Nigham <nigham at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-and.mir
M llvm/test/CodeGen/AArch64/GlobalISel/opt-overlapping-and-postlegalize.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combine-ptr-add-chain.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-hoist-same-hands.mir
Log Message:
-----------
[NewPM][AArch64][GlobalISel] Port AArch64PostLegalizerCombiner to NewPM (#194156)
Adds a standard porting.
Updates some (but not all) tests to verify the NewPM path is working.
Commit: 85ab77340528a7d2e03595aa43c42fcb6105f650
https://github.com/llvm/llvm-project/commit/85ab77340528a7d2e03595aa43c42fcb6105f650
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
A llvm/test/Transforms/InstCombine/issue173148-sext-phi-select-infloop.ll
Log Message:
-----------
[InstCombine] Fix infinite combine loop in evaluateInDifferentType (#202572)
The implementation assumes that all original uses inside visited
instructions would get removed as part of changing the type. However,
this is not true for uses in select conditions, as only the value
operands change type in that case. Bail out if we encounter uses in
select conditions to avoid this.
Fixes https://github.com/llvm/llvm-project/issues/173148.
Commit: 9dfcf7663b1604ae5ced030a69e2be0e93632d5e
https://github.com/llvm/llvm-project/commit/9dfcf7663b1604ae5ced030a69e2be0e93632d5e
Author: Fangrui Song <i at maskray.me>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/docs/ProgrammersManual.rst
M llvm/include/llvm/ADT/StringMap.h
M llvm/lib/Support/StringMap.cpp
M llvm/unittests/ADT/StringMapTest.cpp
M llvm/utils/gdb-scripts/prettyprinters.py
Log Message:
-----------
[StringMap] Replace tombstone deletion with TAOCP 6.4 Algorithm R (#202103)
StringMap uses quadratic probing with lazy deletion: an erased entry
becomes a tombstone, a third bucket state alongside empty and live that
every find/insert must inspect.
Switch to linear probing with Knuth TAOCP 6.4 Algorithm R deletion,
similar to DenseMap #200595.
erase now relocates the following entries to close the hole. StringMap
buckets are pointers to heap-allocated entries, so only the pointers
(and the parallel hash array) move. References and pointers to entries
remain valid, but iterators are invalidated.
Depends on #202237 and #202520
Aided by Claude Opus 4.8
Commit: ca227bff07085250e3a146dadf2ea3246d8b23a8
https://github.com/llvm/llvm-project/commit/ca227bff07085250e3a146dadf2ea3246d8b23a8
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
Log Message:
-----------
[AMDGPU] Produce ballot/icmp/fcmp lane masks at wavefront width (#201358)
Commit: f7e4167f816ac8c5a6e553c66f3b90fe040d1362
https://github.com/llvm/llvm-project/commit/f7e4167f816ac8c5a6e553c66f3b90fe040d1362
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
Log Message:
-----------
[AMDGPU] Clamp load_monitor scope to minimum SCOPE_SE (#198245)
The load_monitor instructions monitor L2 cache lines and therefore
require at least SCOPE_SE to ensure the L2 cache is hit. The current
memory model requires the user to ensure that the specified scope is
such that it results in at least SCOPE_SE, otherwise the behaviour is
undefined. Instead, we now clamp the emitted scope at a minimum of
SCOPE_SE, so that the undefined behaviour is converted into a
performance loss instead.
Assisted-By: Claude Opus 4.6
Commit: 323285f141535bfa8607f773c814000dd4f69e98
https://github.com/llvm/llvm-project/commit/323285f141535bfa8607f773c814000dd4f69e98
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-vectorized-later.ll
Log Message:
-----------
[SLP] Update test against const-folding (#202532)
223ef1f3 ([IRBuilder] ConstFold unary intrinsics, #200496) made a lot of
test updates to SLPVectorizer. The tests were written a long time ago,
and it is unclear what their intent was, but at least update the one
test to replace constants with arguments, where the intent is clear.
Commit: 7581dc5a298dd1736c84ff21fbc310d40901a894
https://github.com/llvm/llvm-project/commit/7581dc5a298dd1736c84ff21fbc310d40901a894
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/unions.cpp
Log Message:
-----------
[clang][bytecode] Fix an assertion failure in visitDtorCall() (#202507)
In `emitDestructionPop()`, we assert that the Descriptor has a
non-trivial dtor. Check this first here so we don't do all this work for
nothing.
Commit: 057a1fe9bd5b3c72ea6d65c456d1266fc20d8e33
https://github.com/llvm/llvm-project/commit/057a1fe9bd5b3c72ea6d65c456d1266fc20d8e33
Author: anjenner <161845516+anjenner at users.noreply.github.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
Log Message:
-----------
[AMDGPU][GISel] Add register bank legalization rules for amdgcn_raw_buffer_load_async_lds (#201406)
Also amdgcn_struct_buffer_load_async_lds,
amdgcn_raw_ptr_buffer_load_async_lds, and
amdgcn_struct_ptr_buffer_load_async_lds.
Commit: 271c8b75cde53d78da5ce971ced8694cca149749
https://github.com/llvm/llvm-project/commit/271c8b75cde53d78da5ce971ced8694cca149749
Author: Vinit Deodhar <vadeodhar89 at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgEnums.td
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
M mlir/test/Dialect/Linalg/roundtrip-morphism-linalg-category-ops.mlir
M mlir/test/Dialect/Linalg/specialize-generic-ops.mlir
Log Message:
-----------
[mlir][linalg] Add sin, cos, tan to elementwise operations (#200950)
Add sin, cos, and tan as UnaryFn entries in the linalg dialect, enabling
their use via linalg.elementwise, named ops (linalg.sin, linalg.cos,
linalg.tan), and specialization from linalg.generic.
---------
Co-authored-by: Vinit Deodhar <vinitdeodhar at users.noreply.github.com>
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
Co-authored-by: Vinit Deodhar <vdeodhar at ah-vdeodhar-l.dhcp.mathworks.com>
Commit: 9129363adbcc3474639e2a3b2b263905da1f86ca
https://github.com/llvm/llvm-project/commit/9129363adbcc3474639e2a3b2b263905da1f86ca
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
Log Message:
-----------
[GlobalISel] Use more inline elements in a match table SmallVector (#202568)
The 4 inline elements for OnFailResumeAt only cover 36.8% (33455 / 90902) of
aarch64-isel executeMatchTable invocations encountered while compiling sqlite3
on aarch64-O0-g.
The 8 inline elements cover 100% (maximum observed depth was 6). Small -0.09%
CTMark geomean improvement on aarch64-O0-g.
https://llvm-compile-time-tracker.com/compare.php?from=2de2edb943fe1b83d79bdffa03606eb8c5452e9b&to=8deb4f949b5f80a26a8a61775fb411bf30fefd80&stat=instructions%3Au
Assisted-by: codex
Commit: 54d5646b0d70e3a198817c61c40ba0226a66bf29
https://github.com/llvm/llvm-project/commit/54d5646b0d70e3a198817c61c40ba0226a66bf29
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/test/SemaCXX/attr-section.cpp
Log Message:
-----------
[Sema] Add original GH192264 reproducer as a section-conflict regression test (#202276)
Follow up of https://github.com/llvm/llvm-project/pull/200873
Commit: 8b0223858b1e15a4310de18445d972e7648b740f
https://github.com/llvm/llvm-project/commit/8b0223858b1e15a4310de18445d972e7648b740f
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
M clang/include/clang/Sema/SemaAMDGPU.h
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/test/CodeGen/amdgpu-builtin-is-invocable.c
M clang/test/CodeGen/amdgpu-builtin-processor-is.c
M clang/test/CodeGen/link-builtin-bitcode.c
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
A clang/test/CodeGenOpenCL/builtins-amdgcn-global-load-store.cl
A clang/test/SemaHIP/amdgpu-av-load-store.hip
A clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-error.cl
A clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-target-error.cl
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
Log Message:
-----------
[AMDGPU][Clang] add __builtin_amdgcn_av_(load|store)_b128 (#199176)
These builtins allow the program to request store-available and
load-visible accesses as described in #191246. Each of them takes a
__MEMORY_SCOPE_* operand that is then translated to target-specific
cache policy bits.
This patch was extracted from #172090.
Co-authored-by: macurtis-amd <macurtis at amd.com>
Assisted-by: Claude Opus 4.6
---------
Co-authored-by: macurtis-amd <macurtis at amd.com>
Commit: 88caf8ef2bd61005e854952b8a1e699aa72347d8
https://github.com/llvm/llvm-project/commit/88caf8ef2bd61005e854952b8a1e699aa72347d8
Author: Erik Enikeev <evonatarius at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
M llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
M llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll
M llvm/test/CodeGen/PowerPC/spe.ll
Log Message:
-----------
Reland "[PowerPC] set libcall lowering for fp setcc ops on SPE boards" (#199198)
This is a reland of 4d0100789dc9b4db7d77c033d8f53f8b7dc68437, which was
reverted by c24ab4c814f680c5ac71600bf80d551123abd84d.
The functionality is unchanged from the original patch. This version
only fixes the fast-math flag propagation issue by passing `SDNodeFlags`
explicitly to `DAG.getSetCC()` (same as #199105 which was closed because
the underlying patch had been reverted).
Commit: 59e1338da9e97be33e19dbe0b0cda46a9eefe834
https://github.com/llvm/llvm-project/commit/59e1338da9e97be33e19dbe0b0cda46a9eefe834
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Strip Ctx arg from tryToFoldLiveIns (NFC) (#202559)
We get the Plan anyway, so the context doesn't need to be passed
separately.
Commit: b1880a09469217aab192ded75643f860fb3d55a8
https://github.com/llvm/llvm-project/commit/b1880a09469217aab192ded75643f860fb3d55a8
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVBaseInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
A llvm/lib/Target/SPIRV/SPIRVAuxDataHandler.cpp
A llvm/lib/Target/SPIRV/SPIRVAuxDataHandler.h
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-all-function-attributes.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-all-function-metadata-debug.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-all-function-metadata.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-auxdata-requires-extension.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-auxdata.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-gv-attributes.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-gv-metadata.ll
A llvm/test/CodeGen/SPIRV/linkage/available-externally-function.ll
A llvm/test/CodeGen/SPIRV/linkage/available-externally-global.ll
M llvm/test/CodeGen/SPIRV/linkage/linkage-types.ll
Log Message:
-----------
[SPIR-V] Add NonSemantic.AuxData emission (-spirv-preserve-auxdata) (#200002)
Add a NonSemantic.AuxData extended instruction set to the SPIR-V
backend, matching SPIRV-LLVM-Translator's --spirv-preserve-auxdata wire
format
- `-spirv-preserve-auxdata` emits LLVM attributes and metadata as
NonSemantic.AuxData records (requires SPV_KHR_non_semantic_info).
- `available_externally` functions keep their linkage via an AuxData
linkage record, emitted unconditionally.
Commit: 97b131ec4a7e021c45586a37832d380c0c16ce1c
https://github.com/llvm/llvm-project/commit/97b131ec4a7e021c45586a37832d380c0c16ce1c
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
Log Message:
-----------
[AMDGPU][NFC] Add atomic optimization tests for gfx13 (#201299)
Commit: dae2935b32a673557e7060f8e90e73eaae4d6199
https://github.com/llvm/llvm-project/commit/dae2935b32a673557e7060f8e90e73eaae4d6199
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/memcpy.align.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/memmove.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll
Log Message:
-----------
[SPIR-V] Drop constant zero-sized memcpy/memmove/memset before selection (#201904)
A constant zero Size operand is invalid for OpCopyMemorySized, and these
intrinsics are no-ops, so erase them instead of lowering
Commit: 70b68dff845403f62d77f42850ac779a78662272
https://github.com/llvm/llvm-project/commit/70b68dff845403f62d77f42850ac779a78662272
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
Log Message:
-----------
[AMDGPU] Fix si-optimize-exec-masking stepping into debug values (#201947)
Summary:
This pass tries to step between register uses and would try to enter a
debug instruction if it managed to get between them.
Commit: 13b28db64845fc9fe7431338d5dc8919b28a6022
https://github.com/llvm/llvm-project/commit/13b28db64845fc9fe7431338d5dc8919b28a6022
Author: CarolineConcatto <caroline.concatto at arm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.td
M llvm/test/TableGen/target-mem-intrinsic-attrs.td
M llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
Log Message:
-----------
[TableGen] Add ArgMem memory location (#201597)
This will allow to use IntrRead/IntrWrite with ArgMem. So this:
```
[IntrWriteMem , IntrInaccessibleMemOrArgMemOnly]
```
could become this:
```
[IntrWriteMem, IntrWrite<[ArgMem, InaccessibleMem]>]
```
Commit: 53870f797be01f586078c1f129d05325c83a3143
https://github.com/llvm/llvm-project/commit/53870f797be01f586078c1f129d05325c83a3143
Author: Arnav Mundada <arnav.dev.mail at gmail.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libc/include/math.yaml
Log Message:
-----------
[libc][math] Add missing math function entries dfmal,dfmaf128 to math.yaml (#199485)
Part of https://github.com/llvm/llvm-project/issues/199266
Added missing math function entries to `libc/include/math.yaml`:
- dfmaf128
- dfmal
Commit: ee39c604feff48ce4b5396f8a7c51da86768479b
https://github.com/llvm/llvm-project/commit/ee39c604feff48ce4b5396f8a7c51da86768479b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/docs/Multilib.rst
M clang/docs/ReleaseNotes.rst
M clang/lib/Driver/ToolChains/MSVC.cpp
A clang/test/Driver/Inputs/multilib_msvc_tree/bin/.keep
A clang/test/Driver/Inputs/multilib_msvc_tree/include/x86_64-pc-windows-msvc/.keep
A clang/test/Driver/Inputs/multilib_msvc_tree/include/x86_64-pc-windows-msvc/debug/.keep
A clang/test/Driver/Inputs/multilib_msvc_tree/include/x86_64-pc-windows-msvc/noexcept/.keep
A clang/test/Driver/Inputs/multilib_msvc_tree/include/x86_64-pc-windows-msvc/release/.keep
A clang/test/Driver/msvc-multilib.yaml
M clang/test/Driver/print-multi-selection-flags.c
Log Message:
-----------
[Clang] Support multilibs on Windows (#200212)
Summary:
This was pushed to a follow-up, and I think the previous has lingered
long enough to expand this to Windows. the per-target runtime directory
this uses is default-off, but nothing stops us from just providing this.
The interest in this is for ROCm builds on Windows to be able to provide
asan / debug builds the same way on Linux.
Commit: 9c54c82d80271c326535f73064a8763d0c730a59
https://github.com/llvm/llvm-project/commit/9c54c82d80271c326535f73064a8763d0c730a59
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M lldb/docs/resources/lldbgdbremote.md
M lldb/include/lldb/Host/ProcessLaunchInfo.h
M lldb/include/lldb/Host/windows/PseudoConsole.h
M lldb/include/lldb/Utility/StringExtractorGDBRemote.h
M lldb/source/Host/common/ProcessLaunchInfo.cpp
M lldb/source/Host/windows/PseudoConsole.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.h
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Utility/StringExtractorGDBRemote.cpp
Log Message:
-----------
[lldb][gdb-remote] Forward client terminal size to lldb-server (#201141)
Add a new gdb-remote packet, `QSetSTDIOWindowSize:cols=N;rows=N`, to
send the dimension of the terminal to the debuggee.
On Windows, the ConPTY emulates a PTY. The client's terminal (the one
the user is running lldb from) has to match the dimensions of the ConPTY
so that the debuggee (which is attached to the ConPTY) gets proper
terminal emulation. If there is a mismatch, lines will not wrap at the
right column and VT sequences will be out of place. In practice, in
lldb, this results in the `(lldb)` prompt being overwritten by the
stdout of the debuggee.
This patch forwards the dimension of the client (the terminal lldb.exe
is running in) to the ConPTY (opened by the server) so that the
dimensions of the client's terminal match the ones of the ConPTY.
As an example, here is the opposite case where the terminal does not
have dimensions (the vscode debug console) and the ConPTY still has
finite dimensions: https://github.com/llvm/llvm-project/pull/186472.
This is a follow up to:
- https://github.com/llvm/llvm-project/pull/201124
Commit: 5ec036aba1243801320611f23f644707496e69c9
https://github.com/llvm/llvm-project/commit/5ec036aba1243801320611f23f644707496e69c9
Author: David Green <david.green at arm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/test/CodeGen/AArch64/ldst-opt-umov-fpr-store.mir
Log Message:
-----------
[AArch64] Protect against mismatching sizes in UMOV combine. (#202116)
This fixes an issue from #199139 where a later revision was not checking
the connection between the size of the UMOV and the size of the store.
This adds a check, based on the register sizes and the memory size from
the MMO.
Commit: 67e3b31450012b939980fc91075d0ab0b035f284
https://github.com/llvm/llvm-project/commit/67e3b31450012b939980fc91075d0ab0b035f284
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M compiler-rt/cmake/caches/AMDGPU.cmake
M compiler-rt/cmake/caches/NVPTX.cmake
M compiler-rt/cmake/caches/SPIRV64.cmake
Log Message:
-----------
[compiler-rt] Fix misspelled variable name in GPU caches (#202604)
Summary:
This likely didn't do anything, but it's best for things to be spelled
right.
Commit: 4662e7136d02accfeb11f5255eb1bcae10cff7ed
https://github.com/llvm/llvm-project/commit/4662e7136d02accfeb11f5255eb1bcae10cff7ed
Author: David Green <david.green at arm.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/ldexp.ll
Log Message:
-----------
[AArch64][GlobalISel] BF16 libcalls operations. (#200740)
This fills in a number of bf16 instructions that lower through f32
libcall.
Commit: 85d4138c12cd1eae0eb7083279ca7b0b26cd15b1
https://github.com/llvm/llvm-project/commit/85d4138c12cd1eae0eb7083279ca7b0b26cd15b1
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libsycl/CMakeLists.txt
A libsycl/cmake/Modules/AddUnitTest.cmake
M libsycl/docs/index.rst
M libsycl/src/CMakeLists.txt
M libsycl/src/detail/device_kernel_info.hpp
M libsycl/src/detail/program_manager.cpp
M libsycl/src/detail/program_manager.hpp
A libsycl/unittests/CMakeLists.txt
A libsycl/unittests/common/device_images.hpp
A libsycl/unittests/mock/CMakeLists.txt
A libsycl/unittests/mock/helpers.cpp
A libsycl/unittests/mock/helpers.hpp
A libsycl/unittests/mock/mock.cpp
A libsycl/unittests/platform/CMakeLists.txt
A libsycl/unittests/platform/get_platforms.cpp
A libsycl/unittests/program_manager/CMakeLists.txt
A libsycl/unittests/program_manager/register_and_unregister.cpp
A libsycl/unittests/queue/CMakeLists.txt
A libsycl/unittests/queue/queue.cpp
Log Message:
-----------
[libsycl] Add UT build and min test set (#199915)
This PR was assisted by GH Copilot (replication of base mock functions
according to my example, fake device image helpers).
---------
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: cbfe4adc92bc0c9680285e9a47201f0ff68c9b66
https://github.com/llvm/llvm-project/commit/cbfe4adc92bc0c9680285e9a47201f0ff68c9b66
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/test/CodeGen/SPIRV/pointers/getelementptr-empty-struct.ll
Log Message:
-----------
[SPIR-V] Fix infinite loop on GEP handling for an empty struct (#202587)
Commit: 431a821cbbb66f89d0cd7d97c6eb7792801fd90e
https://github.com/llvm/llvm-project/commit/431a821cbbb66f89d0cd7d97c6eb7792801fd90e
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/logical-memcpy.inline.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/memcpy.inline.ll
Log Message:
-----------
[SPIRV] Add support for selection of G_MEMCPY_INLINE (#201925)
`G_MEMCPY_INLINE` is the same as `G_MEMCPY` but it's supposed to
guarantee the instruction will not be lowered to an external function
call. This is useful for projects like `libc`.
In SPIR-V, we would never lower to an external function call, we always
lower `G_MEMCPY` to `OpCopyMemory` or `OpCopyMemorySized`, or the copy
is optimized out, so we should be able to handle `G_MEMCPY_INLINE` and
`G_MEMCPY` the same.
Co-Authored-By: Claude Opus 4.8
[noreply at anthropic.com](mailto:noreply at anthropic.com)
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Co-authored-by: Claude Opus 4.8 <noreply at anthropic.com>
Commit: 3f28ade7a938f410baa061c4fe0c69a98dd58281
https://github.com/llvm/llvm-project/commit/3f28ade7a938f410baa061c4fe0c69a98dd58281
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/SPIRV/concat-vectors.ll
Log Message:
-----------
[SPIRV] Support selection of G_CONCAT_VECTORS (#201686)
Implement the G_CONCAT_VECTOR opcode using `OpCompositeConstruct`. The
semantics are similar so the implementation is straightforward.
This opcode being generated is somewhat rare, in this case it seems to
have remained due to the non-power of 2 vector length ABI.
Co-Authored-By: Claude Opus 4.8 <noreply at anthropic.com>
Co-authored-by: Claude Opus 4.8 <noreply at anthropic.com>
Commit: 45f6ab064f881334affa6ff5e3b3cb056cde67cb
https://github.com/llvm/llvm-project/commit/45f6ab064f881334affa6ff5e3b3cb056cde67cb
Author: Sergey Semenov <sergey.semenov at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M libsycl/src/detail/program_manager.cpp
Log Message:
-----------
[libsycl] Fix _LIBSYCL_EXPORT placement (#201364)
Fixes another instance of _LIBSYCL_EXPORT causing compiilation errors on
Windows.
Commit: 4d7ba1f5ef6402183372e2ea6358c53a9c182868
https://github.com/llvm/llvm-project/commit/4d7ba1f5ef6402183372e2ea6358c53a9c182868
Author: Drew Kersnar <dkersnar at nvidia.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/IR/Instructions.cpp
M llvm/test/Transforms/InstCombine/addrspacecast.ll
Log Message:
-----------
[IR] Preserve pointer-byte bitcasts around addrspacecast (#202454)
This fixes cast-pair elimination for addrspacecast combined with
pointer/byte bitcast.
The LLVM LangRef defines [bN byte
types](https://llvm.org/docs/LangRef.html#byte-type) as raw memory data
in SSA registers, where each bit may be an integer bit, part of a
pointer value, or poison.
The LangRef permits pointer-to-byte bitcast: the [bitcast .. to
instruction](https://llvm.org/docs/LangRef.html#bitcast-to-instruction)
says that if the source type is a pointer, the destination type must be
a pointer or a byte/vector-of-bytes type of the same size.
The same [bitcast .. to
section](https://llvm.org/docs/LangRef.html#bitcast-to-instruction) also
defines byte-to-pointer behavior: when the destination type is a pointer
type, a byte value whose bits all come from the same correctly ordered
pointer produces that pointer; otherwise it produces a pointer with the
address encoded by the input and no provenance.
By contrast, [addrspacecast ..
to](https://llvm.org/docs/LangRef.html#addrspacecast-to-instruction) is
only valid from a pointer or vector-of-pointers value to a pointer type
in a different address space.
So these two-step sequences are valid:
```
%p = addrspacecast ptr addrspace(1) %x to ptr
%b = bitcast ptr %p to b64
```
```
%p = bitcast b64 %x to ptr
%q = addrspacecast ptr %p to ptr addrspace(1)
```
But they cannot be folded into a single addrspacecast, because that
would require addrspacecast to cast directly to or from bN, which the
LangRef does not allow.
This patch prevents cast-pair elimination from performing those invalid
folds and adds InstCombine regression coverage for both directions. Both
tests crashed before this patch. This patch was created with the
assistance of AI, based on a real case I found while working on
https://github.com/llvm/llvm-project/pull/177908. I'm pretty sure I'm
reading the langref correctly, but please let me know if I am mistaken.
Commit: 26c72f1b4d375a7dc93df4435b012c221f4ae902
https://github.com/llvm/llvm-project/commit/26c72f1b4d375a7dc93df4435b012c221f4ae902
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for tensor load/store to lds (#202363)
Commit: 727ad9a21d32f19dd0fdf26b39a9c6a064692287
https://github.com/llvm/llvm-project/commit/727ad9a21d32f19dd0fdf26b39a9c6a064692287
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[AMDGPU] Add a feature for VOP3PX2 instructions incrementing VA_VDST twice (#202613)
Commit: 1723b7a301450d7000fe3a86e48adb9f9794d1e9
https://github.com/llvm/llvm-project/commit/1723b7a301450d7000fe3a86e48adb9f9794d1e9
Author: Srividya Sundaram <srividya.sundaram at intel.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/Frontend/CompilerInvocation.cpp
R clang/test/CodeGenSYCL/filescope_asm.c
A clang/test/CodeGenSYCL/filescope_asm.cpp
M clang/test/Driver/offload-target.c
M clang/test/Driver/sycl.cpp
A clang/test/Frontend/sycl-c-input-error.cpp
M clang/test/Headers/__cpuidex_conflict.c
M clang/test/SemaSPIRV/BuiltIns/generic_cast_to_ptr_explicit.c
M clang/test/SemaSPIRV/BuiltIns/ids_and_ranges.c
M clang/test/SemaSPIRV/BuiltIns/subgroup-errors.c
M clang/unittests/Frontend/CompilerInvocationTest.cpp
Log Message:
-----------
[SYCL] Error on C inputs when compiling with -fsycl (#200318)
`SYCL` is a `C++`-based programming model and requires `C++` source
files.
Enforce this invariant in the frontend by rejecting `C` inputs when SYCL
mode is active, ensuring that `LangOpts.SYCL` implies
`LangOpts.CPlusPlus` regardless of how the compiler is invoked.
Commit: 6c706ed5896d10b2a900d5860b80851f01cfe943
https://github.com/llvm/llvm-project/commit/6c706ed5896d10b2a900d5860b80851f01cfe943
Author: xys-syx <xuyuansui at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Dialect/LLVMIR/nvvm.mlir
M mlir/test/Target/LLVMIR/nvvm/barrier.mlir
Log Message:
-----------
[MLIR][NVVM] Add explicit aligned attribute to nvvm.barrier and nvvm.barrier.reduction (#200745)
This PR according to the third PR commitments in #192203
This PR adds an explicit aligned boolean attribute to `nvvm.barrier`,
defaulting to true to preserve the existing semantic default, and
extends the op's LLVM IR lowering to pick between the `.aligned` and
non-`.aligned` spellings of the `@llvm.nvvm.barrier.cta.*` intrinsic
family.
Notes on using `BoolAttr` instead of UnitAttr: `nvvm.barrier`'s existing
lowering always emits an aligned intrinsic variant. Making aligned a
BoolAttr with default true captures that as the op's default, and the
`custom<Aligned>` described below only emits the keyword when
non-default.
(I am not able to merge branches, please help me)
Commit: 859ee9d83ef227848a98c5948f887574f5e7420c
https://github.com/llvm/llvm-project/commit/859ee9d83ef227848a98c5948f887574f5e7420c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.h
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
M clang/lib/Driver/ToolChains/HIPSPV.cpp
M clang/lib/Driver/ToolChains/HIPSPV.h
M clang/test/Driver/amdgpu-openmp-sanitize-options.c
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/hip-binding.hip
M clang/test/Driver/hip-device-compile.hip
M clang/test/Driver/hip-offload-compress-zlib.hip
M clang/test/Driver/hip-offload-compress-zstd.hip
M clang/test/Driver/hip-phases.hip
M clang/test/Driver/hip-rdc-device-only.hip
M clang/test/Driver/hip-sanitize-options.hip
M clang/test/Driver/hip-save-temps.hip
M clang/test/Driver/hip-spirv-backend-bindings.c
M clang/test/Driver/hip-spirv-backend-opt.c
M clang/test/Driver/hip-spirv-backend-phases.c
M clang/test/Driver/hip-spirv-linker-crash.c
M clang/test/Driver/hip-target-id.hip
M clang/test/Driver/hip-toolchain-device-only.hip
M clang/test/Driver/hip-toolchain-no-rdc.hip
M clang/test/Driver/hip-toolchain-rdc-flto-partitions.hip
M clang/test/Driver/hip-toolchain-rdc-separate.hip
M clang/test/Driver/hip-toolchain-rdc-static-lib.hip
M clang/test/Driver/hip-toolchain-rdc.hip
M clang/test/Driver/hip-unbundle-preproc.hipi
M clang/test/Driver/hipspv-toolchain-rdc-separate.hip
M clang/test/Driver/hipspv-toolchain-rdc.hip
M clang/test/Driver/hipspv-toolchain.hip
M clang/test/Driver/openmp-offload-gpu.c
M clang/test/Driver/spirv-amd-toolchain.c
M clang/test/Driver/spirv-openmp-toolchain.c
Log Message:
-----------
[Clang] Set default LTO mode for AMDGCN/SPIR-V targets to full (#201457)
Summary:
Previously we had several layers of if conditions that functionally
amounted to pretending like we were in LTO-mode. The previous changes
moved the LTO settings into the toolchain so we can now override it for
our offloading toolchains. This allows us to respect the LTO mode, where
previously there was no way to override it.
The main artifact of this PR should be trimming up the massive if
statement.
Some slight by-products on the old-driver path, but this can be
recovered with `-fno-offload-lto` and the old driver should be deleted
in a few months anyways.
Commit: f8b0120edb7f19b30870462299e5f7eb0e40f656
https://github.com/llvm/llvm-project/commit/f8b0120edb7f19b30870462299e5f7eb0e40f656
Author: Rose Hudson <rose.hudson at sony.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/lib/Driver/ToolChains/PS4CPU.h
M clang/test/Driver/ps4-ps5-toolchain.c
Log Message:
-----------
[Clang][Driver] default-on include path backslash warning on PS5 (#202300)
It seems like there is precedent for using addClangWarningOptions in the
driver to set warning default states per-target, in e.g. AMDGPU.
These warnings are usually disabled by default to avoid overdiagnosing
common patterns on Windows host+target builds which don't care about
portability. Since PS5 builds are cross-compiled it makes less sense to
assume things about the host, so we want to diagnose portability issues
more eagerly.
Commit: 8a8fc9ca733d5024fd2c8fc9105750d1ddc53b4f
https://github.com/llvm/llvm-project/commit/8a8fc9ca733d5024fd2c8fc9105750d1ddc53b4f
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-06-09 (Tue, 09 Jun 2026)
Changed paths:
M .ci/compute_projects.py
M clang-tools-extra/clangd/CompileCommands.cpp
M clang-tools-extra/clangd/unittests/CompileCommandsTests.cpp
M clang/docs/LanguageExtensions.rst
M clang/docs/Multilib.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/SafeStack.rst
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Sema/SemaAMDGPU.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Context.h
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/Function.h
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpFrame.cpp
M clang/lib/AST/ByteCode/InterpFrame.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CodeGen/CGCoroutine.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.h
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.h
M clang/lib/Driver/ToolChains/HIPSPV.cpp
M clang/lib/Driver/ToolChains/HIPSPV.h
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/lib/Driver/ToolChains/PS4CPU.h
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Headers/__clang_hip_runtime_wrapper.h
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/AST/ByteCode/codegen.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ByteCode/intap.cpp
M clang/test/AST/ByteCode/unions.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGen/amdgpu-builtin-is-invocable.c
M clang/test/CodeGen/amdgpu-builtin-processor-is.c
M clang/test/CodeGen/link-builtin-bitcode.c
M clang/test/CodeGen/target-builtin-noerror.c
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
A clang/test/CodeGenCoroutines/coro-cwg2935.cpp
M clang/test/CodeGenHLSL/ArrayAssignable.hlsl
M clang/test/CodeGenHLSL/ArrayAssignable.logicalptr.hlsl
M clang/test/CodeGenHLSL/cbuffer-matrix-layout-keyword.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer-empty-struct-array.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_and_namespaces.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_with_packoffset.hlsl
M clang/test/CodeGenHLSL/resources/cbuffer_with_static_global_and_function.hlsl
M clang/test/CodeGenHLSL/resources/default_cbuffer.hlsl
M clang/test/CodeGenHLSL/resources/default_cbuffer_with_layout.hlsl
A clang/test/CodeGenOpenCL/builtins-amdgcn-global-load-store.cl
R clang/test/CodeGenSYCL/filescope_asm.c
A clang/test/CodeGenSYCL/filescope_asm.cpp
A clang/test/Driver/Inputs/multilib_msvc_tree/bin/.keep
A clang/test/Driver/Inputs/multilib_msvc_tree/include/x86_64-pc-windows-msvc/.keep
A clang/test/Driver/Inputs/multilib_msvc_tree/include/x86_64-pc-windows-msvc/debug/.keep
A clang/test/Driver/Inputs/multilib_msvc_tree/include/x86_64-pc-windows-msvc/noexcept/.keep
A clang/test/Driver/Inputs/multilib_msvc_tree/include/x86_64-pc-windows-msvc/release/.keep
M clang/test/Driver/amdgpu-openmp-sanitize-options.c
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/hip-binding.hip
M clang/test/Driver/hip-device-compile.hip
M clang/test/Driver/hip-offload-compress-zlib.hip
M clang/test/Driver/hip-offload-compress-zstd.hip
M clang/test/Driver/hip-phases.hip
M clang/test/Driver/hip-rdc-device-only.hip
M clang/test/Driver/hip-sanitize-options.hip
M clang/test/Driver/hip-save-temps.hip
M clang/test/Driver/hip-spirv-backend-bindings.c
M clang/test/Driver/hip-spirv-backend-opt.c
M clang/test/Driver/hip-spirv-backend-phases.c
M clang/test/Driver/hip-spirv-linker-crash.c
M clang/test/Driver/hip-target-id.hip
M clang/test/Driver/hip-toolchain-device-only.hip
M clang/test/Driver/hip-toolchain-no-rdc.hip
M clang/test/Driver/hip-toolchain-rdc-flto-partitions.hip
M clang/test/Driver/hip-toolchain-rdc-separate.hip
M clang/test/Driver/hip-toolchain-rdc-static-lib.hip
M clang/test/Driver/hip-toolchain-rdc.hip
M clang/test/Driver/hip-unbundle-preproc.hipi
M clang/test/Driver/hipspv-toolchain-rdc-separate.hip
M clang/test/Driver/hipspv-toolchain-rdc.hip
M clang/test/Driver/hipspv-toolchain.hip
A clang/test/Driver/msvc-multilib.yaml
M clang/test/Driver/offload-target.c
M clang/test/Driver/openmp-offload-gpu.c
M clang/test/Driver/print-multi-selection-flags.c
M clang/test/Driver/ps4-ps5-toolchain.c
M clang/test/Driver/spirv-amd-toolchain.c
M clang/test/Driver/spirv-openmp-toolchain.c
M clang/test/Driver/sycl.cpp
M clang/test/Driver/x86-march.c
A clang/test/Frontend/sycl-c-input-error.cpp
M clang/test/Frontend/x86-target-cpu.c
M clang/test/Headers/__cpuidex_conflict.c
A clang/test/Headers/hip-constexpr-cmath.hip
M clang/test/Misc/target-invalid-cpu-note/x86.c
M clang/test/Preprocessor/predefined-arch-macros.c
A clang/test/Sema/safestack-deprecated-builtins.c
M clang/test/SemaCXX/attr-section.cpp
A clang/test/SemaHIP/amdgpu-av-load-store.hip
A clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-error.cl
A clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-target-error.cl
M clang/test/SemaSPIRV/BuiltIns/generic_cast_to_ptr_explicit.c
M clang/test/SemaSPIRV/BuiltIns/ids_and_ranges.c
M clang/test/SemaSPIRV/BuiltIns/subgroup-errors.c
M clang/unittests/Frontend/CompilerInvocationTest.cpp
M compiler-rt/cmake/caches/AMDGPU.cmake
M compiler-rt/cmake/caches/NVPTX.cmake
M compiler-rt/cmake/caches/SPIRV64.cmake
M compiler-rt/include/CMakeLists.txt
A compiler-rt/include/sanitizer/safestack_interface.h
M compiler-rt/lib/builtins/cpu_model/x86.c
M compiler-rt/lib/safestack/CMakeLists.txt
M compiler-rt/lib/safestack/safestack.cpp
M compiler-rt/test/builtins/Unit/lit.cfg.py
M compiler-rt/test/safestack/sigaltstack.c
M libc/include/math.yaml
M libcxx/include/CMakeLists.txt
M libcxx/include/__bit_reference
M libcxx/include/__format/range_formatter.h
R libcxx/include/__type_traits/dependent_type.h
M libcxx/include/module.modulemap.in
M libcxx/include/variant
A libcxx/test/libcxx/containers/sequences/vector.bool/nodiscard.iterator.verify.cpp
A libcxx/test/libcxx/containers/sequences/vector/nodiscard.iterator.verify.cpp
M libcxx/test/std/utilities/format/format.range/format.range.fmtset/format.functions.tests.h
M libcxx/test/std/utilities/format/format.range/format.range.formatter/format.functions.tests.h
M libsycl/CMakeLists.txt
A libsycl/cmake/Modules/AddUnitTest.cmake
M libsycl/docs/index.rst
M libsycl/src/CMakeLists.txt
M libsycl/src/detail/device_kernel_info.hpp
M libsycl/src/detail/program_manager.cpp
M libsycl/src/detail/program_manager.hpp
A libsycl/unittests/CMakeLists.txt
A libsycl/unittests/common/device_images.hpp
A libsycl/unittests/mock/CMakeLists.txt
A libsycl/unittests/mock/helpers.cpp
A libsycl/unittests/mock/helpers.hpp
A libsycl/unittests/mock/mock.cpp
A libsycl/unittests/platform/CMakeLists.txt
A libsycl/unittests/platform/get_platforms.cpp
A libsycl/unittests/program_manager/CMakeLists.txt
A libsycl/unittests/program_manager/register_and_unregister.cpp
A libsycl/unittests/queue/CMakeLists.txt
A libsycl/unittests/queue/queue.cpp
M lldb/docs/resources/lldbgdbremote.md
M lldb/include/lldb/Host/ProcessLaunchInfo.h
M lldb/include/lldb/Host/windows/PseudoConsole.h
M lldb/include/lldb/Utility/StringExtractorGDBRemote.h
M lldb/source/Host/common/ProcessLaunchInfo.cpp
M lldb/source/Host/windows/PseudoConsole.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.h
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Utility/StringExtractorGDBRemote.cpp
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/ProgrammersManual.rst
M llvm/include/llvm/ADT/StringMap.h
M llvm/include/llvm/Analysis/Loads.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/Frontend/HLSL/CBuffer.h
M llvm/include/llvm/IR/BundleAttributes.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/TargetParser/Host.h
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/TargetParser/X86TargetParser.h
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/MemDerefPrinter.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
M llvm/lib/CodeGen/MachineOperand.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Frontend/HLSL/CBuffer.cpp
M llvm/lib/IR/BundleAttributes.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Support/StringMap.cpp
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
M llvm/lib/Target/DirectX/DXILCBufferAccess.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVBaseInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
A llvm/lib/Target/SPIRV/SPIRVAuxDataHandler.cpp
A llvm/lib/Target/SPIRV/SPIRVAuxDataHandler.h
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCBufferAccess.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
M llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/X86/X86.td
A llvm/lib/Target/X86/X86ScheduleC864GM4.td
A llvm/lib/Target/X86/X86ScheduleC864GM7.td
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
M llvm/lib/Transforms/IPO/StripSymbols.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/Scalar/AlignmentFromAssumptions.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Analysis/LoopAccessAnalysis/early-exit-runtime-checks.ll
M llvm/test/Analysis/ValueTracking/assume.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-and.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/GlobalISel/opt-overlapping-and-postlegalize.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combine-ptr-add-chain.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-hoist-same-hands.mir
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/ldexp.ll
M llvm/test/CodeGen/AArch64/ldst-opt-umov-fpr-store.mir
A llvm/test/CodeGen/AArch64/sve-multivector-fold-imms.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
R llvm/test/CodeGen/DirectX/cbuffer_global_elim.ll
M llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
M llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
M llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll
M llvm/test/CodeGen/PowerPC/spe.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
R llvm/test/CodeGen/SPIRV/cbuffer_global_elim.ll
A llvm/test/CodeGen/SPIRV/concat-vectors.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-all-function-attributes.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-all-function-metadata-debug.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-all-function-metadata.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-auxdata-requires-extension.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-auxdata.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-gv-attributes.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-gv-metadata.ll
A llvm/test/CodeGen/SPIRV/linkage/available-externally-function.ll
A llvm/test/CodeGen/SPIRV/linkage/available-externally-global.ll
M llvm/test/CodeGen/SPIRV/linkage/linkage-types.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/logical-memcpy.inline.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/memcpy.align.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/memcpy.inline.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/memmove.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll
A llvm/test/CodeGen/SPIRV/pointers/getelementptr-empty-struct.ll
M llvm/test/CodeGen/X86/bypass-slow-division-64.ll
M llvm/test/CodeGen/X86/cmp16.ll
A llvm/test/CodeGen/X86/cpus-hygon.ll
M llvm/test/CodeGen/X86/rdpru.ll
M llvm/test/CodeGen/X86/slow-unaligned-mem.ll
M llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
M llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll
M llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
M llvm/test/MC/X86/x86_long_nop.s
M llvm/test/TableGen/target-mem-intrinsic-attrs.td
M llvm/test/Transforms/AlignmentFromAssumptions/simple.ll
A llvm/test/Transforms/IndVarSimplify/exit-value-safe-udiv.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
M llvm/test/Transforms/InstCombine/addrspacecast.ll
M llvm/test/Transforms/InstCombine/assume.ll
A llvm/test/Transforms/InstCombine/issue173148-sext-phi-select-infloop.ll
M llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
M llvm/test/Transforms/InstSimplify/bitcast-vector-fold.ll
M llvm/test/Transforms/LICM/hoist-deref-load.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-step.ll
M llvm/test/Transforms/LoopVectorize/early-exit-calls.ll
M llvm/test/Transforms/LoopVectorize/expand-scev-after-invoke.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleave-with-i65-induction.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/nested-loops-scev-expansion.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/masked-loads-side-effects-after-vec.ll
M llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-vectorized-later.ll
M llvm/test/Verifier/assume-bundles.ll
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-adx.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-aes.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-avx1.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-avx2.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-bmi1.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-bmi2.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-clflushopt.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-clzero.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-cmov.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-cmpxchg.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-f16c.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-fma.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-fsgsbase.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-lea.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-lzcnt.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-mmx.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-movbe.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-mwaitx.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-pclmul.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-popcnt.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-prefetchw.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-rdrand.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-rdseed.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sha.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse1.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse2.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse3.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse41.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse42.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse4a.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-ssse3.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-x86_32.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-x86_64.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-x87.s
A llvm/test/tools/llvm-mca/X86/C864GM4/resources-xsave.s
A llvm/test/tools/llvm-mca/X86/C864GM4/zero-idioms.s
A llvm/test/tools/llvm-mca/X86/C864GM7/independent-load-stores.s
A llvm/test/tools/llvm-mca/X86/C864GM7/partially-overlapping-group-resources.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-adx.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-aes.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx1.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx2.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bitalg.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bitalgvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bw.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bwvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512cd.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512cdvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512dq.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512dqvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512gfni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512gfnivl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512ifma.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512ifmavl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vaes.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vaesvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi2.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi2vl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmivl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vnni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vnnivl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vp2intersect.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vp2intersectvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpclmulqdq.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpclmulqdqvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpopcntdq.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpopcntdqvl.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avxgfni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-avxvnni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-bmi1.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-bmi2.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-clflushopt.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-clwb.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-cmov.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-cmpxchg.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-f16c.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-fma.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-fsgsbase.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-gfni.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-lea.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-lzcnt.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-mmx.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-movbe.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-mwaitx.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-pclmul.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-popcnt.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-prefetchw.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-rdrand.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-rdseed.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sha.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse1.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse2.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse3.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse41.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse42.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse4a.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-ssse3.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-vaes.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-vpclmulqdq.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-x86_32.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-x86_64.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-x87.s
A llvm/test/tools/llvm-mca/X86/C864GM7/resources-xsave.s
A llvm/test/tools/llvm-mca/X86/C864GM7/zero-idioms.s
M llvm/tools/llvm-exegesis/lib/Assembler.h
M llvm/unittests/ADT/StringMapTest.cpp
M llvm/unittests/Support/DynamicLibrary/DynamicLibraryTest.cpp
M llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
M llvm/utils/gdb-scripts/prettyprinters.py
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationTypeInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgEnums.td
A mlir/include/mlir/Dialect/SPIRV/IR/SPIRVExperimentalMLOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.td
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
M mlir/lib/Conversion/MemRefToSPIRV/MemRefToSPIRV.cpp
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/lib/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationDialect.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/test/Conversion/MemRefToSPIRV/atomic.mlir
M mlir/test/Conversion/SPIRVToLLVM/cast-ops-to-llvm.mlir
A mlir/test/Conversion/SPIRVToLLVM/cl-ops-to-llvm.mlir
M mlir/test/Conversion/SPIRVToLLVM/gl-ops-to-llvm.mlir
M mlir/test/Conversion/SPIRVToLLVM/logical-ops-to-llvm.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-bufferize.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-non-module-bufferize.mlir
A mlir/test/Dialect/Bufferization/Transforms/test-one-shot-module-bufferize.mlir
M mlir/test/Dialect/LLVMIR/nvvm.mlir
M mlir/test/Dialect/Linalg/roundtrip-morphism-linalg-category-ops.mlir
M mlir/test/Dialect/Linalg/specialize-generic-ops.mlir
M mlir/test/Dialect/NVGPU/invalid.mlir
A mlir/test/Dialect/SPIRV/IR/experimental-ml-ops.mlir
M mlir/test/Target/LLVMIR/nvvm/barrier.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp4x2.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp6x2.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp8x2.mlir
M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
A mlir/test/Target/SPIRV/experimental-ml-ops.mlir
M mlir/test/lib/Dialect/Bufferization/TestOneShotModuleBufferize.cpp
M mlir/test/lib/Dialect/Bufferization/TestTensorCopyInsertion.cpp
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestTypeDefs.td
M mlir/test/lib/Dialect/Test/TestTypes.cpp
M offload/plugins-nextgen/level_zero/src/L0Queue.cpp
Log Message:
-----------
rebase
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/8dce969b0ff0...8a8fc9ca733d
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