[all-commits] [llvm/llvm-project] 13b28d: [TableGen] Add ArgMem memory location (#201597)

[CarolineConcatto via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 13b28db64845fc9fe7431338d5dc8919b28a6022
      https://github.com/llvm/llvm-project/commit/13b28db64845fc9fe7431338d5dc8919b28a6022
  Author: CarolineConcatto <caroline.concatto at arm.com>
  Date:   2026-06-09 (Tue, 09 Jun 2026)

  Changed paths:
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/test/TableGen/target-mem-intrinsic-attrs.td
    M llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp

  Log Message:
  -----------
  [TableGen] Add ArgMem memory location (#201597)

This will allow to use IntrRead/IntrWrite with ArgMem. So this:
```
[IntrWriteMem , IntrInaccessibleMemOrArgMemOnly]
```
could become this:
```
[IntrWriteMem, IntrWrite<[ArgMem, InaccessibleMem]>] 
```



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