[all-commits] [llvm/llvm-project] f7fc4d: [LoongArch] Add DAG combine for widening shift-left

[hev via All-commits]

  Branch: refs/heads/users/hev/vsllwil
  Home:   https://github.com/llvm/llvm-project
  Commit: f7fc4d91f03a4a23e8049ebff87557fea52f07f8
      https://github.com/llvm/llvm-project/commit/f7fc4d91f03a4a23e8049ebff87557fea52f07f8
  Author: WANG Rui <wangrui at loongson.cn>
  Date:   2026-06-09 (Tue, 09 Jun 2026)

  Changed paths:
    M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
    M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
    M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
    M llvm/test/CodeGen/LoongArch/lasx/vsllwil.ll
    M llvm/test/CodeGen/LoongArch/lsx/vsllwil.ll

  Log Message:
  -----------
  [LoongArch] Add DAG combine for widening shift-left

Add DAG combines to recognize vector widening left-shift idioms and
lower them to VSLLWIL instructions.

The following pattern is matched for both signed and unsigned variants:

```
  SEXT/ZEXT(Low-Half-Lanes(vec)) << Imm
```

This covers the following instructions:

```
  LSX:  VSLLWIL.H.B, VSLLWIL.W.H, VSLLWIL.D.W
        VSLLWIL.HU.BU, VSLLWIL.WU.HU, VSLLWIL.DU.WU

  LASX: XVSLLWIL.H.B, XVSLLWIL.W.H, XVSLLWIL.D.W
        XVSLLWIL.HU.BU, XVSLLWIL.WU.HU, XVSLLWIL.DU.WU
```



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