[all-commits] [llvm/llvm-project] ed352e: [RFC][AMDGPU] Add BARRIER address space

[Pierre van Houtryve via All-commits]

  Branch: refs/heads/users/pierre-vh/barrier-as-impl
  Home:   https://github.com/llvm/llvm-project
  Commit: ed352e24756741486b932cbc0a9537e02dcb55ee
      https://github.com/llvm/llvm-project/commit/ed352e24756741486b932cbc0a9537e02dcb55ee
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2026-06-09 (Tue, 09 Jun 2026)

  Changed paths:
    M clang/lib/CodeGen/Targets/AMDGPU.cpp
    M clang/test/CodeGen/target-data.c
    M clang/test/CodeGenHIP/amdgpu-barrier-type.hip
    M clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl
    M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
    M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
    M lld/test/ELF/lto/amdgcn-oses.ll
    M lld/test/ELF/lto/amdgcn.ll
    M llvm/docs/AMDGPUUsage.rst
    M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
    M llvm/include/llvm/Support/AMDGPUAddrSpace.h
    M llvm/lib/Target/AMDGPU/AMDGPU.h
    M llvm/lib/Target/AMDGPU/AMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULowerExecSync.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.h
    M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
    M llvm/lib/Target/AMDGPU/SIDefines.h
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/lib/TargetParser/TargetDataLayout.cpp
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll
    A llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-module-lds.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync-and-sw-lds.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-lower-exec-sync.ll
    M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
    M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
    M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
    M llvm/test/CodeGen/AMDGPU/attributor-noalias-addrspace.ll
    A llvm/test/CodeGen/AMDGPU/barrier-addrspace-dereference.ll
    M llvm/test/CodeGen/AMDGPU/lds-link-time-codegen-named-barrier.ll
    M llvm/test/CodeGen/AMDGPU/lds-link-time-named-barrier.ll
    A llvm/test/CodeGen/AMDGPU/null-named-barrier-gv.ll
    A llvm/test/CodeGen/AMDGPU/s-barrier-lowering-bad-absolute-symbol.ll
    A llvm/test/CodeGen/AMDGPU/s-barrier-lowering-wrong-gv-signature.ll
    M llvm/test/CodeGen/AMDGPU/s-barrier-lowering.ll
    M llvm/test/CodeGen/AMDGPU/s-barrier.ll
    M llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
    M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
    M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
    M mlir/test/Dialect/LLVMIR/rocdl.mlir
    M mlir/test/Target/LLVMIR/rocdl.mlir

  Log Message:
  -----------
  [RFC][AMDGPU] Add BARRIER address space

Add a new BARRIER address space that is used for global variables that are used to represent the barrier IDs in GFX12.5.

These barrier addresses just have values corresponding 1-1 to barrier IDs. They are still implemented on top of LDS, but the offsetting happens during an addrspacecast to generic, not whenever the barrier GV is used.

The motivation for this is to make the relation between LDS and barrier GVs explicit in the compiler. It does add a bit more complexity, but that complexity was already there, just hidden by pretending barrier GVs were actual LDS.


  Commit: 05de6ce293023d0af5a1dda729ea9d78660a2f98
      https://github.com/llvm/llvm-project/commit/05de6ce293023d0af5a1dda729ea9d78660a2f98
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2026-06-09 (Tue, 09 Jun 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/s-barrier-id-allocation.ll
    M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
    M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
    M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
    M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-barriers-gfx12.mlir

  Log Message:
  -----------
  Fix MLIR


  Commit: 1b819ad253ca67b34ea12b26676668961c269d6f
      https://github.com/llvm/llvm-project/commit/1b819ad253ca67b34ea12b26676668961c269d6f
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2026-06-09 (Tue, 09 Jun 2026)

  Changed paths:
    M llvm/docs/AMDGPUUsage.rst
    M llvm/include/llvm/Support/AMDGPUAddrSpace.h

  Log Message:
  -----------
  Fix docs


  Commit: b942ed2aa1945e9ec66fbc6628e113622d83a07c
      https://github.com/llvm/llvm-project/commit/b942ed2aa1945e9ec66fbc6628e113622d83a07c
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2026-06-09 (Tue, 09 Jun 2026)

  Changed paths:
    M llvm/docs/AMDGPUUsage.rst
    M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td

  Log Message:
  -----------
  Address comments, fix rebase


Compare: https://github.com/llvm/llvm-project/compare/f1b20c7fc606...b942ed2aa194

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