[all-commits] [llvm/llvm-project] 1ad448: [InstCombine] Don't reuse a sibling binop with ext...

[lijinpei-amd via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1ad448f48b3ea8c79e3246dff691d41449db562d
      https://github.com/llvm/llvm-project/commit/1ad448f48b3ea8c79e3246dff691d41449db562d
  Author: lijinpei-amd <jinpli at amd.com>
  Date:   2026-06-09 (Tue, 09 Jun 2026)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    M llvm/test/Transforms/InstCombine/vec_demanded_elts.ll

  Log Message:
  -----------
  [InstCombine] Don't reuse a sibling binop with extra flags via demanded elts (#199782) (#201545)

SimplifyDemandedVectorElts can replace a vector binop with a sibling
binop. But if the sibling carries a flag the original lacked, it could
produce a result the original never would. E.g.

  Reusing `sub nuw`   could make the result poison on wrap.
  Reusing `fmul nsz`  could flip the sign of a zero.
  Reusing `fdiv arcp` could make the result less accurate.

Fix by only reusing the sibling when its flags are a subset of the
replaced binop's.

https://alive2.llvm.org/ce/z/9yEaG7
Fixes #199782.



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