[all-commits] [llvm/llvm-project] 7556cf: [MLIR][XeGPU] Support transposed load_nd of sub-32...

[Sang Ik Lee via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7556cf15527c817983a14eaf20b87fd796f8dc5c
      https://github.com/llvm/llvm-project/commit/7556cf15527c817983a14eaf20b87fd796f8dc5c
  Author: Sang Ik Lee <sang.ik.lee at intel.com>
  Date:   2026-06-08 (Mon, 08 Jun 2026)

  Changed paths:
    M mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp
    A mlir/test/Conversion/XeGPUToXeVM/loadstore_nd_transpose.mlir

  Log Message:
  -----------
  [MLIR][XeGPU] Support transposed load_nd of sub-32-bit elements (#201636)

The 2D block load transpose feature is only available for 32-bit
elements. When a transposed load_nd is requested for a sub-32-bit
element type, the XeGPU-to-XeVM lowering now emulates it by
reinterpreting the tile as 32-bit elements: the element size is promoted
to 32 bits, the tile width is scaled down by (32 / elemBitSize), and the
column offset (offsetW) is right-shifted by log2(32 / elemBitSize) to
account for the wider element.

Add a conversion test (loadstore_nd_transpose.mlir) covering the f16
transposed load path.



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