[all-commits] [llvm/llvm-project] e7e5bb: [AArch64][MacroFusion] Fuse only tied AES pairs po...

[Tomer Shafir via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e7e5bb5e7bd81508b616c50ee9086f5646b2bc0f
      https://github.com/llvm/llvm-project/commit/e7e5bb5e7bd81508b616c50ee9086f5646b2bc0f
  Author: Tomer Shafir <tomer.shafir8 at gmail.com>
  Date:   2026-06-08 (Mon, 08 Jun 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
    A llvm/test/CodeGen/AArch64/misched-fusion-aes-post-ra.mir
    M llvm/test/CodeGen/AArch64/misched-fusion-aes.ll

  Log Message:
  -----------
  [AArch64][MacroFusion] Fuse only tied AES pairs post-RA (#201610)

This patch adds an ad-hoc check to macro fusion to only fuse AES pairs
that are tied post-RA as a guardrail.

Currently, ISel captures every RAW dependent AESE/D+AES[I]MC pair (by
data-dependence DAG), and applies a constraint that the pair must write
to the same dest, i.e the second instruction is tied (a thing that
cannot be expressed in SSA IR). So this is effectively a NFC in that
perspective, as AES is not really being lowered through other paths.
Here we add an appropriate check to macro fusion, if registers are
physical, to avoid pre-RA regression (maintaining the current status
where pre-RA fusion hides theoretical better schedules even if the pari
is not tied). Otherwise the tests in
llvm/test/CodeGen/AArch64/misched-fusion-aes.ll may not catch an ISel
change that would happen to pass, satisfying the register allocation
being filechecked.

If it appears in the future that a subtarget can fuse untied pairs, we
should re-address and maybe distinguish 2 subtarget features for the 2
cases.

Plus adding a test runline for latest apple-m5.

First attempt: https://github.com/llvm/llvm-project/pull/196484



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications