[all-commits] [llvm/llvm-project] 724301: Fix "Cannot select" crash on bitcast between f64 a...

[Abinaya Saravanan via All-commits]

  Branch: refs/heads/release/22.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 724301d98c6ef981111a077489358de10ec14127
      https://github.com/llvm/llvm-project/commit/724301d98c6ef981111a077489358de10ec14127
  Author: Abinaya Saravanan <asaravan at qti.qualcomm.com>
  Date:   2026-06-04 (Thu, 04 Jun 2026)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonPatterns.td
    A llvm/test/CodeGen/Hexagon/bitcast-f64-vector.ll

  Log Message:
  -----------
  Fix "Cannot select" crash on bitcast between f64 and int vector types (#201509)

All of i64, f64, v2i32, v4i16, v8i8 are assigned to the DoubleRegs
register class (64-bit register pairs). A bitcast between any two of
these types is a machine-level no-op (ie. the same physical register is
reinterpreted with a different type).

HexagonPatterns.td had NopCast_pat entries for all int-to-int bitcasts
within DoubleRegs, and explicit patterns for f64 <-> i64, but was
missing patterns for f64 <-> v2i32, f64 <-> v4i16, and f64 <-> v8i8. The
same gap existed in IntRegs for f32 <-> v2i16 and f32 <-> v4i8.

Without a tableGen pattern for "f64 = bitcast v2i32" node, the
instruction selector crashed with:

  LLVM ERROR: Cannot select: t26: f64 = bitcast t6
    t6: v2i32,ch = CopyFromReg t0, Register:v2i32 %2

Fix by adding the five missing NopCast_pat entries.

Fixes: https://github.com/llvm/llvm-project/issues/195495
(cherry picked from commit c005f737e764fab61a02ca5587cf43a16716b5fc)



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