[all-commits] [llvm/llvm-project] 2433b0: [RISCV][TargetLowering][P-ext] Support sext_inreg ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2433b06e6dbe3ef015a226620d207a45f7b98c7c
      https://github.com/llvm/llvm-project/commit/2433b06e6dbe3ef015a226620d207a45f7b98c7c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-06-05 (Fri, 05 Jun 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
    M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
    M llvm/test/CodeGen/RISCV/rvp-simd-64.ll

  Log Message:
  -----------
  [RISCV][TargetLowering][P-ext] Support sext_inreg or v2i32/v4i16 vectors on RV32. (#201752)

Update sext_vector_inreg expansion to use sext_inreg. Previously it
emitted 2 shifts that wouldn't be combined.



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