[all-commits] [llvm/llvm-project] 0f1808: [RISCV][MC] Add experimental `Zvvmtls` and `Zvvmtt...

[Kiva via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0f18088dca8aa03124cac4d174e97174a9aa35be
      https://github.com/llvm/llvm-project/commit/0f18088dca8aa03124cac4d174e97174a9aa35be
  Author: Kiva <zengtao at iscas.ac.cn>
  Date:   2026-06-05 (Fri, 05 Jun 2026)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvvm.td
    M llvm/test/CodeGen/RISCV/features-info.ll
    A llvm/test/MC/RISCV/rvv/zvvmtls-invalid.s
    A llvm/test/MC/RISCV/rvv/zvvmtls.s
    A llvm/test/MC/RISCV/rvv/zvvmttls-invalid.s
    A llvm/test/MC/RISCV/rvv/zvvmttls.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV][MC] Add experimental `Zvvmtls` and `Zvvmttls` support (#198229)

This patch adds experimental MC-layer support for the [RISC-V Integrated
Matrix
Extension](https://github.com/riscv/integrated-matrix-extension/releases/tag/riscv-isa-release-71c48b9-2026-05-17),
specifically the tile load/store extensions: `Zvvmtls` and `Zvvmttls`

This PR:

- Adds the optional tile lambda operand syntax (`L1` through `L64`), and
related asm operand.
- Adds the `vmtl.v`, `vmts.v`, `vmttl.v` and `vmtts.v` instructions to
the MC
- Modifies `parseMaskReg` to return `NoMatch` to allow overloaded
mnemonics to continue matching alternative optional operands, such as
parsing `vmtl.v v8, (a0), a1, L4` as the tile-lambda form instead of
failing by treating `L4` as a malformed mask operand. Real mask
registers missing .t, such as v0, still produce the existing diagnostic.



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