[all-commits] [llvm/llvm-project] de2d0f: [RISCV][P-ext] Add zero/sign extend support betwee...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: de2d0f48ea2c237f12a046c2b56589b1b0ea22e0
      https://github.com/llvm/llvm-project/commit/de2d0f48ea2c237f12a046c2b56589b1b0ea22e0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-06-04 (Thu, 04 Jun 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
    M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
    M llvm/test/CodeGen/RISCV/rvp-simd-64.ll

  Log Message:
  -----------
  [RISCV][P-ext] Add zero/sign extend support between 32-bit and 64-bit vectors. (#201694)

Still need to improve sext on RV64.

Assisted-by: Claude Sonnet 4.6



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