[all-commits] [llvm/llvm-project] 27d0d7: [X86] Add encoding support for indirect branch his...

[Mahesh-Attarde via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 27d0d76799cf05975ee3aa5b6a1d13d6831aae28
      https://github.com/llvm/llvm-project/commit/27d0d76799cf05975ee3aa5b6a1d13d6831aae28
  Author: Mahesh-Attarde <mahesh.attarde at intel.com>
  Date:   2026-06-04 (Thu, 04 Jun 2026)

  Changed paths:
    M llvm/lib/Target/X86/X86InstrSystem.td
    A llvm/test/MC/Disassembler/X86/ibhf-64.txt
    A llvm/test/MC/X86/ibhf-64.s

  Log Message:
  -----------
  [X86] Add encoding support for indirect branch history fence (#200918)

This patch introduces ISA under BHI_CTRL CPUID.
The following tech paper is published in May, 2025:


[intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html#ibhf](https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html#ibhf)

As shown in the paper, The encoding is F3 48 0F 1E F8.
It does not need c-intrinsic.

---------

Co-authored-by: mattarde <mattarde at intel.com>



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