[all-commits] [llvm/llvm-project] 0f4b1e: [AArch64] Address issue reported in PR#196029 (#19...
Harald van Dijk via All-commits
all-commits at lists.llvm.org
Thu Jun 4 06:44:38 PDT 2026
Branch: refs/heads/users/hvdijk/directx-delay-converting-debug-info
Home: https://github.com/llvm/llvm-project
Commit: 0f4b1e11e64fdaaf6258043e1a30014b00bd04d3
https://github.com/llvm/llvm-project/commit/0f4b1e11e64fdaaf6258043e1a30014b00bd04d3
Author: Sushant Gokhale <sgokhale at nvidia.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
Log Message:
-----------
[AArch64] Address issue reported in PR#196029 (#199122)
For certain types of truncating stores, the lowering action is set to
custom although no custom lowering exists for them.
This patch addresses issue reported in PR #196029 by removing the custom lowering entry.
Commit: c6c2ad52586c28e74a724570985a48dc0022d250
https://github.com/llvm/llvm-project/commit/c6c2ad52586c28e74a724570985a48dc0022d250
Author: Aayush Shrivastava <iamaayushrivastava at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/bitfield-insert.ll
M llvm/test/CodeGen/AArch64/bswap-known-bits.ll
M llvm/test/CodeGen/AArch64/sshl_sat.ll
M llvm/test/CodeGen/AArch64/ushl_sat.ll
A llvm/test/CodeGen/X86/aext-and-trunc-avx512.ll
A llvm/test/CodeGen/X86/aext-and-trunc.ll
M llvm/test/CodeGen/X86/and-with-overflow.ll
M llvm/test/CodeGen/X86/combine-srem.ll
M llvm/test/CodeGen/X86/llvm.frexp.ll
M llvm/test/CodeGen/X86/masked_load.ll
M llvm/test/CodeGen/X86/masked_store.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-innerouter.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbits.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-lowhigh.ll
Log Message:
-----------
[DAG] Fold any-extend(and(trunc(x), C)) -> and(x, C) (#200052)
Fixes #195575
Fix a missed optimization in `DAGCombiner::visitANY_EXTEND` where the
pattern `any-extend(and(trunc(x), C))` was not being folded into `and(x,
C)` on X86, causing a redundant `movzbl` instruction to be emitted after
a small-mask AND.
Commit: 91edd87a801fc5c9d12c7f5c6863edd50327cef8
https://github.com/llvm/llvm-project/commit/91edd87a801fc5c9d12c7f5c6863edd50327cef8
Author: mike-goutokuji <gfunni234 at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/ucmp.ll
Log Message:
-----------
[Legalizer] Add support for promoting integers for s/ucmp (#198554)
Instead of manually doing promotion in LowerUCMP of platforms like
PowerPC, we should have this logic in the legalizer.
Commit: 678a6c7dbbb90b5cf856d487820c63aafa6de25b
https://github.com/llvm/llvm-project/commit/678a6c7dbbb90b5cf856d487820c63aafa6de25b
Author: Deric C. <cheung.deric at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
A llvm/test/CodeGen/DirectX/SampleGrad.ll
Log Message:
-----------
[DirectX] Implement lowering of SampleGrad. Refactor sample lowering functions (#200871)
Fixes #192549
This PR builds atop #199745 by adding a helper `lowerSampleOp` function
to refactor `lowerSampleBias` and implement `lowerSampleGrad`.
The `lowerSampleGrad` implementation is very similar to
`lowerSampleBias`, just with ddx and ddy arguments instead of a bias.
Unlike SampleBias, SampleGrad is usable in all shader stages because it
has explicit gradient/derivative arguments.
Assisted-by: GitHub Copilot
Commit: 06ac45db1597049c0e4f04c334bf78cd362b75ee
https://github.com/llvm/llvm-project/commit/06ac45db1597049c0e4f04c334bf78cd362b75ee
Author: Ilpo Ruotsalainen <lonewolf at iki.fi>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
A llvm/test/CodeGen/X86/GlobalISel/calllowering-inalloca.ll
Log Message:
-----------
[GISel][CallLowering] Set byval flag for inalloca/preallocated args (#200600)
GlobalISel asserts when lowering a function with an `inalloca` or
`preallocated` argument:
> TargetCallingConv.h:183: void
llvm::ISD::ArgFlagsTy::setByValSize(unsigned): Assertion `isByVal() &&
!isByRef()' failed.
https://godbolt.org/z/jWr4enjaj
`addFlagsFromAttrSet()` sets the `InAlloca`/`Preallocated` flags but
never `ByVal`.
`setArgFlags()` then calls `Flags.setByValSize()` for any non-`ByRef`
indirect argument which asserts `isByVal()`.
`SelectionDAGISel::LowerArguments()` avoids this by deliberately also
setting the `ByVal` flag for `inalloca`/`preallocated`, this change
makes the GlobalISel side match that behavior.
Commit: 15375d84799ec260d101aa35670f61fa456b6a4e
https://github.com/llvm/llvm-project/commit/15375d84799ec260d101aa35670f61fa456b6a4e
Author: Andre Kuhlenschmidt <andre.kuhlenschmidt at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/include/clang/Options/FlangOptions.td
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/docs/OpenACC-extensions.md
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Support/Fortran-features.cpp
A flang/test/Semantics/OpenACC/acc-default-none-scalars-strict.f90
M flang/test/Semantics/OpenACC/acc-default-none-scalars.f90
Log Message:
-----------
[flang][openacc] change option feature flag names to address comments. (#200037)
- Fixes FeatureFlags and CLI flags to use OpenACC instead of ACC.
- Offline comments further refined the name to be
OpenACCDefaultNoneScalarsStrict
- Which changes the semantics requiring the user to opt out of the
default behavior, instead of opt-in to an extension.
- Also makes the CLI flag OptOut instead of OptIn to match the cli
behavior.
- Gets rid of the unneeded warning flag since FeatureFlags have both a
disabled bit and a warning bit.
- Updates old test for these changes and adds a new test to document all
the different cli configurations.
Commit: cd75a7db92289d9784b471b27cd72cb50a2352fd
https://github.com/llvm/llvm-project/commit/cd75a7db92289d9784b471b27cd72cb50a2352fd
Author: Jan Schultke <me at eisenwave.net>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/clmul.ll
Log Message:
-----------
[SelectionDAG] Fix missed optimization for CLMUL where one operand is all ones (#200592)
Fixes #200556
This special case is equivalent to a "parallel prefix XOR" or "bitwise
parity" operation, which can be expanded to a logarithmic amount of
bitwise operations instead of a linear amount (relative to the bit
width). When other bitwise operations such as BDEP and BEXT are
expanded, they rely on that operation being lowered to a CLMUL directly
or expanded to this efficient form.
See also
- #200570 (this PR needs this fix to have good codegen)
Commit: cf9bf34e29e67fae3562705cfaffb71c7846e8c8
https://github.com/llvm/llvm-project/commit/cf9bf34e29e67fae3562705cfaffb71c7846e8c8
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.cpp
M llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
M llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll
Log Message:
-----------
[AMDGPU] Fix backward compatibility kernarg preload prolog base offset (#201355)
Backward compatibility preload prolog loaded args from kernarg-segment
byte 0, but on non-AMDHSA triples the explicit args start at
`getExplicitKernelArgOffset()` (value: 36), so preloaded SGPRs held the
runtime header instead of the arguments
Commit: ee10231219016efcc51a23bb74dc541dcba3aaf6
https://github.com/llvm/llvm-project/commit/ee10231219016efcc51a23bb74dc541dcba3aaf6
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M libc/include/llvm-libc-macros/_LIBC_MODULAR_FORMAT_PRINTF-disable.h
M libc/include/llvm-libc-macros/_LIBC_MODULAR_FORMAT_PRINTF.h
M libc/include/stdio.yaml
Log Message:
-----------
[libc] Add explicit format attributes for modular printf (#201212)
We had been relying on compiler-generated format attributes when using
the modular_format attribute for printf-family functions, but this is
not applied in -ffreestanding mode. When modular format is enabled, libc
is explicitly asserting the semantics of these functions, so it should
be explicit about the format attributes as well to keep them from
breaking in -ffreestanding.
Generated by Gemini, reviewed and edited by hand.
Commit: 3a1420effe06748cb9bd1b2ef746bd5be25fad52
https://github.com/llvm/llvm-project/commit/3a1420effe06748cb9bd1b2ef746bd5be25fad52
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
A clang/cmake/caches/generic-allow-shared-imports.cmake
A clang/cmake/caches/hexagon-unknown-linux-musl-clang-cross-dist.cmake
A clang/cmake/caches/hexagon-unknown-linux-musl-clang-defaults-dist.cmake
A clang/cmake/caches/hexagon-unknown-linux-musl-clang-dist.cmake
A clang/cmake/caches/hexagon-unknown-linux-musl-clang-dylib-dist.cmake
Log Message:
-----------
[Hexagon] Add cmake caches for cross-toolchain distribution build (#201207)
Adds and extends the
clang/cmake/caches/hexagon-unknown-linux-musl-clang* files to drive a
full install-distribution build: host tools, per-target builtins (Linux
and baremetal), and runtimes for hexagon-unknown-linux-musl.
Commit: f080619e96dfc661fd0f4c0f51a7cc2457d298b9
https://github.com/llvm/llvm-project/commit/f080619e96dfc661fd0f4c0f51a7cc2457d298b9
Author: Martin Erhart <martin.erhart at sifive.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M mlir/include/mlir/Bindings/Python/IRCore.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/test/python/ir/location.py
Log Message:
-----------
[mlir][Python] Downcast location returned from diagnostic (#201337)
Essentially a follow up to
https://github.com/llvm/llvm-project/pull/192630
Commit: 0b109532693fec0dce3a8d275b716f5a5fb6e45c
https://github.com/llvm/llvm-project/commit/0b109532693fec0dce3a8d275b716f5a5fb6e45c
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M lldb/CMakeLists.txt
M lldb/source/Host/common/PythonRuntimeLoader.cpp
Log Message:
-----------
[lldb][windows] explicitly load python3.dll in PythonRuntimeLoader (#201399)
When building with the Python stable API, `liblldb.dll`'s delay-load
crashes because it needs `python3.dll` and it can't find it
Loading `python310.dll` via `LoadLibrary` with a full path doesn't add
Python's directory to the DLL search path for subsequent loads.
This patch also explicitly loads `python3.dll` from the same directory
in `PythonRuntimeLoader` to fix the issue.
This is needed for https://github.com/llvm/llvm-project/pull/200533.
Commit: 7954dcc70ef251581f95582beb7929e286ec9fe9
https://github.com/llvm/llvm-project/commit/7954dcc70ef251581f95582beb7929e286ec9fe9
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Transforms/IPO/HotColdSplitting.cpp
M llvm/test/Transforms/CodeExtractor/input-value-debug.ll
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs.ll.generated.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs.ll.nogenerated.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs_prefix_reuse.ll.generated.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs_prefix_reuse.ll.nogenerated.globals.expected
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[HotColdSplit] Unconditionally mark new functions as cold (#200947)
Previously, HotColdSplit would only mark functions as cold if there was
a profile summary available in the module metadata. This was causing
profcheck failures and is inconsistent with how we handle profile
metadata in other parts of the compiler.
This behavior has been around since
c36c10ddfb3dc07129b9f3973029d17940f6a45f when the profile annotation was
first introduced.
Commit: 7e45473cc229baff6c2a8d2130b58035f4f70e41
https://github.com/llvm/llvm-project/commit/7e45473cc229baff6c2a8d2130b58035f4f70e41
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/lldb/include/lldb/Host/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Host/BUILD.gn
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/DTLTO/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port commits (#201400)
142ad481b625
87d6941017aa
c264e07c2f3d
f91f589aaa82
Commit: 28b12c6317568c8d31a701a35d1c59366030e054
https://github.com/llvm/llvm-project/commit/28b12c6317568c8d31a701a35d1c59366030e054
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/tools/llvm-lto2/BUILD.gn
Log Message:
-----------
[gn build] Add missing dep (#201414)
Commit: 102d8583355c316618648de7d8537299f4357f95
https://github.com/llvm/llvm-project/commit/102d8583355c316618648de7d8537299f4357f95
Author: Jan Schultke <me at eisenwave.net>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/test/CodeGen/X86/clmul.ll
Log Message:
-----------
Regenerate X86/clmul.ll expectations (#201405)
Fixes a build failure on trunk after merging:
- #200592
See
https://github.com/llvm/llvm-project/pull/200592#issuecomment-4614719422
Commit: 3f67f166d6580970a9f4d50bdf7827c510d884d3
https://github.com/llvm/llvm-project/commit/3f67f166d6580970a9f4d50bdf7827c510d884d3
Author: Philipp Rados <philipp.rados at openchip.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
A llvm/test/CodeGen/RISCV/stack-offset-large.ll
Log Message:
-----------
[RISCV] Allow 64-bit fixed frame-offsets on RV64 (#201338)
Some HPC code requires a _very_ large stack. GCC also allows 64-bit
frame-offsets on 64-bit systems.
Since RISCVInstrInfo::movImm() supports materializing 64-bit immediates
the existing framework already handles the lowering correctly.
This patch only enables support for 64-bit _fixed_ frame offsets.
Scalable offsets call RISCVInstrInfo::mulImm() which doesn't seem to
support 64-bit calculations yet. This should be fine since there'd have
to be more than 2^31 RVV spills for this case to happen.
Commit: 1c88bd716167a0650513319176c30dd715101a70
https://github.com/llvm/llvm-project/commit/1c88bd716167a0650513319176c30dd715101a70
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M lldb/include/lldb/Host/MainLoopBase.h
M lldb/source/Host/common/MainLoopBase.cpp
Log Message:
-----------
[lldb] Preserve FIFO order for equal time MainLoop callbacks (#199056)
Co-authored-by: Adrian Prantl <adrian.prantl at gmail.com>
Commit: 6cfa1a01a0f737ed1d54963810057fb1bd67a274
https://github.com/llvm/llvm-project/commit/6cfa1a01a0f737ed1d54963810057fb1bd67a274
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGCUDANV.cpp
R clang/test/CodeGenHIP/offload-pgo-sections.hip
M compiler-rt/CMakeLists.txt
M compiler-rt/lib/profile/CMakeLists.txt
M compiler-rt/lib/profile/InstrProfilingFile.c
R compiler-rt/lib/profile/InstrProfilingPlatformROCm.cpp
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
R llvm/test/Instrumentation/InstrProfiling/amdgpu-instrumentation.ll
R llvm/test/Instrumentation/InstrProfiling/amdgpu-profc-arrays.ll
R llvm/test/Instrumentation/InstrProfiling/gpu-weak.ll
R llvm/test/Transforms/PGOProfile/amdgpu-disable-value-profiling.ll
Log Message:
-----------
Revert "[PGO][AMDGPU] Add basic HIP offload PGO support (#177665)" (#201416)
This broke profiling builds on Windows by switching the profile library
to link against the dynamic CRT; see discussion on the PR.
There were already a number of issues reported and fixed after this PR.
Rather than piling on the fixes (and this one may need some work),
revert back to green for now to let the project recover.
This reverts commit 5db13643f4b7038db0ca304d9f8900122502935c.
Additionally, this reverts the followup PRs in
635e120fb87304924508a7a204574727e3c37363,
2766733764f4bdf8399d48c0225e9c64bdfa95f7,
4c33844b4b560f24b2a3a0cc689d73510cb01ad5, and
5eca8b67ff3c5f371141d54b6e4544a0ebe77fdb:
"[PGO][HIP] Stop pulling ROCm.o into every PGO host link (#200101)"
"[compiler-rt][profile] Add COMPILER_RT_BUILD_PROFILE_ROCM option
(#200127)"
"[PGO][HIP] Skip ROCm interceptor in profile-only compiler-rt builds
(#200111)"
"[PGO][HIP] Fix profile-only Windows link by gating ROCm interceptor
macro (#200859)"
Commit: 09020f9d68e4a0a8f93d2e7f4875ef58f451f948
https://github.com/llvm/llvm-project/commit/09020f9d68e4a0a8f93d2e7f4875ef58f451f948
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for llvm.amdgcn.frexp.exp (#201178)
Commit: e43adaea1fb557e860fbb34568ac024fd649cf5c
https://github.com/llvm/llvm-project/commit/e43adaea1fb557e860fbb34568ac024fd649cf5c
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
A lldb/docs/python_api.md
R lldb/docs/python_api.rst
A lldb/docs/python_extensions.md
R lldb/docs/python_extensions.rst
A lldb/docs/resources/caveats.md
R lldb/docs/resources/caveats.rst
A lldb/docs/resources/contributing.md
R lldb/docs/resources/contributing.rst
A lldb/docs/resources/fuzzing.md
R lldb/docs/resources/fuzzing.rst
A lldb/docs/use/links.md
R lldb/docs/use/links.rst
A lldb/docs/use/ondemand.md
R lldb/docs/use/ondemand.rst
A lldb/docs/use/python-reference.md
R lldb/docs/use/python-reference.rst
A lldb/docs/use/repeat-commands.md
R lldb/docs/use/repeat-commands.rst
Log Message:
-----------
[lldb][docs] Convert simple RST pages to Markdown (NFC) (#201256)
Convert nine short, low-risk RST docs to MyST Markdown as the first
batch of an incremental RST -> Markdown migration. Subsequent batches
will cover the rest.
Verified by building the docs on origin/main and on this branch with
identical sphinx flags and diffing the rendered HTML. Seven of nine
pages are byte-identical.
contributing.html differs in 42 lines, all attributable to `{doc}` xrefs
replacing RST hyperlinks to sibling pages (`reference external` ->
`reference internal`) and CommonMark collapsing two-spaces-after- period
to one.
ondemand.html differs in 26 lines because two bulleted lists that
followed a paragraph with no blank-line separator originally rendered as
literal `- ...` text in both RST and Markdown. The conversion tool
preserved that by emitting `\-`; this patch instead inserts a blank line
so they render as proper `<ul>` lists, fixing a latent doc bug.
Context:
https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/
Assisted-by: Claude
Commit: 47209321457b4302ac0d2cb668cdd3f3caff9134
https://github.com/llvm/llvm-project/commit/47209321457b4302ac0d2cb668cdd3f3caff9134
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCComputeLowering.cpp
A mlir/test/Dialect/OpenACC/acc-compute-lowering-compute-device-type.mlir
A mlir/test/Dialect/OpenACC/acc-compute-lowering-loop-device-type.mlir
Log Message:
-----------
[mlir][acc] ACCComputeLowering needs to account for device_type par (#201267)
When assigning parallelism for compute constructs or loops, device_type
parallelism must be first considered as a group for all available (gang,
worker, vector) - if any of these have device_type setting, then those
are the only ones that should be considered. Only if the loop has no
device_type specific parallelism then default parallelism should be
assigned.
Commit: 91b00526a599fa21e43da82438f1e9c8a8e1b7b3
https://github.com/llvm/llvm-project/commit/91b00526a599fa21e43da82438f1e9c8a8e1b7b3
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/IR/BasicBlock.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
A llvm/test/Bitcode/musttail-bitcast-upgrade.ll
A llvm/test/Bitcode/musttail-bitcast-upgrade.ll.bc
M llvm/test/Instrumentation/AddressSanitizer/musttail.ll
M llvm/test/Instrumentation/ThreadSanitizer/tsan_musttail.ll
M llvm/test/Transforms/CallSiteSplitting/musttail.ll
M llvm/test/Transforms/SafeStack/X86/musttail.ll
M llvm/test/Verifier/musttail-invalid.ll
Log Message:
-----------
Remove the optional bitcast between a musttail call and its ret (#201280)
Under opaque pointers the only bitcast the verifier could accept in this
position is a no-op ptr->ptr cast
Drop it and reduce isTypeCongruent to a plain type equality check
Commit: 420b8b3cede41894dc5dac29f8e64bcff13e3620
https://github.com/llvm/llvm-project/commit/420b8b3cede41894dc5dac29f8e64bcff13e3620
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/tools/llvm-exegesis/lib/LlvmState.cpp
M llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
M llvm/tools/llvm-exegesis/lib/MCInstrDescView.h
M llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp
Log Message:
-----------
[llvm-exegesis] Support LookupRegClassByHwMode in exegesis Instruction::create
This resolves the TODO for LookupRegClassByHwMode support in llvm-exegesis by
passing the MCSubtargetInfo to Instruction::create and calling
getOpRegClassID with the active HwMode.
This also updates MemoryUse test expectations for Mips, as the target now
correctly resolve HwMode-dependent memory register operands (MSA128F16 in
Mips and post-#177073 BasePtrRegClass for RISC-V).
Pull Request: https://github.com/llvm/llvm-project/pull/200525
Commit: 4169b17acfe53c79e0e170ebb8249ef749e061a2
https://github.com/llvm/llvm-project/commit/4169b17acfe53c79e0e170ebb8249ef749e061a2
Author: adams381 <adams at nvidia.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
Log Message:
-----------
[CIR][NFC] Remove unused DataLayout in array lowering (#201408)
The per-element loop in CIRAttrToValue::visitCirAttr(ConstArrayAttr) constructed an mlir::DataLayout for every element of an ArrayAttr-backed constant array and never used it. Constructing a DataLayout walks the parent ops to gather the layout spec, so for an N-element array this was N redundant constructions on the lowering path. Removing the dead local is NFC -- the generated IR is unchanged.
Split out of #198427, where it was flagged as an unrelated drive-by.
Commit: 0b9dc1bdd3a0186582ae7a56c3c27b6e449715fa
https://github.com/llvm/llvm-project/commit/0b9dc1bdd3a0186582ae7a56c3c27b6e449715fa
Author: cmtice <cmtice at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M lldb/docs/dil-expr-lang.ebnf
M lldb/include/lldb/ValueObject/DILAST.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/include/lldb/ValueObject/DILLexer.h
M lldb/include/lldb/ValueObject/DILParser.h
M lldb/include/lldb/ValueObject/ValueObject.h
M lldb/source/ValueObject/DILAST.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILLexer.cpp
M lldb/source/ValueObject/DILParser.cpp
M lldb/source/ValueObject/ValueObject.cpp
A lldb/test/API/commands/frame/var-dil/expr/Assignment/Makefile
A lldb/test/API/commands/frame/var-dil/expr/Assignment/TestFrameVarDILAssign.py
A lldb/test/API/commands/frame/var-dil/expr/Assignment/TestFrameVarDILCompositeAssign.py
A lldb/test/API/commands/frame/var-dil/expr/Assignment/main.cpp
Log Message:
-----------
[LLDB] Add assignment to DIL. (#190223)
Add the ability for DIL to recognize and process assignment, updating
program variables. Recognizes '=', '+=' and '-=' operators. Increment
and decrement ('++' and '--') will be added in a separate (future) PR.
"*=" and "/=" need to wait until DIL handles multiply and divide
operators.
Commit: 5708e7fd9eca368b1b519c13a58360a15a263e4f
https://github.com/llvm/llvm-project/commit/5708e7fd9eca368b1b519c13a58360a15a263e4f
Author: George Burgess IV <george.burgess.iv at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M compiler-rt/lib/scudo/standalone/tests/primary_test.cpp
Log Message:
-----------
[compiler-rt] fix out-of-bounds access in scudo test (#201390)
When `I = 0`, we can't do `Array[I-1]`.
Caught by libcxx hardening.
Commit: 517308ad15ee9480edfb9aa6dcc2c628c43da20d
https://github.com/llvm/llvm-project/commit/517308ad15ee9480edfb9aa6dcc2c628c43da20d
Author: Aayush Shrivastava <iamaayushrivastava at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/ContainerSizeEmptyCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/container-size-empty.rst
M clang-tools-extra/test/clang-tidy/checkers/readability/container-size-empty.cpp
Log Message:
-----------
[clang-tidy] Extend readability-container-size-empty to std::size() (#201231)
Fixes #198494
Extend the check to warn when the non-member `std::size()` free function
is used in a boolean context or compared to 0/1, and suggest using
.empty instead.
Commit: 7e439d571e3dcf420448391eb76e58879e73ee1e
https://github.com/llvm/llvm-project/commit/7e439d571e3dcf420448391eb76e58879e73ee1e
Author: khaki3 <47756807+khaki3 at users.noreply.github.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-intrinsics.ll
Log Message:
-----------
[VectorCombine] Skip foldShuffleOfIntrinsics when operand types differ (#201241)
Example:
```llvm
define <4 x i32> @t(<2 x float> %a, <2 x double> %b) {
%fa = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f32(<2 x float> %a)
%fb = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double> %b)
%s = shufflevector <2 x i32> %fa, <2 x i32> %fb, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x i32> %s
}
```
In this code, `foldShuffleOfIntrinsics` folds `shuffle(intrinsic(x),
intrinsic(y))` into `intrinsic(shuffle(x, y))`, but only checks the
result type, not the operand types. Since `fptosi.sat` is overloaded on
its operand type, the two calls share an `<2 x i32>` result but have
different operands (`<2 x float>` vs `<2 x double>`), so the new
`shufflevector` gets mismatched operands and trips `isValidOperands`.
Fix: bail out when the intrinsics' shuffled operands have different
types.
Commit: bad4005b863bf8f8d0f108d82c27c10d59d01e6d
https://github.com/llvm/llvm-project/commit/bad4005b863bf8f8d0f108d82c27c10d59d01e6d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/utils/LLVMVisualizers/llvm.natvis
Log Message:
-----------
[NATVIS] Fix bitrotted SmallPtrSet handling (#201404)
Use IsSmall to report Small/Big Mode
Use NumEntries instead of NumNonEmpty to track array size
Commit: 85b72c16948f940058e04cd804ffb1d9b4249407
https://github.com/llvm/llvm-project/commit/85b72c16948f940058e04cd804ffb1d9b4249407
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/AsmParser/LLParser.cpp
A llvm/test/Assembler/invalid-phi-fast-math-flags.ll
A llvm/test/Assembler/invalid-select-fast-math-flags.ll
Log Message:
-----------
[AsmParser] Delete orphaned select/phi when rejecting fast-math-flags (#201409)
parseSelect/parsePHI create the instruction before the caller checks the
fast-math-flags. When FMF are rejected on a non-FP select/phi, the error
path leaked the instruction, which crashed on teardown with "Uses remain
when a value is destroyed!".
Fix by deleting the instruction before returning the error, as is
already done for `call`.
Fixes #185111.
Commit: 974be2bc84be577e395479171f1db70d733d7efc
https://github.com/llvm/llvm-project/commit/974be2bc84be577e395479171f1db70d733d7efc
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
A llvm/test/Transforms/LoopInterchange/non-phi-uses-lcssa-phi.ll
Log Message:
-----------
[LoopInterchange] Fix assertion failure when LCSSA PHI is used by non-PHI (#201059)
This patch fixes one of the assertion failures reported in #200819. The
root cause is that the assertion assumes all uses of LCSSA PHIs are PHI
nodes, which is not always true, so `cast<PHINode>(U)` can fail. In
fact, the user does not have to be a PHI, and the assertion should apply
the special check only when the user is a PHI node.
Commit: 8eb252007ce042204d9ebf904a353864989ffe8b
https://github.com/llvm/llvm-project/commit/8eb252007ce042204d9ebf904a353864989ffe8b
Author: satyanarayana reddy janga <satyajanga at fb.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M lldb/docs/resources/lldbgdbremote.md
M lldb/include/lldb/Utility/AcceleratorGDBRemotePackets.h
M lldb/include/lldb/Utility/StringExtractorGDBRemote.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.h
M lldb/source/Plugins/Process/gdb-remote/LLDBServerAcceleratorPlugin.h
M lldb/source/Utility/AcceleratorGDBRemotePackets.cpp
M lldb/source/Utility/StringExtractorGDBRemote.cpp
M lldb/test/API/accelerator/mock/TestMockAcceleratorPlugin.py
M lldb/tools/lldb-server/Plugins/Accelerator/Mock/LLDBServerMockAcceleratorPlugin.cpp
M lldb/tools/lldb-server/Plugins/Accelerator/Mock/LLDBServerMockAcceleratorPlugin.h
A lldb/unittests/Utility/AcceleratorGDBRemotePacketsTest.cpp
M lldb/unittests/Utility/CMakeLists.txt
Log Message:
-----------
[lldb-server] Add breakpoint support to accelerator plugin protocol (#200584)
This is the 2nd PR of many related to
https://discourse.llvm.org/t/upstreaming-basic-support-for-accelerators/89827/6
Continuation to https://github.com/llvm/llvm-project/pull/198907
Extend the accelerator plugin infrastructure with breakpoint request and
hit handling, allowing plugins to set breakpoints in the native process
and respond when those breakpoints are hit.
This patch adds:
- Support for jAcceleratorPluginBreakpointHit packet handler in
GDBRemoteCommunicationServerLLGS that routes hits to the correct plugin
by name and returns the plugin's response
- Many related struct for defining request packet and response packet.
New structs: AcceleratorBreakpointByName,
AcceleratorBreakpointByAddress, AcceleratorBreakpointInfo, SymbolValue
,AcceleratorBreakpointHitArgs and AcceleratorBreakpointHitResponse
structs with JSON encode/decode for the hit round-trip.
- breakpoints field in AcceleratorActions for plugins to request
breakpoints during initialization
- Tests verifying breakpoints in initialize response and breakpoint hit
round-trip with JSON validation
- Packet documentation in lldbgdbremote.md
Commit: d8fb3dc721c4481eabc95f1a1ab6e2d270d763b4
https://github.com/llvm/llvm-project/commit/d8fb3dc721c4481eabc95f1a1ab6e2d270d763b4
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M offload/test/api/omp_indirect_func_basic.c
M offload/test/offloading/cuda_no_devices.c
M offload/test/offloading/shared_lib_fp_mapping.c
Log Message:
-----------
[offload][lit] Disable three more tests on Intel GPU (#201381)
Buildbot is still unstable, these tests are causing kernel driver errors
so let's disable them.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: b76fb96a862f3acf374117895a44a36c0a23d615
https://github.com/llvm/llvm-project/commit/b76fb96a862f3acf374117895a44a36c0a23d615
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M offload/plugins-nextgen/level_zero/include/L0Program.h
M offload/plugins-nextgen/level_zero/src/L0Program.cpp
M offload/unittests/OffloadAPI/symbol/olGetSymbolInfo.cpp
Log Message:
-----------
[OFFLOAD][L0] Return symbol size in getGlobalMetadataFromDevice (#201352)
Return not just the address but also the size of the symbols in getGlobalMetadataFromDevice.
Fixes olGetSymbolInfoSizeGlobalTest.SuccessSize unitt test failure with L0 plugin.
Commit: 1b5a86f165d642cac56cb4a4becbded2c1872c1d
https://github.com/llvm/llvm-project/commit/1b5a86f165d642cac56cb4a4becbded2c1872c1d
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M offload/unittests/OffloadAPI/memory/olMemFill.cpp
Log Message:
-----------
[OFFLOAD] Update L0 olMemFill unit tests known failures (#201323)
With the latest L0 changes most MemFill tests are passing. Only those
that rely on olLaunchHostFunction should be skipped.
Commit: 0fcf63e179486c0a7e72d656c65d2c0a45754a11
https://github.com/llvm/llvm-project/commit/0fcf63e179486c0a7e72d656c65d2c0a45754a11
Author: Ron Green [NVIDIA] <rogreen at nvidia.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M flang/docs/OpenACC-extensions.md
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Parser/openacc-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/check-cuda.cpp
M flang/lib/Semantics/check-do-forall.cpp
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Semantics/OpenACC/acc-reduction-validity.f90
M flang/test/Semantics/reduce.cuf
M flang/test/Semantics/resolve124.f90
Log Message:
-----------
[flang][OpenACC] Add minus operator to reduction clause (#200909)
Adds '-' as a recognized reduction operator alongside '+'. The new
ReductionOperator::Operator::Minus is parsed from the '-' token,
accepted on integer/real/complex reduction variables, and lowered the
same as Plus (mlir::acc::ReductionOperator::AccAdd in OpenACC, and
fir::ReduceOperationEnum::Add in DO CONCURRENT). The unparser emits it
as '-'.
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: 884168c32563d20b0f2d6df5210a07c9de18a332
https://github.com/llvm/llvm-project/commit/884168c32563d20b0f2d6df5210a07c9de18a332
Author: Michael Jones <michaelrj at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M libc/include/llvm-libc-macros/math-macros.h
Log Message:
-----------
[libc] add HUGE_VALL (#201235)
Straightforward macro in math-macros.h
Commit: d703919410c5055132c037df810dfe70074ef58b
https://github.com/llvm/llvm-project/commit/d703919410c5055132c037df810dfe70074ef58b
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
A llvm/test/Transforms/LoopInterchange/atomic-memory-ordering.ll
A llvm/test/Transforms/LoopInterchange/invoke.ll
Log Message:
-----------
[LoopInterchange] Add tests for instructions that aren't checked (NFC) (#201401)
This patch adds test cases that contain instructions which are currently
not handled properly in the legality check, leading to miscompilations.
Some of the test cases are taken from #200913, and others are cases that
trigger unsafe interchange for the same reason. I am not trying to cover
all possible instruction types here, since a follow-up patch will update
the legality check so that it can handle other instructions as well.
Commit: 37432c85b43654d0c3e15edd503e95c74f39afb1
https://github.com/llvm/llvm-project/commit/37432c85b43654d0c3e15edd503e95c74f39afb1
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M lldb/unittests/Host/CMakeLists.txt
Log Message:
-----------
[lldb] Add PARTIAL_SOURCES_INTENDED to HostTests to fix build (#201361)
with LLDB_ENABLE_PYTHON=OFF
PythonRuntimeLoaderTest.cpp is only added to the target when Python is
enabled, which orphaned the source and broke configuration otherwise
culprit PR: https://github.com/llvm/llvm-project/pull/200524
Commit: 5e890995b2ebcf4bbbf8fb3161647c4788245e4c
https://github.com/llvm/llvm-project/commit/5e890995b2ebcf4bbbf8fb3161647c4788245e4c
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
Log Message:
-----------
[AMDGPU] Simplify getDivNumBits with APInt::countMaxActiveBits. NFC. (#201387)
Commit: 3d830a9c517725bd73e9497cbe4c159c6d04f9ba
https://github.com/llvm/llvm-project/commit/3d830a9c517725bd73e9497cbe4c159c6d04f9ba
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-cache.f90
Log Message:
-----------
[flang][OpenACC] Re-declare cached array sections with lower bounds only (#201223)
When acc.cache yields a box, rebind the symbol with a fir.shift (lower
bounds, no extents) instead of a fir.shape_shift, so the rebox preserves
the materialized descriptor's extents and strides. Add lowering tests.
Assisted by Claude
Commit: cca173885706f6c728b46f9035f034de4f39a4ba
https://github.com/llvm/llvm-project/commit/cca173885706f6c728b46f9035f034de4f39a4ba
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/test/Transforms/LoopInterchange/atomic-memory-ordering.ll
M llvm/test/Transforms/LoopInterchange/call-instructions-remarks.ll
M llvm/test/Transforms/LoopInterchange/invoke.ll
Log Message:
-----------
[LoopInterchange] Identify unsafe instructions for interchange (#201402)
In LoopInterchange, all instructions in the loops are traversed and
checked during the legality phase, and the pass bails out if it finds an
instruction that is unsafe to interchange. However, previously it only
handled call instructions and ignored all others, leaving several kinds
of instruction that should have been detected but were not.
This patch fixes the issue by restructuring the legality check, in
particular replacing instruction‑specific handling with calling general
Instruction APIs.
Fixes #200913.
Commit: fb649b41b0db8cd33a5be613345be845a41d0d98
https://github.com/llvm/llvm-project/commit/fb649b41b0db8cd33a5be613345be845a41d0d98
Author: Miguel A. Arroyo <miguel.arroyo at rockstargames.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
Log Message:
-----------
[compiler-rt][cmake][msvc] Install PDBs for shared libraries (#201224)
Following up on similar PRs in the past to address PDBs not being copied
for install targets:
* https://github.com/llvm/llvm-project/pull/126961
* https://github.com/llvm/llvm-project/pull/126680
* https://github.com/llvm/llvm-project/pull/120683
Commit: 3c9afa9fe7c091dffd353e65a9a16653f139787b
https://github.com/llvm/llvm-project/commit/3c9afa9fe7c091dffd353e65a9a16653f139787b
Author: Petr Hosek <phosek at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
A llvm/docs/ProjectGovernance.rst
M llvm/docs/index.rst
Log Message:
-----------
[Docs] Project governance documentation (#197108)
This page largely covers the same information as proposal LP-0004 and
also includes information on current area team and project council
composition.
Commit: 0a4f19e4769eae755cdad1a4af1d73988762dd2c
https://github.com/llvm/llvm-project/commit/0a4f19e4769eae755cdad1a4af1d73988762dd2c
Author: mygitljf <101249452+mygitljf at users.noreply.github.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/FormatTestObjC.cpp
Log Message:
-----------
[clang-format][Objective-C] Fix assertion crash on stray '-'/'+' in @interfa… (#199104)
Before calling `parseObjCMethod()`, it now checks whether the next token
is a `(` or an identifier; if not, it simply skips ahead, thereby
preventing the assertion failure and subsequent crash.
Fixes #199075
Commit: b207fd6fd43514b2852ff64b89769a2cf4b781c2
https://github.com/llvm/llvm-project/commit/b207fd6fd43514b2852ff64b89769a2cf4b781c2
Author: Martin Storsjö <martin at martin.st>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M lldb/CMakeLists.txt
M lldb/source/Host/common/PythonRuntimeLoader.cpp
Log Message:
-----------
[lldb] Use the right MinGW name for the Python DLLs (#201325)
In MinGW mode, the Python DLLs have different names than they have in
MSVC mode; they are named `libpython<major>.<minor>.dll` (a "lib" prefix
and a dot between major and minor) and `libpython3.dll`.
This avoids a warning on startup after
142ad481b6254104a51da7d636ad9e3f30518a32 and total failures to start up
after 3eb13f8db39ed42827122489c830c414cb6660e3.
Commit: 98160521cb72966e984a241f28b1dc5aae19e4ec
https://github.com/llvm/llvm-project/commit/98160521cb72966e984a241f28b1dc5aae19e4ec
Author: Justin Lebar <justin.lebar at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/test/CodeGen/NVPTX/global-ordering.ll
Log Message:
-----------
[NVPTX] Handle symbol-relative integer initializers in aggregates (#201220)
A symbol-relative integer applies an offset outside the ptrtoint, e.g.
@g = addrspace(1) global i8 0
@s = addrspace(1) global { i64, i64 }
{ i64 add (i64 ptrtoint (ptr addrspace(1) @g to i64), i64 4),
i64 7 }
I'm not sure this is an important feature, but it's explicitly
implemented and works for scalars; the bug is that it hits
llvm_unreachable if you use it inside an aggregate.
While we're here, we also add support for Sub in addition to Add.
Commit: 309ace568351f1d3001a736c58c496277fc000dd
https://github.com/llvm/llvm-project/commit/309ace568351f1d3001a736c58c496277fc000dd
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Log Message:
-----------
[RISCV] Remove unnecessary explicit template parameter on has_single_bit (#201421)
I think this code was extracted into a function and the Amount was not a
uint32_t when it was in the original location.
Commit: 67a641cf8adb083e6694fbf306b375b99c45de91
https://github.com/llvm/llvm-project/commit/67a641cf8adb083e6694fbf306b375b99c45de91
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACCCG.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCComputeLowering.cpp
A mlir/test/Dialect/OpenACC/acc-compute-lowering-compute-async-wait.mlir
M mlir/test/Dialect/OpenACC/canonicalize.mlir
Log Message:
-----------
[mlir][acc] Specialize compute region target during ACCComputeLowering (#201386)
During ACCComputeLowering, when an acc compute region (such as
acc.parallel) is split into in acc.kernel_environment and
acc.compute_region, all wait and async operands are transferred over.
This includes the multiple lists that are used to manage device_type
specific aspects eg:
`acc parallel async device_type(nvidia) async(2)`
This ends up as
`acc.parallel async([#acc.device_type<none>], %c2_i32 : i32
[#acc.device_type<nvidia>])`
And similarly, acc.kernel_environment inherited both async aspects.
However, during ACCComputeLowering, the pass knows its device_type
target. Thus it can directly create a single async (because only
async(2) applies when device_type is nvidia): `acc.kernel_environment
async(%c2_i32 : i32)`
This MR simplifies the operation to not hold all of the multiple lists
and updates to ACCComputeLowering pass to ensure to transfer only
relevant information. The intent/goal is that the none of the CG
operations will hold device_type specific lists.
Commit: deb6854eec93529b2bd30178d400ad2ee7665cd4
https://github.com/llvm/llvm-project/commit/deb6854eec93529b2bd30178d400ad2ee7665cd4
Author: Justin Lebar <justin.lebar at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/test/CodeGen/NVPTX/globals_init.ll
Log Message:
-----------
[NVPTX] Pad non-power-of-2 vectors in structs properly. (#201246)
A non-power-of-2 vector inside of a struct is padded up to its alloc
size.
But when the NVPTX asm printer emits bytes for such a struct, it
currently skips this tail padding, thus emitting an incorrect struct.
Commit: 971076f616e6c6f07580c506375b700b207224f9
https://github.com/llvm/llvm-project/commit/971076f616e6c6f07580c506375b700b207224f9
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M mlir/test/Conversion/ConvertToSPIRV/arith.mlir
Log Message:
-----------
[NFC][mlir][SPIR-V] Test ceildivui/ceildivsi/floordivsi via test-convert-to-spirv (#198766)
SPIR-V has no direct opcode for these ops. Verify that using
`--test-convert-to-spirv` pass is sufficient to convert these ops to
SPIR-V
Commit: 55587f7b757583b1e30c3027803ed092790471a3
https://github.com/llvm/llvm-project/commit/55587f7b757583b1e30c3027803ed092790471a3
Author: Adhemerval Zanella <zatrazz at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/read-fp-reg.ll
A llvm/test/CodeGen/AArch64/read-reg-non-entry.ll
M llvm/test/CodeGen/AArch64/write-volatile-register.ll
Log Message:
-----------
[CodeGen] Mark read_register of allocatable physreg as live-in (#200825)
llvm.read_register / llvm.read_volatile_register of an allocatable
register (e.g. the MSVC __getReg/__getRegFp intrinsics reading xN/dN)
was lowered to a plain COPY from the physical register. That COPY uses a
physical register that is never defined, which the machine verifier
rejects as "Using an undefined physical register" (seen on
read-fp-reg.ll under LLVM_ENABLE_EXPENSIVE_CHECKS).
Reading such a register only makes sense as "whatever value it currently
holds", i.e. like an inline-asm read; it cannot be modelled as a normal
SSA use of a physical register, and a live-in only works in the entry
block.
Lower these reads in AArch64 like the existing MRS/MSR sysreg path:
select to a small pseudo (READ_REGISTER_GPR64 / READ_REGISTER_FPR64)
that carries the source register as an immediate operand rather than a
tracked physical-register use, and have the AsmPrinter materialize the
real "mov Xt, Xn" / "fmov Dt, Dn". The verifier never sees an undefined
physreg use, so the read is valid in any block and needs no live-in or
undef. Reads of reserved registers (e.g. sp) and system registers keep
their existing lowering.
Commit: 4d23acde98acb72e103d8c999edf752a9317aced
https://github.com/llvm/llvm-project/commit/4d23acde98acb72e103d8c999edf752a9317aced
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M .github/workflows/release-binaries.yml
M llvm/utils/release/github-upload-release.py
Log Message:
-----------
[release] Add zstd archives to github releases (#186526)
This leaves the previous xz files but also creates zstd archives of the
binaries. This provides significantly reduced download sizes. We could
integrate this with cpack but we don't have control over the compression
level in that until version 4.3 which isn't even released yet.
Fixes https://github.com/llvm/llvm-project/issues/164537
Commit: f70a28f4d1b5d17d94fca03fb74387ad800560de
https://github.com/llvm/llvm-project/commit/f70a28f4d1b5d17d94fca03fb74387ad800560de
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
A lldb/docs/resources/build.md
R lldb/docs/resources/build.rst
A lldb/docs/resources/dataformatters.md
R lldb/docs/resources/dataformatters.rst
A lldb/docs/resources/debugging.md
R lldb/docs/resources/debugging.rst
A lldb/docs/resources/extensions.md
R lldb/docs/resources/extensions.rst
A lldb/docs/resources/formatterbytecode.md
R lldb/docs/resources/formatterbytecode.rst
A lldb/docs/resources/overview.md
R lldb/docs/resources/overview.rst
A lldb/docs/resources/projects.md
R lldb/docs/resources/projects.rst
A lldb/docs/resources/qemu-testing.md
R lldb/docs/resources/qemu-testing.rst
A lldb/docs/resources/sbapi.md
R lldb/docs/resources/sbapi.rst
A lldb/docs/resources/test.md
R lldb/docs/resources/test.rst
Log Message:
-----------
[lldb][docs] Convert resources/ RST docs to Markdown (NFC) (#201442)
Convert the ten contributor-facing RST docs under lldb/docs/resources/
to MyST Markdown. This is the second batch of an incremental RST ->
Markdown migration. The previous PR (#201256) covered nine small leaf
pages.
Files: build, dataformatters, debugging, extensions, formatterbytecode,
overview, projects, qemu-testing, sbapi, test.
Verified by building the docs on origin/main and on this branch with
identical sphinx flags and diffing both the warnings and the rendered
HTML. After file extension and line numbers are normalized, the warning
sets match exactly. Six of the ten pages are byte-identical. The four
that differ (dataformatters, projects, sbapi, test) differ only in:
- CommonMark collapsing two-spaces-after-period to one.
- MyST adding a `myst` CSS class to `<dl>` elements and an `<hr>`
separator before footnote sections.
- Footnote IDs renamed from auto `id3` to named `footnote-1`.
The diff also surfaced two semantic regressions in the conversion, fixed
here:
- build.md `{ref}` to `Optional Dependencies` did not match the new
`(optional-dependencies)=` anchor; updated to use the new label.
- test.md and build.md lost cross-reference behavior on single- backtick
refs to SB-class names and `lldb`. RST's default role is `any`, so
single backticks attempted xrefs; in MyST single backticks are plain
code spans. Converted these 14 occurrences to explicit `{any}`...``
syntax.
Several `eval-rst` blocks remain in formatterbytecode.md and test.md to
preserve grid tables that MyST does not render natively.
Context: https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/
Assisted-by: Claude
Commit: ad422cd10bfd0be0c069221546de7c7299ca305d
https://github.com/llvm/llvm-project/commit/ad422cd10bfd0be0c069221546de7c7299ca305d
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M flang/lib/Semantics/expression.cpp
A flang/test/Semantics/cuf-constant-generic-unified.cuf
Log Message:
-----------
[flang][cuda] Handle Constant and Shared attributes in CUDA generic matching distance (#201451)
The CUDA generic resolution matching distance function did not handle
actual arguments with the `Constant` or `Shared` data attribute. These
attributes represent device memory but were unhandled, causing the
distance to fall through to infinity. Under `-gpu=mem:unified`, this led
to spurious ambiguity errors when multiple specifics (e.g.
host-to-device and device-to-device overloads) both became candidates
with tied infinite distances.
Treat Constant and Shared actuals the same as Device in the matching
distance table, since all three reside in device memory.
Commit: 9ae0d890a9236a94f23d5c3ff84ea08d7a670f03
https://github.com/llvm/llvm-project/commit/9ae0d890a9236a94f23d5c3ff84ea08d7a670f03
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/test/Analysis/Checkers/WebKit/call-args.cpp
M clang/test/Analysis/Checkers/WebKit/mock-types.h
M clang/test/Analysis/Checkers/WebKit/nodelete-annotation.cpp
A clang/test/Analysis/Checkers/WebKit/nodelete-lazy-initialize.cpp
Log Message:
-----------
[alpha.webkit.NoDeleteChecker] Treat a r-value smart pointer return value as no-delete. (#200912)
Skip the checkin g of the destructor of T in ExprWithCleanups /
CXXBindTemporaryExpr when returning a value using r-value reference
since such a construct never invokes delete.
---------
Co-authored-by: Balazs Benics <benicsbalazs at gmail.com>
Commit: 901cfb4aa4d52fd4f751b78bf932f54210fdcf5b
https://github.com/llvm/llvm-project/commit/901cfb4aa4d52fd4f751b78bf932f54210fdcf5b
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
M llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
M llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
M llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp
A llvm/test/CodeGen/Hexagon/hvc-remarks.ll
A llvm/test/CodeGen/Hexagon/hwloop-remarks.ll
A llvm/test/CodeGen/Hexagon/loop-idiom-remarks.ll
A llvm/test/CodeGen/Hexagon/vlcr-remarks.ll
Log Message:
-----------
[Hexagon] Add optimization remarks to Hexagon IR and MIR passes (#189176)
Add OptimizationRemark/OptimizationRemarkMissed emissions to four
Hexagon-specific passes, making them observable via the standard
-Rpass/-Rpass-missed flags:
- HexagonLoopIdiomRecognition (hexagon-lir): remarks for loop-to-memcpy/
memmove conversions and polynomial multiply recognition, with missed
remarks for non-countable loops, aliasing, non-affine pointers, etc.
- HexagonVectorLoopCarriedReuse (hexagon-vlcr): remarks for reused
loop-carried vector values, with missed remarks for multi-block loops,
non-innermost loops, and missing candidates.
- HexagonVectorCombine (hexagon-vc): remarks for aligned vector memory
operations, with missed remarks for group size limits, unsafe
relocations, and insufficient HVX version.
- HexagonHardwareLoops (hwloops): remarks for hardware loop conversion,
with missed remarks for invalid instructions (calls), multiple exits,
induction variable issues, and non-computable trip counts.
Commit: 5f975bb6afec710e4ef47c3b90a299b2212c6ec0
https://github.com/llvm/llvm-project/commit/5f975bb6afec710e4ef47c3b90a299b2212c6ec0
Author: Michael Spencer <bigcheesegs at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/include/clang-c/BuildSystem.h
M clang/include/clang/Serialization/ModuleCache.h
M clang/lib/Serialization/ModuleCache.cpp
M clang/tools/libclang/BuildSystem.cpp
M clang/tools/libclang/libclang.map
M clang/unittests/libclang/LibclangTest.cpp
Log Message:
-----------
[libclang] Add clang_ModuleCache_pruneWithCallback (#199789)
clang_ModuleCache_pruneWithCallback takes a callback that is invoked for
each PCM that gets pruned. This is to support build systems that would
like to clean up additional data when PCMs are removed from disk.
Commit: 2e9cdc4f3be729686c8c238f9da2ffa961690e47
https://github.com/llvm/llvm-project/commit/2e9cdc4f3be729686c8c238f9da2ffa961690e47
Author: Justin Lebar <justin.lebar at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/test/CodeGen/NVPTX/global-ordering.ll
Log Message:
-----------
[NVPTX] Remove support for `sub` in global initializers. (#201473)
I added this in https://github.com/llvm/llvm-project/pull/201220 and
assumed it worked because the pre-commit builders passed. But (a) this
is not attested in the PTX ISA, and (b) it seems that the builders don't
actually run ptxas.
Oops. Removed support for `sub`.
Commit: 49ac4f475e4cf643a3fd68f9bf97f6b7d1adef83
https://github.com/llvm/llvm-project/commit/49ac4f475e4cf643a3fd68f9bf97f6b7d1adef83
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/test/CodeGen/Xtensa/inline-asm-invalid.ll
M llvm/test/CodeGen/Xtensa/setcc.ll
Log Message:
-----------
[Xtensa] Fix setcc test. (#201196)
Fix setcc test after changes in llvm passes.
Also add minor fix in inline-asm-invalid.ll test.
Commit: 2b081a26d96450283814209d2b9001db89000f0a
https://github.com/llvm/llvm-project/commit/2b081a26d96450283814209d2b9001db89000f0a
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
A llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
M llvm/test/CodeGen/AMDGPU/sched-ldsdma-mask.mir
Log Message:
-----------
[AMDGPU] Do not add latency for tensorcnt / asynccnt dependencies (#201201)
Currently, when constructing the ScheduleDAG we see dependencies between
LDSDMA->LDSDMA or s_wait->s_wait due to implicit $asynccnt / $tensorcnt
operands. These implicit operands are necessary to force ordering of the
instructions, but there should be no latency for this dependency. In the
LDSDMA->LDSDMA case, the scheduler thinks it will be hundreds of cycles
until the next LDSDMA is ready.
This handles the cases:
1. LDSDMA -> LDSDMA
2. WAIT -> LDSDMA
3. WAIT -> WAIT
In the LDSDMA -> WAIT case, usually the relevant WAIT is in a different
iteration, so we don't need latency between these instructions in the
same iteration, though that isn't guaranteed. I plan to handle remove
the latency for obvious cases in a followup PR.
Commit: 7917772d7d61384696c61102c08c2ea158e610fa
https://github.com/llvm/llvm-project/commit/7917772d7d61384696c61102c08c2ea158e610fa
Author: Akash Dutta <137309513+akadutta at users.noreply.github.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
Log Message:
-----------
[AMDGPU][NFC] Hoist independent condition out of loop in dependsOnLocalPhi in AMDGPUTTI (#198789)
Commit: 58de983ea7c28e1fa83add7d89d5e7b2cc6e9386
https://github.com/llvm/llvm-project/commit/58de983ea7c28e1fa83add7d89d5e7b2cc6e9386
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.td
Log Message:
-----------
[NFC] Remove trailing whitespaces in Intrinsics.td (#201472)
Commit: aa9099a47468425b6d16613e08ae84c8c77671b7
https://github.com/llvm/llvm-project/commit/aa9099a47468425b6d16613e08ae84c8c77671b7
Author: Justin Lebar <justin.lebar at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/test/Transforms/JumpThreading/noalias-scope-decl.ll
Log Message:
-----------
[JumpThreading] Clone noalias scopes in duplicateCondBranchOnPHIIntoPred (#200550)
duplicateCondBranchOnPHIIntoPred clones a block into a predecessor with
its own loop. Unlike cloneInstructions (used by threadEdge), it never
cloned the duplicated noalias scope declarations. The duplicated code
therefore shared the original's !alias.scope/!noalias MDNodes, letting
AA incorrectly treat two accesses on different paths as non-aliasing.
Fix by cloning the scopes.
Commit: 7132f8f40649ebe15f701c8103e22dead7ea8f71
https://github.com/llvm/llvm-project/commit/7132f8f40649ebe15f701c8103e22dead7ea8f71
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[NFC] Remove trailing whitespaces from llvm/docs/ReleaseNotes.md (#201478)
Commit: 96a50e0ee0959dd3095b0d3c561fab0c5f5fe94c
https://github.com/llvm/llvm-project/commit/96a50e0ee0959dd3095b0d3c561fab0c5f5fe94c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChain.cpp
M clang/test/Driver/lto.c
Log Message:
-----------
[Clang] Accept `-flto=none` similar to `-fno-lto` (#201460)
Summary:
Personal preference, but I would like to be able to set all the LTO
kinds from the string, and it feels a little odd to need to use
`-fno-lto` to override the mode.
Commit: 086f9c1e6ea3ed30345f685d9055f57f044834a7
https://github.com/llvm/llvm-project/commit/086f9c1e6ea3ed30345f685d9055f57f044834a7
Author: ovatonne <ovatonne at gmail.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M libcxx/test/std/containers/exception_safety_helpers.h
M libcxx/test/std/containers/sequences/forwardlist/exception_safety.pass.cpp
Log Message:
-----------
[libc++][tests] Add missing strong exception guarantee test coverage in forward_list (#200666)
Adds missing test coverage for exception guarantees in forward_list.
- Strong exception guarantee for forward_list::push_front and
forward_list::emplace_front.
- Exception guarantee for constructor, operator= and assign overloads
taking an initializer_list.
- Add move and inplace construction as throwing functions in test
helpers.
- Add tests throwing upon moving or constructing elements inplace for
relevant overloads.
Commit: 8a21afca17117a380f2716ae81fb402d673f48fe
https://github.com/llvm/llvm-project/commit/8a21afca17117a380f2716ae81fb402d673f48fe
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
A llvm/test/Transforms/LoopVectorize/AArch64/arith-costs.ll
R llvm/test/Transforms/LoopVectorize/AArch64/binop-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/cmp_cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
Log Message:
-----------
[LV] Add cost for VPInstruction::Not. (#198445)
This patch add the cost for VPInstruction::Not which will lower to Xor.
Commit: ff812a578f236d3554750391041146a6781a9f55
https://github.com/llvm/llvm-project/commit/ff812a578f236d3554750391041146a6781a9f55
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbtest.py
Log Message:
-----------
[lldb/test] Add _excluded_variant_combinations hook in lldbtest (#201459)
Add a module-scope hook that LLDBTestCaseFactory consults during variant
expansion so the suite can declare combinations of variant axis values
that should never be generated. Each entry in
`_excluded_variant_combinations` is a dict mapping variant_name ->
value; the helper `_is_excluded_variant_combination(method,
variant_name, value_name)` returns True when assigning the given
variant=value to the method would produce a combination matching every
entry. `_expand_test_variants` checks the predicate before generating
each copy and drops the variant entirely so excluded crosses don't
appear in the test matrix at all.
This is a suite-wide per-axis-combination analogue of
NO_DEBUG_INFO_TESTCASE: instead of collapsing the entire debug-info axis
for one test class, it lets the suite declare narrowly that any variant
carrying e.g. {"swift_module_importer": "noclang", "swift_embedded":
"swiftembed"} should be dropped, regardless of which source method or
test class generated it. Useful when a subset of the variant matrix is
known broken (or simply redundant) without resorting to broad @skipIf /
@expectedFailureAll decorators on each affected method.
The list starts empty; the first downstream consumer
(swiftlang/llvm-project) adds the noclang × swiftembed cross at the same
time it registers the swift_module_importer / swift_embedded variants.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: c10e5060490e1377a4d59cab5f8e345134d35d97
https://github.com/llvm/llvm-project/commit/c10e5060490e1377a4d59cab5f8e345134d35d97
Author: Michael Jones <michaelrj at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/CMakeLists.txt
M libc/include/inttypes.yaml
M libc/src/inttypes/CMakeLists.txt
A libc/src/inttypes/wcstoimax.cpp
A libc/src/inttypes/wcstoimax.h
A libc/src/inttypes/wcstoumax.cpp
A libc/src/inttypes/wcstoumax.h
M libc/test/src/inttypes/CMakeLists.txt
A libc/test/src/inttypes/wcstoimax_test.cpp
A libc/test/src/inttypes/wcstoumax_test.cpp
Log Message:
-----------
[libc] implement wcstoimax/wcstoumax (#200284)
Adds the implementation and tests for wide character to intmax_t and
uintmax_t.
Assisted-by: Automated tooling, human reviewed.
Commit: 2e27610b8f79c34238ffc405d3f4558945c32752
https://github.com/llvm/llvm-project/commit/2e27610b8f79c34238ffc405d3f4558945c32752
Author: Florian Mayer <fmayer at google.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/IR/BasicBlock.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
R llvm/test/Bitcode/musttail-bitcast-upgrade.ll
R llvm/test/Bitcode/musttail-bitcast-upgrade.ll.bc
M llvm/test/Instrumentation/AddressSanitizer/musttail.ll
M llvm/test/Instrumentation/ThreadSanitizer/tsan_musttail.ll
M llvm/test/Transforms/CallSiteSplitting/musttail.ll
M llvm/test/Transforms/SafeStack/X86/musttail.ll
M llvm/test/Verifier/musttail-invalid.ll
Log Message:
-----------
Revert "Remove the optional bitcast between a musttail call and its ret" (#201479)
This reverts https://github.com/llvm/llvm-project/pull/201280
This broke MSan on the buildbots:
https://lab.llvm.org/buildbot/#/builders/169/builds/23291/steps/10/logs/stdio
This is the only change in the batch that touched BitcodeReader
Commit: 0f3d6b9cac25c750f5fa477d92ba15b68b03e210
https://github.com/llvm/llvm-project/commit/0f3d6b9cac25c750f5fa477d92ba15b68b03e210
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
A llvm/include/llvm/ExecutionEngine/Orc/SymbolLookupSet.h
Log Message:
-----------
[ORC] Lift SymbolLookupSet into its own header. NFCI. (#201295)
Lifts the SymbolLookupSet class and SymbolLookupFlags enum out of Core.h
and into a new SymbolLookupSet.h header.
Commit: f0d98c3693a47679115ce05a5a5629e9b869472f
https://github.com/llvm/llvm-project/commit/f0d98c3693a47679115ce05a5a5629e9b869472f
Author: savchart <metaartem at protonmail.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/FunctionSizeCheck.cpp
M clang-tools-extra/clang-tidy/readability/FunctionSizeCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/function-size.rst
A clang-tools-extra/test/clang-tidy/checkers/readability/function-size-ignore-macros.cpp
Log Message:
-----------
[clang-tidy][readability] Ignore macros in function-size check (#199549)
This patch adds an IgnoreMacros option to the readability-function-size
check.
Fixes https://github.com/llvm/llvm-project/issues/112835
Commit: 9263a42920ea470ff7377fa3ca3b3759aeb86fa1
https://github.com/llvm/llvm-project/commit/9263a42920ea470ff7377fa3ca3b3759aeb86fa1
Author: Johannes Doerfert <jdoerfert.llvm at gmail.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M clang/test/OpenMP/amdgcn_weak_alias.c
M clang/test/OpenMP/declare_target_codegen.cpp
M clang/test/OpenMP/target_codegen.cpp
M clang/test/OpenMP/target_depend_codegen.cpp
M clang/test/OpenMP/target_indirect_codegen.cpp
M clang/test/OpenMP/target_parallel_depend_codegen.cpp
M clang/test/OpenMP/target_parallel_for_depend_codegen.cpp
M clang/test/OpenMP/target_parallel_for_simd_depend_codegen.cpp
M clang/test/OpenMP/target_simd_codegen.cpp
M clang/test/OpenMP/target_simd_depend_codegen.cpp
M clang/test/OpenMP/target_teams_depend_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_depend_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_depend_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_depend_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_depend_codegen.cpp
M llvm/include/llvm/Frontend/Offloading/Utility.h
M llvm/lib/Frontend/Offloading/Utility.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir
M mlir/test/Target/LLVMIR/omptarget-declare-target-to-host.mlir
Log Message:
-----------
[OpenMP] Use ext linkage for kernels handles and globals handles keep… (#200964)
… linkage
Host handles are now emmitted with external linkage to clash if two
kernels with the same name are registered. This could have happen right
now and silently corrupt the program, but it can happen more easily once
we allow users to name their kernels.
In the same patch we make global variable handles retain the linkage of
the global variable, forcing clashes for external ones and continue to
support weak use cases.
---------
Co-authored-by: Shilei Tian <i at tianshilei.me>
Commit: 97d72648474f2bd8832810993a31a69d28196ffe
https://github.com/llvm/llvm-project/commit/97d72648474f2bd8832810993a31a69d28196ffe
Author: Teresa Johnson <tejohnson at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/test/ThinLTO/X86/memprof-icp-recursive.ll
Log Message:
-----------
[MemProf] Change default of memprof-icp-noinline-threshold to 0 (#201474)
This is no longer needed after PR172502 added support to identify
indirect callees from inlined frames.
Commit: 84085aac175bd949c521957af88ff5cda4aeeb20
https://github.com/llvm/llvm-project/commit/84085aac175bd949c521957af88ff5cda4aeeb20
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
M mlir/test/Dialect/Linalg/roundtrip-morphism-linalg-category-ops.mlir
M mlir/test/Dialect/Linalg/roundtrip-morphism-linalg-named-ops.mlir
Log Message:
-----------
[mlir][linalg] Improve contraction specialization (#201300)
Extend the matcher to recognize additional supported boolean contraction
form(and+or). Fixes #198235.
Commit: 70256dff97f1393c0bceb6c90c0341215d2ba598
https://github.com/llvm/llvm-project/commit/70256dff97f1393c0bceb6c90c0341215d2ba598
Author: Chi-Chun, Chen <chichun.chen at hpe.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
R flang/test/Lower/OpenMP/Todo/metadirective-dynamic.f90
M flang/test/Lower/OpenMP/metadirective-user.f90
M flang/test/Semantics/OpenMP/metadirective-user.f90
Log Message:
-----------
[flang][OpenMP] Support lowering of metadirective (part 2) (#194424)
Lower non-constant `user={condition(expr)}` selectors in OpenMP
metadirectives to a runtime `fir.if` / `else` selection cascade.
Dynamic user conditions are handled in two separate phases:
- Static applicability uses only selector traits that are known at
compile time.
- Guarded ranking preserves selector specificity and dynamic-condition
scores for the path where the runtime condition evaluates to true.
Lowering first filters candidates using compile-time selector traits,
then orders the remaining candidates with the normal OpenMP variant
ranking rules. If the selected candidate has a non-constant user
condition, that condition is emitted as a `fir.if` guard. When the
condition evaluates to false, the `else` branch continues selection
among the remaining candidates.
For example:
```fortran
!$omp metadirective &
!$omp & when(user={condition(score(100): high)}: barrier) &
!$omp & when(user={condition(low)}: taskwait) &
!$omp & otherwise(nothing)
```
is selected as:
```text
if (high) barrier
else if (low) taskwait
else nothing
```
Scores attached to dynamic `condition(score(...): expr)` selectors are
preserved for the guarded candidate. As a result, those scores affect
ranking only on the runtime path where the condition is true, instead of
allowing a false runtime condition to influence unconditional selection.
This also fixes the interactions with `extension(match_any)` and
`extension(match_none)`:
- `match_any` can be satisfied by a runtime condition when no static
trait matches.
- If static traits already satisfy `match_any`, the dynamic condition
score is used only when the condition is true.
- `match_none` keeps the dynamic condition inactive for static
applicability while still preserving its score for ranking.
For example, this `match_any` selector is statically applicable through
`vendor(llvm)`, but the score on `flag` is used only when `flag`
evaluates to true:
```fortran
!$omp metadirective &
!$omp & when(implementation={extension(match_any), vendor(llvm)}, &
!$omp & user={condition(score(100): flag)}: barrier) &
!$omp & when(user={condition(score(10): .true.)}: taskwait) &
!$omp & otherwise(nothing)
```
is selected as:
```text
if (flag) barrier
else taskwait
```
The final fallback is the highest-ranked unguarded candidate, an
explicit `otherwise` / `default` clause, or implicit `nothing`.
This patch is part of the feature work for #188820 and is stacked on top
of [#193664](https://github.com/llvm/llvm-project/pull/193664).
Assisted with Copilot and GPT-5.4.
Commit: a53507fb5c108f0fd71270bf6498fa0f283b27c1
https://github.com/llvm/llvm-project/commit/a53507fb5c108f0fd71270bf6498fa0f283b27c1
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx20.cpp
Log Message:
-----------
[clang][bytecode] Fix a crash with covariant return types (#201354)
`Context::collectBaseOffset()` will assert if the passed-in classes are
the same.
Commit: 36e714b78712ef7f697d172b3ede0131568b892c
https://github.com/llvm/llvm-project/commit/36e714b78712ef7f697d172b3ede0131568b892c
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/TargetProcessControlTypes.h
M llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/ExecutorResolver.h
M llvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
M llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutorResolutionGenerator.cpp
M llvm/lib/ExecutionEngine/Orc/SelfExecutorProcessControl.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/ExecutorResolver.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleExecutorDylibManager.cpp
M llvm/tools/lli/ForwardingMemoryManager.h
M llvm/unittests/ExecutionEngine/Orc/ObjectLinkingLayerTest.cpp
Log Message:
-----------
[ORC] Replace ExecutorSymbolDef with ExecutorAddr in remote lookup. (#201492)
Update DylibManager and associated interfaces to return ExecutorAddrs
for remote symbols, rather than ExecutorSymbolDefs. No clients were
using the flags component of ExecutorSymbolDef, and this brings the
SimpleExecutorDylibManager implementation in OrcTargetProcess into
closer alignment with the NativeDylibManager implementation in the new
ORC runtime.
Commit: 4a77ce7c6f510283083dba0daccefc4d32326e44
https://github.com/llvm/llvm-project/commit/4a77ce7c6f510283083dba0daccefc4d32326e44
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SplitKit.cpp
A llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
Log Message:
-----------
[CodeGen][AMDGPU] Remove premature empty subrange elimination (#201263)
This commit removes a call to `removeEmptySubRanges` inside
`SplitEditor::rewriteAssigned` which removes empty subranges that may be
expected at a later stage. The empty subranges are eliminated by a later
call to `removeEmptySubRanges`.
Fixes https://github.com/llvm/llvm-project/issues/199337.
---------
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
Commit: c17f6208157d04b730576d84c8998f7bd8112cef
https://github.com/llvm/llvm-project/commit/c17f6208157d04b730576d84c8998f7bd8112cef
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
A llvm/test/Transforms/LoopInterchange/reduction2mem-extra-lcssa.ll
Log Message:
-----------
[LoopInterchange] Check all inner-exit LCSSA PHIs (#200860)
areInnerLoopExitPHIsSupported() returned true as soon as it saw the
reduction LCSSA PHI, skipping the user-check for any later LCSSA PHIs.
If one had a non-PHI user, legality wrongly succeeded and the transform
hit a cast<PHINode> assertion. Use continue so the remaining PHIs are
still validated.
Fixes #200811.
Commit: cdf26f6721363d542865d826dd6455d448e1e860
https://github.com/llvm/llvm-project/commit/cdf26f6721363d542865d826dd6455d448e1e860
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/div-by-constant.ll
M llvm/test/CodeGen/RISCV/srem-lkk.ll
M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
Log Message:
-----------
[RISCV] Fold (add X, (mulhs X, C)) -> (mulhsu X, C) if C is negative. (#199287)
Improves some division by constant cases.
Based on this blog post
https://needlesscomplexity.substack.com/p/implementing-division-by-multiplying
Correctness proof is sketched out in the comments.
Commit: e75e96af6987cb017f8d11efc1eed430b0d6080d
https://github.com/llvm/llvm-project/commit/e75e96af6987cb017f8d11efc1eed430b0d6080d
Author: mike-goutokuji <gfunni234 at gmail.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir
M llvm/test/CodeGen/AArch64/arm64-csel.ll
M llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
M llvm/test/CodeGen/AArch64/fcvt-i256.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/select-constant-xor.ll
Log Message:
-----------
[AArch64][GlobalISel] Port shouldBeAdjustedToZero to GlobalISel (#195941)
Commit: 4695c84c7954f0133679b76302bff13e2b059def
https://github.com/llvm/llvm-project/commit/4695c84c7954f0133679b76302bff13e2b059def
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/test/Dialect/XeGPU/invalid.mlir
M mlir/test/Dialect/XeGPU/ops.mlir
Log Message:
-----------
[MLIR][XeGPU] Extend op definitions to support 3D+: load_nd, store_nd, prefetch_nd (#199811)
**Summary**
Extend xegpu.load_nd, xegpu.store_nd, and xegpu.prefetch_nd operations
to support 3D and higher-dimensional tensor descriptors with batch
dimensions, enabling batched memory operations for workloads like [4, 8,
16] tensor loads/stores.
**Changes**
- Verifiers: Removed rank > 2 checks in LoadNdOp::verify() and
StoreNdOp::verify() to allow 3D+ tensor descriptors
- Documentation: Added comprehensive documentation explaining: Tensor
descriptors can be 1D, 2D, 3D, or higher dimensional; Batch dimensions
(leading dimensions) are unrolled to unit dimensions during lowering;
Operations execute at 2D granularity at subgroup level to match 2D block
IO hardware; Examples of 3D operations
- Tests: Added unit tests for 3D operations (load_nd_3d, store_nd_3d,
prefetch_nd_3d)
---------
Co-authored-by: Claude Sonnet 4.5 <noreply at anthropic.com>
Commit: 5f517ddd3e7c29ac51ea88a33e500455deee03a1
https://github.com/llvm/llvm-project/commit/5f517ddd3e7c29ac51ea88a33e500455deee03a1
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/test/Dialect/XeGPU/invalid.mlir
M mlir/test/Dialect/XeGPU/ops.mlir
Log Message:
-----------
[MLIR][XeGPU] Extend op definitions to support 3D+: dpas, dpas_mx (#199809)
**Summary**
Extend xegpu.dpas and xegpu.dpas_mx operations to support 3D and 4D
operands with batch dimensions, enabling batched matrix multiplication
workloads like [4, 128, 512] x [4, 512, 128] -> [4, 128, 128].
**Changes**
- Type definitions: Extended XeGPU_DpasOprType and XeGPU_DpasResType to
support rank 3-4 (previously 1-3 and 1-2)
- Op definitions: Extended dpas_mx scale operands to support rank 3-4
vectors
- Verifiers: Updated verifyDpasDimensions() to validate batch dimensions
across A, B, and result operands; updated DpasMxOp::verify() for
batch-aware scale dimension checks
- Documentation: Added comprehensive documentation explaining batch
dimensions, microarchitecture-specific matrix sizes, and 3D/4D usage
examples
- Tests: Added unit tests for 3D batched dpas and dpas_mx operations
Assisted-by-Claude
---------
Co-authored-by: Claude Sonnet 4.5 <noreply at anthropic.com>
Commit: 3192648845b87e1907377a395d626b85a7bad6ee
https://github.com/llvm/llvm-project/commit/3192648845b87e1907377a395d626b85a7bad6ee
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M orc-rt/include/orc-rt/NativeDylibManager.h
M orc-rt/lib/executor/NativeDylibManager.cpp
M orc-rt/lib/executor/Unix/NativeDylibAPIs.inc
M orc-rt/lib/executor/sps-ci/NativeDylibManagerSPSCI.cpp
M orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
M orc-rt/unittests/NativeDylibManagerTest.cpp
Log Message:
-----------
[orc-rt] Make NativeDylibManager::lookup return optional addresses. (#201519)
NativeDylibManager::lookup used to return (asynchronously) a vector of
void *s where null represented not-present. This commit updates it to
return a vector of std::optional<void *>s where std::nullopt represents
not-present and an address of zero indicates that the symbol is present
with an address of zero.
This matches the resolve semantics of SimpleExecutorDylibManager,
completing the alignment of the two implementations after the earlier
additions of the Mode argument to load() and the
required/weakly-referenced flag on lookup symbols.
Commit: 192c013865fbdc038996550e34ecc943f9b5c90e
https://github.com/llvm/llvm-project/commit/192c013865fbdc038996550e34ecc943f9b5c90e
Author: Guy David <guyda96 at gmail.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/dup.ll
Log Message:
-----------
[AArch64] Fix DUP-of-extload combine to ignore chain uses (#201351)
The original combine bailed when the load had more than one use, but
counted chain uses too.
Commit: b8cc5942b3c1b3dd56d3e37093b0c22e134fd0b0
https://github.com/llvm/llvm-project/commit/b8cc5942b3c1b3dd56d3e37093b0c22e134fd0b0
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosa.h
M mlir/lib/Conversion/TosaToSPIRVTosa/CMakeLists.txt
M mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosa.cpp
A mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaConstants.cpp
M mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaOps.cpp
M mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaPass.cpp
A mlir/test/Conversion/TosaToSPIRVTosa/graph-constant-invalid.mlir
A mlir/test/Conversion/TosaToSPIRVTosa/graph-constant-mark-invalid.mlir
A mlir/test/Conversion/TosaToSPIRVTosa/graph-constant-mark.mlir
M mlir/test/Conversion/TosaToSPIRVTosa/tosa-to-spirv.mlir
Log Message:
-----------
[mlir][spirv] Add TOSA graph constant marking (#201095)
Add a TOSA to SPIR-V TOSA preprocessing pass that marks large tosa.const
and tosa.const_shape operations for lowering to spirv.ARM.GraphConstant.
Keep small constants inline as spirv.Constant, assign graph constant IDs
with a grapharm-prefixed marker attribute, and teach the existing
constant conversion to use the marker when present.
Expose the grapharm source-side attribute names used for interface ABI
annotations and graph constant IDs.
Add tests for marking large constants, leaving small constants unmarked,
increasing graph constant IDs across mixed constants, and lowering
pre-marked constants to spirv.ARM.GraphConstant.
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: 364a8837a9d67135d050fe594ba51e319fbab938
https://github.com/llvm/llvm-project/commit/364a8837a9d67135d050fe594ba51e319fbab938
Author: ShashwathiNavada <shashwathinavada at gmail.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Flang.cpp
A flang/test/Driver/frelaxed-c-loc-checks.f90
Log Message:
-----------
[Flang] Fix -frelaxed-c-loc-checks being ignored when using the driver (#200733)
`-frelaxed-c-loc-checks` worked correctly when passed directly to -fc1,
but was silently ignored when using the driver (e.g., flang -c
-frelaxed-c-loc-checks), causing the flag to go unused. This patch fixes
it by adding `OPT_relaxed_c_loc` to the `addAllArgs` call in Flang.cpp
Also extend the existing test with a driver-mode RUN line to cover this
path.
Commit: ee1fe9431baedb216674a1452eb39aca9d3a78d9
https://github.com/llvm/llvm-project/commit/ee1fe9431baedb216674a1452eb39aca9d3a78d9
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp
M mlir/test/Dialect/Arith/emulate-wide-int.mlir
Log Message:
-----------
[mlir][arith] Use subui_extended in wide integer emulation of subi (#197762)
Commit: b8c18e9aa7f273a786a0dd09a4fcab822438e975
https://github.com/llvm/llvm-project/commit/b8c18e9aa7f273a786a0dd09a4fcab822438e975
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
Log Message:
-----------
[mlir][ArithToLLVM] Lower arith.subui_extended (#197737)
Commit: bdd7b4cc2a0c9a8c58e4025edae079ce6af73aa0
https://github.com/llvm/llvm-project/commit/bdd7b4cc2a0c9a8c58e4025edae079ce6af73aa0
Author: ShashwathiNavada <shashwathinavada at gmail.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Semantics/entry01.f90
Log Message:
-----------
[Flang][Semantics] Throw diagnostics for identical entry and result names. (#198500)
Fixes https://github.com/llvm/llvm-project/issues/198499
In flang entry name and result names cannot be same as per
[C1583](https://j3-fortran.org/doc/year/25/25-007r1.pdf).
Previously, Flang did not diagnose cases where the ENTRY name and RESULT
name were identical, e.g.
```
function m1f1()
integer :: m1f1
real :: m1f1e1
m1f1 = 0
entry m1f1e1() result(m1f1e1)
m1f1e1 = 0.1
end function
```
Commit: 96c0f5ad27abba13bc941df99686fdb8c7b59fff
https://github.com/llvm/llvm-project/commit/96c0f5ad27abba13bc941df99686fdb8c7b59fff
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M lldb/include/lldb/Target/Memory.h
M lldb/include/lldb/Target/Process.h
M lldb/source/Target/Memory.cpp
M lldb/source/Target/Process.cpp
M lldb/unittests/Target/MemoryTest.cpp
Log Message:
-----------
[lldb] Use MemoryCache in Process::ReadRangesFromMemory (#201166)
There are scenarios (especially in the ObjectiveC metadata reading) in
which multiple strings are read over and over again, but through
different code paths. In order to make that part of the code use
MultiMemRead effectively, the memory cache must be integrated into
ReadRangesFromMemory before we can migrate the string reading to
vectorized version.
Commit: 375fa6fb02035afc8719e8484f0c914a96987fd8
https://github.com/llvm/llvm-project/commit/375fa6fb02035afc8719e8484f0c914a96987fd8
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Analysis/Loads.cpp
M llvm/test/Analysis/ValueTracking/memory-dereferenceable.ll
Log Message:
-----------
[Loads] Use willNotFreeBetween() for dereferenceable-at-point (#201353)
If dereferenceable-at-point semantics are enabled, use
willNotFreeBetween() to check whether frees are known to not occur
between the definition point of the value and the context instruction.
We already use this logic for dereferenceable assumptions, this enables
it for other dereferenceability fact (under deref-at-point).
Commit: f02dd4afbac15705016a9a7962d87161524b66cc
https://github.com/llvm/llvm-project/commit/f02dd4afbac15705016a9a7962d87161524b66cc
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M clang/test/CodeGen/ms-intrinsics-other.c
M llvm/lib/Analysis/CaptureTracking.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sincos.ll
M llvm/test/Transforms/Attributor/nofpclass.ll
M llvm/test/Transforms/Attributor/nonnull.ll
M llvm/test/Transforms/Attributor/nosync.ll
M llvm/test/Transforms/FunctionAttrs/atomic.ll
M llvm/test/Transforms/FunctionAttrs/initializes.ll
M llvm/test/Transforms/FunctionAttrs/nocapture.ll
M llvm/test/Transforms/FunctionAttrs/nofpclass.ll
M llvm/test/Transforms/FunctionAttrs/nonnull.ll
M llvm/test/Transforms/FunctionAttrs/readattrs.ll
M llvm/test/Transforms/FunctionAttrs/writeonly.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll
M llvm/test/Transforms/PhaseOrdering/branch-dom-cond.ll
Log Message:
-----------
[CaptureTracking] Volatile operations only capture address (#201316)
The fact that a volatile access was performed on a certain address is an
observable effect in the abstract machine, so volatile operations
capture the address of the accessed pointer. However, they do not
capture the provenance. This matches what we document in LangRef.
While I'm pretty sure that this models the semantics correctly, I'm
slightly concerned that we might be using the provenance capture here to
paper over some other issue, though nothing specific comes to mind (and
the test changes don't show anything problematic).
Commit: 73802c2e9d102a4fb646bc039754779fca3ea476
https://github.com/llvm/llvm-project/commit/73802c2e9d102a4fb646bc039754779fca3ea476
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
A offload/test/offloading/array_reductions.cpp
M offload/test/offloading/multiple_reductions.cpp
Log Message:
-----------
[OpenMP][offload] Add enhanced array-reduction tests (#201040)
Commit: 601958395ae7f24c74d85fcda2829e102e4176f0
https://github.com/llvm/llvm-project/commit/601958395ae7f24c74d85fcda2829e102e4176f0
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.h
M llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[NFC][GlobalISel] Refactor ownership of InstructionMatchers (#200798)
- Clarify that the array of InstructionMatchers in the RuleMatcher are
for the roots only.
- Let RuleMatcher own all of the InstructionMatcher used for/by
predicates.
They are all kept in an array in which the index of the
InstructionMatcher is equal to its
InsnID, which eliminates some redundant tracking.
- Remove duplicate tracking of InsnID from RuleMatcher;
InstructionMatcher does it on its own already.
Co-authored-by: Pierre-vh <29600849+Pierre-vh at users.noreply.github.com>
Commit: b6599484337145cd03cdc42b30de08939e3f6947
https://github.com/llvm/llvm-project/commit/b6599484337145cd03cdc42b30de08939e3f6947
Author: Amr Hesham <amr96 at programmer.net>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/test/CIR/CodeGen/complex-atomic-cast.c
Log Message:
-----------
[CIR] Fix Complex Casting with Atomic qualifier (#201424)
Apply Complex Casting with Atomic qualifier fixes from PRs #172210 and
#172163
Issue https://github.com/llvm/llvm-project/issues/192331
Commit: b12cd6aa2faac1af50ee332c30a3e863dc462d7d
https://github.com/llvm/llvm-project/commit/b12cd6aa2faac1af50ee332c30a3e863dc462d7d
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCClassDescriptorV2.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCClassDescriptorV2.h
Log Message:
-----------
[lldb] Use batched memory reads in ClassDescriptorV2::relative_list_entry_t (#201284)
This reduces the number of memory reads performed when reading Objective
C classes metadata.
Note: these addresses are indeed sequential (with a small offset between
them), but there are so many of them that they would not fit into a
single Process::ReadMemory cache line, so this is still a win, and it
also puts the code into the right shape for vectorizing the next read in
the same loop, which will see the biggest savings.
Commit: ca085afb41ab167597e76daf732b4f5a6eb36298
https://github.com/llvm/llvm-project/commit/ca085afb41ab167597e76daf732b4f5a6eb36298
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
A llvm/test/CodeGen/X86/freeze-fp.ll
M llvm/test/CodeGen/X86/freeze-vector.ll
M llvm/test/CodeGen/X86/madd.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
Log Message:
-----------
[SelectionDAG] Pre-commit tests for dagcombine improvements (#201270)
I've got a stack of dagcombine improvements that together make an
infinite cycle relating to freeze insertion in vector-manipulation IR.
Here we have
- Handling freeze(undef) in demanded-elts for shufflevector
- Improvements to noundef checks for bitcast, concat, and select
- Improvements to extract(concat), extract(extract), and extract(insert)
handling
Even though the regression I'm fixing is an AMDGPU one, these tests are
mainly X86 because the AMDGPU calling convention makes it hard to
demonstrate the folds I'm adding.
AI note: I got an LLM to find most of these tests, especially some of
the fiddly ones that needed control flow.
Commit: b0cb331995d494dda75d5fd967e160ec0c32caf1
https://github.com/llvm/llvm-project/commit/b0cb331995d494dda75d5fd967e160ec0c32caf1
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/BracesAroundStatementsCheck.cpp
M clang-tools-extra/clang-tidy/utils/BracesAroundStatement.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/readability/braces-around-statements-same-line.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/braces-around-statements.cpp
Log Message:
-----------
[clang-tidy] Avoid brace fix-it crash in macro body expansion (#198788)
`readability-braces-around-statements `could assert when diagnosing an
unbraced statement that ends in the middle of a macro body expansion. It
would be hard/unsafe to give fix-its for such cases, so treat them as
diagnostic-only.
Closes https://github.com/llvm/llvm-project/issues/198711
Commit: 6fd4b82f8985b4d86ba190781f132832637e8642
https://github.com/llvm/llvm-project/commit/6fd4b82f8985b4d86ba190781f132832637e8642
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-usabs.ll
Log Message:
-----------
[LV] Optimize partial reduction extends before handling inloop subs (#199665)
The crash avoided in #194660 was caused by the extend optimizations
failing to match as due to the extra sub/negation added to the
"ExtendedOp".
A similar crash exists for [us]abs partial reductions (see
https://godbolt.org/z/MerMon5rE), which is fixed with this patch.
This patch solves the underlying issue by running the extend
optimizations before any inloop sub/fsub handling.
Fixes #194000
Commit: 808b9e58c651486eee2e297b8814de90254082a2
https://github.com/llvm/llvm-project/commit/808b9e58c651486eee2e297b8814de90254082a2
Author: KRM7 <rugasikrisztian at gmail.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
Log Message:
-----------
[GlobalISel] Combine sext(load), zext(load) patterns when the load has multiple uses (#182831)
Extend the existing combiners for sext(load), zext(load) patterns to also work when the load has multiple uses.
Commit: d226dcc019d6a83cba79951ec2a8a08c53a57858
https://github.com/llvm/llvm-project/commit/d226dcc019d6a83cba79951ec2a8a08c53a57858
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
A llvm/test/CodeGen/NVPTX/insert-vector-elt-bitcast-legalize.ll
Log Message:
-----------
[NVPTX] Fix illegal combineInsertEltToShuffle pattern (#198259)
Adds a condition to the `isShuffleMaskLegal` method to prevent
`combineInsertEltToShuffle` from creating an illegal `vector_shuffle`
after type legalization which leads to a crash.
Context:
This is triggered when bitcasting a `v2f16` into a vector that type
legalizes to a `v2i32`. This happens on architectures supporting packed
`f32` operations (>= `sm_100`). In certain cases, this leads to
`combineInsertEltToShuffle` creating a vector shuffle with `v4f16` for
simplification. Since this happens after type legalization and `v4f16`
is an illegal type, it leads to a crash.
Commit: 3112581e2945ed5027360387f0ddcb72115f3886
https://github.com/llvm/llvm-project/commit/3112581e2945ed5027360387f0ddcb72115f3886
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/test/Dialect/Tosa/constant_folding.mlir
Log Message:
-----------
[mlir][tosa] Improve folder conformance to TOSA specification (#200223)
This commit fixes some bugs in TOSA folders that cause non-conformant
results. The fixes include:
- tosa.intdiv - Folding when the lhs and rhs are zero. In the TOSA
specification this is undefined behaviour.
- tosa.div_ceil_shape/tosa.div_floor_shape - Folding when the lhs is
negative or the rhs is non-positive. In the TOSA specification this is
undefined behaviour.
In addition, some test cases have been added for non-exercised code
paths, including:
- tosa.intdiv - Rejects overflow cases
- tosa.greater/tosa.greater_equal/tosa.equal - Correctly evaluates NaN
cases to False.
- tosa.cast - Saturating rounding when input is out of range of the
output type.
- tosa.mod_shape - Rejects cases where lhs is negative or rhs is
non-positive.
Commit: c88cefb9f13ee2a448e06f75e98fe01d8a0bcb60
https://github.com/llvm/llvm-project/commit/c88cefb9f13ee2a448e06f75e98fe01d8a0bcb60
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M libcxx/include/__memory/unique_ptr.h
Log Message:
-----------
[libc++] Simplify unique_ptr constructor SFINAE (#201305)
This patch does a couple of things:
- inline aliases to `__enable_if_t`s, making it easier to understand
what's actually going on
- make the `enable_if`s dependent via a `class _Deleter = deleter_type`
instead of a `bool` and `__dependent_type`, reducing the number of
instantiated classes
- remove `__unique_ptr_deleter_sfinae`
Commit: b09fceba26bf6d34465821460deb40b3834cf50f
https://github.com/llvm/llvm-project/commit/b09fceba26bf6d34465821460deb40b3834cf50f
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
A llvm/test/Transforms/LoopFusion/peel-preserve-lcssa.ll
Log Message:
-----------
[LoopFusion] Reform LCSSA after peelFusionCandidate's peelLoop (#200442)
peelLoop's internal simplifyLoop call requires LCSSA to be preserved
across it, but the cloned exit edges and cloned defs that peelLoop
introduces are not reflected in the existing LCSSA phis, so the contract
cannot be honoured. Pass PreserveLCSSA=false to peelLoop here and reform
LCSSA on the affected nest immediately afterward. LCSSA is expected
before and after peel+fuse, just not during it.
Caught by yarpgen fuzzing of clang -O3 -fexperimental-loop-fusion -mllvm
-loop-fusion-peel-max-count=8 on AArch64.
Fixes #199418
Commit: b66b10e852ea3bcb4a35ff83c781bf875ed50870
https://github.com/llvm/llvm-project/commit/b66b10e852ea3bcb4a35ff83c781bf875ed50870
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M clang/test/CodeGenCUDA/amdgpu-atomic-ops.cu
M clang/test/CodeGenCUDA/managed-var.cu
M clang/test/CodeGenHIP/builtins-amdgcn-vi-f16.hip
M clang/test/CodeGenHLSL/BasicFeatures/AggregateSplatCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/ArrayElementwiseCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/InitLists.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/MatrixSplat.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/OutputArguments.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/StructElementwiseCast.hlsl
M clang/test/CodeGenHLSL/Operators/logical-not.hlsl
M clang/test/CodeGenHLSL/builtins/acos-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/asin-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/atan-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/atan2-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/atan2-overloads_mat.hlsl
M clang/test/CodeGenHLSL/builtins/ceil-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/cos-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/cosh-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/degrees-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/dot2add.hlsl
M clang/test/CodeGenHLSL/builtins/exp-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/exp2-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/floor-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/frac-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/lerp-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/log-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/log10-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/log2-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/normalize-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/pow-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/radians-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/round-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/rsqrt-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/sin-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/sinh-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/sqrt-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/step-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/tan-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/tanh-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/trunc-overloads.hlsl
M clang/test/CodeGenHLSL/resources/Texture2D-GetDimensions.hlsl
M clang/test/Headers/__clang_hip_math.hip
M clang/test/Headers/openmp_device_math_isnan.cpp
M clang/test/SemaHLSL/VectorOverloadResolution.hlsl
M llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/Operator.h
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Operator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Assembler/fast-math-flags.ll
M llvm/test/Bitcode/compatibility.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
M llvm/test/CodeGen/AMDGPU/divrem24-assume.ll
M llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
M llvm/test/Transforms/InstCombine/log-pow.ll
Log Message:
-----------
[IR] Add fast-math support to {u,s}itofp (#198470)
- `{u,s}itofp` are floating point typed values.
- CodeGen part (foldFPToIntToFP in DAGCombiner) needs `nsz` to fold
pattern (uitofp (fptoui x)) -> (trunc x).
- LLVM has intrinsic variants of `{u,s}itofp`, which already support
fast-math flags.
Now optimization flags require 9 bits in bitcode, fast-math flags of
`uitofp` are stored in high 8 bits.
VPlan part may need some extra work, it assumes optimization flags from
different categories are disjoint.
Commit: 7da29bc529d74d327804ad25e49e0cdeccfed263
https://github.com/llvm/llvm-project/commit/7da29bc529d74d327804ad25e49e0cdeccfed263
Author: Liao Chunyu <chunyu at iscas.ac.cn>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
A llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/MC/RISCV/rvv/zvfqwdota8f.s
A llvm/test/MC/RISCV/rvv/zvfwdota16bf.s
A llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV][MC] Support experimental Zvdota Family instructions (#195069)
Spec:
https://github.com/aswaterman/riscv-misc/blob/main/isa/ldot-bdot/ldot-bdot.adoc
---------
Co-authored-by: Brandon Wu <songwu0813 at gmail.com>
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: 1960c7a9fdf2fc613a148fbc078173adddd6ca13
https://github.com/llvm/llvm-project/commit/1960c7a9fdf2fc613a148fbc078173adddd6ca13
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/cxx23.cpp
Log Message:
-----------
[clang][bytecode] Reject erroneous vector conversions (#201368)
Commit: 8557b5714bca181906118a86d8152598f525fcc7
https://github.com/llvm/llvm-project/commit/8557b5714bca181906118a86d8152598f525fcc7
Author: Jacob Crawley <jacob.crawley at arm.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
A llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll
A llvm/test/CodeGen/AArch64/sve-frintz.ll
M llvm/test/CodeGen/AMDGPU/fptoui_uitofp.ll
Log Message:
-----------
[DAG] Fold INT_TO_FP( FP_TO_INT (x) ) to FTRUNC(X) (#198477)
Extends the `foldFPToIntToFP` DAG Combine so that it can now be applied
when `FTRUNC` has a custom lowering, and given that `INT_TO_FP
(FP_TO_INT (X))` is not already legal.
On AArch64 targets with SVE, this change simplifies the codegen of
`INT_TO_FP (FP_TO_INT (X))` conversions by making use of the `frintz`
instruction.
Commit: 6b13656fd8386f979e061cc97e32b607ee3fcdf4
https://github.com/llvm/llvm-project/commit/6b13656fd8386f979e061cc97e32b607ee3fcdf4
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/include/bolt/Passes/LongJmp.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Passes/BinaryPasses.cpp
M bolt/lib/Passes/LongJmp.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/lib/Target/AArch64/CMakeLists.txt
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
M bolt/lib/Utils/CommandLineOpts.cpp
M bolt/test/AArch64/compare-and-branch-inversion.S
M bolt/unittests/Core/CMakeLists.txt
M bolt/unittests/Core/MCPlusBuilder.cpp
Log Message:
-----------
[BOLT][AArch64] Transform cmpbr ~> cmp + br when inversion not possible (#185731)
When reordering blocks we may have to invert branches. Sometimes this
isn't possible for compare-and-branch instructions because the immediate
value would overflow/underflow after the adjustment. In such cases I am
splitting the instruction into a compare followed by a branch. For this
to be legal we should be sure that the condition flags are not being
clobbered. Liveness analysis may help here.
Commit: bd209f39b43f958a1ac338c338a9a9538751b2fe
https://github.com/llvm/llvm-project/commit/bd209f39b43f958a1ac338c338a9a9538751b2fe
Author: wanglei <wanglei at loongson.cn>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
A llvm/test/CodeGen/LoongArch/pr198339.ll
Log Message:
-----------
[LoongArch] Fix FP_EXTEND legalization for v2f32 (#201260)
FP_EXTEND may reach ReplaceNodeResults due to a Custom action for
v2f32 results, but no target-specific lowering is required.
Fixes #198339
Commit: d83abac82bd290e16a38ab79f6207f0bc3a07b3c
https://github.com/llvm/llvm-project/commit/d83abac82bd290e16a38ab79f6207f0bc3a07b3c
Author: Barbara Mitic <bmitic at amd.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/test/Transforms/InstCombine/AMDGPU/wave-shuffle-patterns.ll
Log Message:
-----------
[AMDGPU][InstCombine] Match ds_swizzle rotate mode for cyclic lane shuffles (#199004)
Follow-up to 17cc4f77109d [AMDGPU][InstCombine] Optimize constant
shuffle patterns (#192246).
Adds matchDsSwizzleRotatePattern to recognise shuffles of the form
dst_lane = (src_lane + N) % 32 (N in [1, 31]) and lower them to a single
ds_swizzle with rotate-mode encoding (ROTATE_MODE_ENC | N << 5),
available on GFX9+. The bitmask mode cannot express such rotations since
the carry between bit positions makes the per-bit mapping
non-independent. On wave64 the pattern is accepted only when
hasPeriodicLayout<32> confirms both 32-lane groups rotate by the same
amount. Wave32-only ID forms (mbcnt.lo alone) are correctly rejected on
wave64 targets.
Co-authored-by: Barbara Mitic <Barbara.Mitic at amd.com>
Commit: faf4728454f57e93530a1ce4fa6f6ca2192e8afb
https://github.com/llvm/llvm-project/commit/faf4728454f57e93530a1ce4fa6f6ca2192e8afb
Author: ioana ghiban <ioana.ghiban at arm.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M mlir/include/mlir/Conversion/MemRefToEmitC/MemRefToEmitC.h
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitCPass.cpp
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-dealloc.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-failed.mlir
Log Message:
-----------
[mlir][EmitC] Convert MemRef::DeallocOp (#194591)
Add `memref.dealloc` lowering to EmitC by mapping pointer-backed
deallocations to `void*` cast + `free()` call. This complements the
existing `memref.alloc` lowering to `malloc()` / `aligned_alloc()` and
ensures the pass emits the required standard library include when
`free()` is used.
Assisted-by: Codex (refine implementation + tests). I reviewed all code
and tests before submission.
Commit: 5c2565b67d086a3f56ce837424402084c37c7895
https://github.com/llvm/llvm-project/commit/5c2565b67d086a3f56ce837424402084c37c7895
Author: lijinpei-amd <jinpli at amd.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/include/llvm/IR/IRBuilder.h
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
A llvm/test/Transforms/InstCombine/gep-canonicalize-index-constfold.ll
Log Message:
-----------
[InstCombine] Fix assertion in GEP exact div/shr index canonicalization (#201431)
When canonicalizing the index of `(gep ptr, (div/shr exact X, C))`,
visitGetElementPtrInst builds the new index with Builder.CreateBinOp and
then sets the exact flag via
`cast<BinaryOperator>(NewOp)->setIsExact()`. If X is a constant (as can
be proved during InstCombine), the folding builder constant-folds NewOp
to a non-BinaryOperator, so the cast asserts.
Fix this by adding a CreateExactBinOp API, so the exact flag is set on creation.
Fixes #190324.
Commit: ed4ed6f41e94e24035e07406af737502a8e149a6
https://github.com/llvm/llvm-project/commit/ed4ed6f41e94e24035e07406af737502a8e149a6
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.h
M llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[GlobalISel] Do not depend on the RuleMatcher at MatchTable emission (#200799)
Some PredicateMatchers/MatchAction/OperandRenderers relied on accessing
RuleMatcher at emission as a crutch.
Instead, make these classes collect all necessary information in the
constructor so the `emit` methods don't depend on RuleMatcher anymore.
The primary motivation for this is that I've been looking at ways to
optimize the MatchTable better,
and the fact that Predicates/Actions/Renderers are not "pure" objects,
in the sense that they keep
accessing a bunch of data all over the place even as late as emission,
was a consistent pain.
This is NFCI. There are no changes to any of the match table for
AMDGPU/AArch64 in this patch.
This patch has a bunch of noise due to function signature changes so
I'll highlight the following interesting changes:
- `SameOperandMatcher` needed a bit of an update in its
`canHoistOutsideOf` function. I had to rewrite it
but I think the end result is the same.
- `EraseInstAction` has been updated as well, and its users in both
Combiner/ISel backends have been updated to.
Instead of ignoring this action if the Inst was already erased, it's now
the responsibility of the
builder to never insert it in the first place. `BuildMIAction` had a
small update because of that too.
Assisted-By: Claude Sonnet 4.6
Context-of-Use: I used Claude to mass-remove the `RuleMatcher&`
arguments from the `emitPredicateOpcode`
methods. It did not write any logic.
Co-authored-by: Pierre-vh <29600849+Pierre-vh at users.noreply.github.com>
Commit: 7a008c0ad92a434e3bd419f4bb1c94ce85c56844
https://github.com/llvm/llvm-project/commit/7a008c0ad92a434e3bd419f4bb1c94ce85c56844
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
M clang/test/Analysis/Checkers/WebKit/call-args.cpp
Log Message:
-----------
[alpha.webkit.UncountedCallArgsChecker] Protect the const member getter's this argument (#201147)
This PR fixes a bug that when a const member variable getter is
detected, we don't check if its object argument is kept alive for the
duration of the function call.
Commit: 4590ef3017290cd2bb7eeadf14c23fe0c6d5128f
https://github.com/llvm/llvm-project/commit/4590ef3017290cd2bb7eeadf14c23fe0c6d5128f
Author: Abhinav Garg <abhinav.garg at amd.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform.mir
Log Message:
-----------
[AMDGPU][Uniformity Analysis] Marking G_DYN_STACKALLOC AlwaysUniform in uniformity analysis (#200390)
Mark G_DYN_STACKALLOC as AlwaysUniform.
The result of G_DYN_STACKALLOC is always derived from the wave-uniform
stack pointer and wave-wide max reduce alloca size hence its always uniform.
Commit: ab478d9c57547e96e9b5db2621ac2d913bec6ab8
https://github.com/llvm/llvm-project/commit/ab478d9c57547e96e9b5db2621ac2d913bec6ab8
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/early_exit_costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/f128-fmuladd-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-scalable-vectorization-always.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fully-unrolled-cost.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reg-pressure-spills.ll
M llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/WebAssembly/memory-interleave.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-ptradd-with-replicated-operand.ll
M llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll
M llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/interleave_vec.ll
Log Message:
-----------
[LV] Implement integer part of VPDerivedIV cost model (#198252)
Adds support for InductionDescriptor::IK_IntInduction variants of
inductions in VPDerivedIVRecipe::computeCost. Designing a cost model for
this recipe is tricky because it gets expanded in expandVPDerivedIV into
smaller individual recipes that will then be folded by simplifyRecipe.
Effectively the cost model has to guess how these will be folded
otherwise the costs will be too pessimistic. For example, 'add i32 %x,
0' and 'mul i32 %x, 1' should both be treated as zero cost since all
uses will be replaced with '%x'. Similarly,
'mul i32 %x, 4' will be converted to 'shl i32 %x, 2', and 'mul i32 %x,
-1' will be simplified to 'sub i32 0, %x'.
As can be seen by this PR, it's important to have non-zero costs for
cases where VPDerivedIVRecipe recipes will end up with non-foldable
instructions. Some of the tests now favour wider VFs to cover the
non-zero cost, or in other cases we prefer not to vectorise at all. I've
added loop attributes in some places to maintain the previous
vectorisation behaviour so that we're still matching the intent of the
test.
I built the LLVM test suite and I couldn't find any cases where we use
more than the first lane of the result so for now I maintained the
original behaviour and returned 0. The other induction types (pointers,
floating point values) are also left as returning 0 for now. These will
be handled in future PRs.
Commit: 6a68bd8892d9bbfaba3847fb48da78a8923fe144
https://github.com/llvm/llvm-project/commit/6a68bd8892d9bbfaba3847fb48da78a8923fe144
Author: adeshcom14 <aadikane at amd.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Log Message:
-----------
[AMDGPU][GIsel] Replace old C type castings with safer C++ (#201505)
AMDGPURegisterBankInfo.cpp still contains the old C style castings to int type which can be switched to much safer C++ variants.
Commit: 76b035c3b00e072334f6f516b0ccb31140f5975f
https://github.com/llvm/llvm-project/commit/76b035c3b00e072334f6f516b0ccb31140f5975f
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
A llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-hoisting-cxx.td
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.h
M llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
Log Message:
-----------
[GlobalISel] Do not use recordsOperand() to check if a Combiner C++ predicate can be hoisted (#200815)
The combiner does not use RecordNamedOperand, so assume that any operand
is "recorded" in the sense that can be used by a C++ predicate.
Commit: 31f0e25074627bd081130f81ba6ffcb0ede1aaab
https://github.com/llvm/llvm-project/commit/31f0e25074627bd081130f81ba6ffcb0ede1aaab
Author: dong jianqiang <dongjianqiang2 at huawei.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/test/CodeGen/ARM/elf-preemption.ll
A llvm/test/CodeGen/ARM/weak-hidden-pic.ll
Log Message:
-----------
[ARM] Use GOT indirection for weak symbols in PIC mode (#198577)
On ARM ELF PIC, weak dso_local symbols were incorrectly accessed via
PC-relative constant pool entries (e.g. .long xxx-(.LPC+8)). The
assembler eagerly resolves this expression when both the symbol and
label are in the same section, preventing the linker from overriding a
weak definition with a strong one from another object file.
Fix #183916 by treating weak symbols as indirect (requiring GOT) on ELF
PIC, matching GCC's behavior. This affects:
- isGVIndirectSymbol (ARMTargetMachine) — Darwin, GlobalISel, stack
prot.
- isGVInGOT (ARMSubtarget)
- LowerGlobalAddressELF (SelectionDAG path)
- ARMLowerPICELF (FastISel path)
Assisted-by: Claude Opus 4.7 <noreply at anthropic.com>
Commit: 36a1b5156e94f2c07ee8eeabe710ab99fc1a5489
https://github.com/llvm/llvm-project/commit/36a1b5156e94f2c07ee8eeabe710ab99fc1a5489
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
Log Message:
-----------
clang: Remove hacky OpenMP handling for appending bound arch (#201555)
Use the same path as CUDA/HIP and stop doing a hacky search through
the arguments looking for -march.
Commit: 5fe1bf6c1987c3e5e38e4ba31fe26d2415d18002
https://github.com/llvm/llvm-project/commit/5fe1bf6c1987c3e5e38e4ba31fe26d2415d18002
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/test/Transforms/FunctionAttrs/nocapture.ll
Log Message:
-----------
[FunctionAttrs] Switch readonly etc inference to use CaptureTracking (#201136)
Inference of memory attributes on arguments also needs to reason about
indirect accesses via captures and implemented a home-grown variant of
CaptureTracking for that purpose. Switch it to the shared
implementation, which slightly improves precision.
Commit: 03127a03860b9d8cb440fe8f51c00647f45eb8be
https://github.com/llvm/llvm-project/commit/03127a03860b9d8cb440fe8f51c00647f45eb8be
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/extern.cpp
Log Message:
-----------
[clang][bytecode] Fix a diagnostic difference with extern variables (#201369)
If the extern variable is constexpr of of non-array type, we should
diagnose it as missing an initializer. Otherwise, we diagose a read of
non-constexpr variable.
Commit: 37f8a85dbcb70cd87471a4bf388d0d85fa105105
https://github.com/llvm/llvm-project/commit/37f8a85dbcb70cd87471a4bf388d0d85fa105105
Author: John Brawn <john.brawn at arm.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
A llvm/test/Transforms/LoopStrengthReduce/AArch64/use-outside-loop.ll
Log Message:
-----------
[LSR] Narrow search space by merging users outside and inside loop (#185929)
Loop Strength Reduce can give different (and worse) results for a loop
when it is followed by uses of variables used inside the loop. This is
because the uses outside the loop increase the size of the search space,
which can lead to using NarrowSearchSpaceByPickingWinnerRegs which often
discards the best solution.
Solve this by narrowing the search space by merging uses outside the
loop with uses inside the loop. This ignores the Kind and AccessTy of
the use which can mean that the cost may be inaccurate, but it will give
the same cost as if we had just ignored the uses outside of the loop.
Commit: 4d2a670ba868a75103424ff3203f443391d55b1b
https://github.com/llvm/llvm-project/commit/4d2a670ba868a75103424ff3203f443391d55b1b
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/test/Transforms/FunctionAttrs/2009-01-02-LocalStores.ll
M llvm/test/Transforms/FunctionAttrs/nofree.ll
M llvm/test/Transforms/FunctionAttrs/optnone.ll
M llvm/test/Transforms/FunctionAttrs/out-of-bounds-iterator-bug.ll
Log Message:
-----------
[FunctionAttrs] Regenerate test checks (NFC) (#201576)
Commit: 5e0b3c94aed2d5127843e7e5eb7f1b23eb5ca876
https://github.com/llvm/llvm-project/commit/5e0b3c94aed2d5127843e7e5eb7f1b23eb5ca876
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
Log Message:
-----------
[X86] Add test coverage for #199445 (#201564)
Commit: 9de6f9e7c8d1faabf7e7e49ba49e6d6f3af21373
https://github.com/llvm/llvm-project/commit/9de6f9e7c8d1faabf7e7e49ba49e6d6f3af21373
Author: Jan André Reuter <j.reuter at fz-juelich.de>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M offload/libomptarget/OpenMP/API.cpp
Log Message:
-----------
[Offload][libomptarget] Replace slow `omp_target_memset` implementation by `dataFill` (#200202)
`omp_target_memset` was initially implemented before the existance of
`offload`. Because of this, a slow path was chosen to implement
`omp_target_memset`, first allocating memory on the host, calling
`memset` on that memory, and then transferring this to the device.
Aside from the inefficient way of setting device memory, this also
causes a data transfer event for the OpenMP Tools Interface, interfering
with the added memset event in OpenMP v6.0.
Since offload implements setting data via `dataFill` by now, replace the
slow path by just calling `dataFill` instead. This resolves both the
inefficiency, and removes the superfluous event dispatched to a tool.
Signed-off-by: Jan André Reuter <j.reuter at fz-juelich.de>
Commit: 3a1d8a8db2645a2a62b4f13916e2ba6e639a7fad
https://github.com/llvm/llvm-project/commit/3a1d8a8db2645a2a62b4f13916e2ba6e639a7fad
Author: Vassil Vassilev <v.g.vassilev at gmail.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M clang/include/clang/Interpreter/Value.h
M clang/lib/Interpreter/InterpreterValuePrinter.cpp
M clang/lib/Interpreter/Value.cpp
M clang/unittests/Interpreter/InterpreterTest.cpp
Log Message:
-----------
[clang-repl] Fix Value::setRawBits unit confusion and right-size raw storage. (#200886)
Value::setRawBits had inconsistent units: the default value and the size
assert treated the parameter as bytes (sizeof(Storage)), while the
memcpy treated it as bits (NBits / 8). A caller passing the natural byte
count (e.g. sizeof(long long)) ended up copying only sizeof(T)/8 bytes
-- one byte for an 8-byte payload, leaving the rest stale. The one
in-tree caller compensated by multiplying by 8, hiding the bug.
Rename the parameter to NBytes and drop the / 8 so the API name,
default, assert, and memcpy all agree on bytes. Update the caller in
InterpreterValuePrinter.cpp to pass ElemSize directly.
Right-size the Storage::m_RawBits array while we are here: it was
sizeof(long double) * 8 bytes, which reads like a bit/byte confusion
since the widest typed member of the union is long double itself. The
oversized array made sizeof(Value) ~144 bytes on x86_64 instead of ~40,
bloating every copy/move of a Value.
Add a regression test exercising setRawBits with both an explicit byte
count and the default argument. Pre-fix the test fails for both: the
explicit-count branch copies 1 byte instead of 8, and the default branch
copies sizeof(Storage)/8 bytes instead of the full union width.
Commit: 48f20c86d0fe594bdb3a5633cb11e19829211ec4
https://github.com/llvm/llvm-project/commit/48f20c86d0fe594bdb3a5633cb11e19829211ec4
Author: sujianIBM <Jian.Su at ibm.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/utils/lit/tests/lit.cfg
M llvm/utils/lit/tests/shtest-cat.py
M llvm/utils/lit/tests/shtest-format.py
M llvm/utils/lit/tests/shtest-output-printing.py
Log Message:
-----------
[z/OS] Modify regex in error message to match on z/OS. (#194020)
This PR modifies regex in error message to match on z/OS:
```
[Errno 129] EDC5129I No such file or directory.: 'temp1.txt'
wc: file "missing-file": EDC5129I No such file or directory.
cat: does-not-exist: EDC5129I No such file or directory.
```
Commit: 3e447333fe327854484fa5b4c75210fdf04cb369
https://github.com/llvm/llvm-project/commit/3e447333fe327854484fa5b4c75210fdf04cb369
Author: Ádám Kallai <kadam at inf.u-szeged.hu>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Profile/DataAggregator.cpp
M bolt/lib/Utils/CommandLineOpts.cpp
M bolt/unittests/Core/MemoryMaps.cpp
M bolt/unittests/Profile/CMakeLists.txt
A bolt/unittests/Profile/PerfScripts.cpp
M bolt/unittests/Profile/PerfSpeEvents.cpp
Log Message:
-----------
[BOLT] Add pre-parsed perf script support (#163785)
Implement the functionality to read and parse a pre-parsed perf-script
profile generated by perf2bolt's '--profile-format=perfscript' option.
The '-ps' option defines the perfscript input profile format. It requires
specifying the aggregation type ('--spe', '--ba') if it differs from
the default one ('brstack'). Note that the profile has to also be generated
using the exact same aggregation type.
Examples:
For ARM SPE:
1) $ perf2bolt BINARY -p perf.data -o test.text --spe --profile-format=perfscript
2) $ perf2bolt BINARY -o test.fdata -p test.text --spe -ps
For Brstack aggregation:
1) $ perf2bolt BINARY -p perf.data -o test.text --profile-format=perfscript
2) $ perf2bolt BINARY -o test.fdata -p test.text -ps
Commit: 07e081dcd784f3286ed9aa1ac549beb61066ce97
https://github.com/llvm/llvm-project/commit/07e081dcd784f3286ed9aa1ac549beb61066ce97
Author: Ariel-Burton <arielburton at yahoo.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M clang/test/DebugInfo/CXX/line.cpp
Log Message:
-----------
Fix clang/test/DebugInfo/CXX/line.cpp (#198401)
This PR twaeks the clang/test/DebugInfo/line.cpp test to pass on z/OS.
The reason the test was failing is that the RUN lines which specify
-triple %itanium_abi_triple expands to s390x-ibm-zos when run on z/OS.
The IR that is emitted for this triple does not match the patterns
expected by the test.
This PR tweaks the patterns in the CHECK lines so that the test also
passes on z/OS.
Commit: ba57a015bae759554357f1a88abe7b03a6e4c9e0
https://github.com/llvm/llvm-project/commit/ba57a015bae759554357f1a88abe7b03a6e4c9e0
Author: John Brawn <john.brawn at arm.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
R llvm/test/Transforms/LoopStrengthReduce/AArch64/use-outside-loop.ll
Log Message:
-----------
Revert "[LSR] Narrow search space by merging users outside and inside loop" (#201581)
This is causing buildbot failures.
Reverts llvm/llvm-project#185929
Commit: 011fab8c30c6ec7a937c33e21f5a586391a51de2
https://github.com/llvm/llvm-project/commit/011fab8c30c6ec7a937c33e21f5a586391a51de2
Author: Harald van Dijk <hdijk at accesssoftek.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
A llvm/test/CodeGen/DirectX/DebugInfo/di-compile-unit-versioned-language.ll
A llvm/test/CodeGen/DirectX/DebugInfo/di-subprogram.ll
M llvm/test/CodeGen/DirectX/debug-info.ll
M llvm/test/CodeGen/DirectX/llc-pipeline.ll
Log Message:
-----------
[DirectX] Move IR printing to DXILPrettyPrinter (#198318)
By doing the IR printing inside DXILPrettyPrinter, we have the option to
customise what we print and include the info that we collect and
generate in DXILDebugInfo.
Commit: 9a87c6e30242c7c10edb71a8b7b70753c8a87250
https://github.com/llvm/llvm-project/commit/9a87c6e30242c7c10edb71a8b7b70753c8a87250
Author: Harald van Dijk <hdijk at accesssoftek.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M .github/workflows/release-binaries.yml
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/include/bolt/Passes/LongJmp.h
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Passes/BinaryPasses.cpp
M bolt/lib/Passes/LongJmp.cpp
M bolt/lib/Profile/DataAggregator.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/lib/Target/AArch64/CMakeLists.txt
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
M bolt/lib/Utils/CommandLineOpts.cpp
M bolt/test/AArch64/compare-and-branch-inversion.S
M bolt/unittests/Core/CMakeLists.txt
M bolt/unittests/Core/MCPlusBuilder.cpp
M bolt/unittests/Core/MemoryMaps.cpp
M bolt/unittests/Profile/CMakeLists.txt
A bolt/unittests/Profile/PerfScripts.cpp
M bolt/unittests/Profile/PerfSpeEvents.cpp
M clang-tools-extra/clang-tidy/readability/BracesAroundStatementsCheck.cpp
M clang-tools-extra/clang-tidy/readability/ContainerSizeEmptyCheck.cpp
M clang-tools-extra/clang-tidy/readability/FunctionSizeCheck.cpp
M clang-tools-extra/clang-tidy/readability/FunctionSizeCheck.h
M clang-tools-extra/clang-tidy/utils/BracesAroundStatement.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/container-size-empty.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/function-size.rst
M clang-tools-extra/test/clang-tidy/checkers/readability/braces-around-statements-same-line.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/braces-around-statements.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/container-size-empty.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/function-size-ignore-macros.cpp
A clang/cmake/caches/generic-allow-shared-imports.cmake
A clang/cmake/caches/hexagon-unknown-linux-musl-clang-cross-dist.cmake
A clang/cmake/caches/hexagon-unknown-linux-musl-clang-defaults-dist.cmake
A clang/cmake/caches/hexagon-unknown-linux-musl-clang-dist.cmake
A clang/cmake/caches/hexagon-unknown-linux-musl-clang-dylib-dist.cmake
M clang/include/clang-c/BuildSystem.h
M clang/include/clang/Interpreter/Value.h
M clang/include/clang/Options/FlangOptions.td
M clang/include/clang/Serialization/ModuleCache.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Interpreter/InterpreterValuePrinter.cpp
M clang/lib/Interpreter/Value.cpp
M clang/lib/Serialization/ModuleCache.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ByteCode/cxx23.cpp
M clang/test/AST/ByteCode/extern.cpp
M clang/test/Analysis/Checkers/WebKit/call-args.cpp
M clang/test/Analysis/Checkers/WebKit/mock-types.h
M clang/test/Analysis/Checkers/WebKit/nodelete-annotation.cpp
A clang/test/Analysis/Checkers/WebKit/nodelete-lazy-initialize.cpp
M clang/test/CIR/CodeGen/complex-atomic-cast.c
M clang/test/CodeGen/ms-intrinsics-other.c
M clang/test/CodeGenCUDA/amdgpu-atomic-ops.cu
M clang/test/CodeGenCUDA/managed-var.cu
M clang/test/CodeGenHIP/builtins-amdgcn-vi-f16.hip
R clang/test/CodeGenHIP/offload-pgo-sections.hip
M clang/test/CodeGenHLSL/BasicFeatures/AggregateSplatCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/ArrayElementwiseCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/InitLists.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/MatrixSplat.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/OutputArguments.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/StructElementwiseCast.hlsl
M clang/test/CodeGenHLSL/Operators/logical-not.hlsl
M clang/test/CodeGenHLSL/builtins/acos-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/asin-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/atan-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/atan2-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/atan2-overloads_mat.hlsl
M clang/test/CodeGenHLSL/builtins/ceil-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/cos-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/cosh-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/degrees-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/dot2add.hlsl
M clang/test/CodeGenHLSL/builtins/exp-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/exp2-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/floor-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/frac-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/lerp-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/log-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/log10-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/log2-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/normalize-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/pow-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/radians-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/round-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/rsqrt-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/sin-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/sinh-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/sqrt-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/step-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/tan-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/tanh-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/trunc-overloads.hlsl
M clang/test/CodeGenHLSL/resources/Texture2D-GetDimensions.hlsl
M clang/test/DebugInfo/CXX/line.cpp
M clang/test/Driver/lto.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Headers/__clang_hip_math.hip
M clang/test/Headers/openmp_device_math_isnan.cpp
M clang/test/OpenMP/amdgcn_weak_alias.c
M clang/test/OpenMP/declare_target_codegen.cpp
M clang/test/OpenMP/target_codegen.cpp
M clang/test/OpenMP/target_depend_codegen.cpp
M clang/test/OpenMP/target_indirect_codegen.cpp
M clang/test/OpenMP/target_parallel_depend_codegen.cpp
M clang/test/OpenMP/target_parallel_for_depend_codegen.cpp
M clang/test/OpenMP/target_parallel_for_simd_depend_codegen.cpp
M clang/test/OpenMP/target_simd_codegen.cpp
M clang/test/OpenMP/target_simd_depend_codegen.cpp
M clang/test/OpenMP/target_teams_depend_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_depend_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_depend_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_depend_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_simd_depend_codegen.cpp
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/SemaHLSL/VectorOverloadResolution.hlsl
M clang/tools/libclang/BuildSystem.cpp
M clang/tools/libclang/libclang.map
M clang/unittests/Format/FormatTestObjC.cpp
M clang/unittests/Interpreter/InterpreterTest.cpp
M clang/unittests/libclang/LibclangTest.cpp
M compiler-rt/CMakeLists.txt
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/lib/profile/CMakeLists.txt
M compiler-rt/lib/profile/InstrProfilingFile.c
R compiler-rt/lib/profile/InstrProfilingPlatformROCm.cpp
M compiler-rt/lib/scudo/standalone/tests/primary_test.cpp
M flang/docs/OpenACC-extensions.md
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/lib/Parser/openacc-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/check-cuda.cpp
M flang/lib/Semantics/check-do-forall.cpp
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Support/Fortran-features.cpp
A flang/test/Driver/frelaxed-c-loc-checks.f90
M flang/test/Lower/OpenACC/acc-cache.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
R flang/test/Lower/OpenMP/Todo/metadirective-dynamic.f90
M flang/test/Lower/OpenMP/metadirective-user.f90
A flang/test/Semantics/OpenACC/acc-default-none-scalars-strict.f90
M flang/test/Semantics/OpenACC/acc-default-none-scalars.f90
M flang/test/Semantics/OpenACC/acc-reduction-validity.f90
M flang/test/Semantics/OpenMP/metadirective-user.f90
A flang/test/Semantics/cuf-constant-generic-unified.cuf
M flang/test/Semantics/entry01.f90
M flang/test/Semantics/reduce.cuf
M flang/test/Semantics/resolve124.f90
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/CMakeLists.txt
M libc/include/inttypes.yaml
M libc/include/llvm-libc-macros/_LIBC_MODULAR_FORMAT_PRINTF-disable.h
M libc/include/llvm-libc-macros/_LIBC_MODULAR_FORMAT_PRINTF.h
M libc/include/llvm-libc-macros/math-macros.h
M libc/include/stdio.yaml
M libc/src/inttypes/CMakeLists.txt
A libc/src/inttypes/wcstoimax.cpp
A libc/src/inttypes/wcstoimax.h
A libc/src/inttypes/wcstoumax.cpp
A libc/src/inttypes/wcstoumax.h
M libc/test/src/inttypes/CMakeLists.txt
A libc/test/src/inttypes/wcstoimax_test.cpp
A libc/test/src/inttypes/wcstoumax_test.cpp
M libcxx/include/__memory/unique_ptr.h
M libcxx/test/std/containers/exception_safety_helpers.h
M libcxx/test/std/containers/sequences/forwardlist/exception_safety.pass.cpp
M lldb/CMakeLists.txt
M lldb/docs/dil-expr-lang.ebnf
A lldb/docs/python_api.md
R lldb/docs/python_api.rst
A lldb/docs/python_extensions.md
R lldb/docs/python_extensions.rst
A lldb/docs/resources/build.md
R lldb/docs/resources/build.rst
A lldb/docs/resources/caveats.md
R lldb/docs/resources/caveats.rst
A lldb/docs/resources/contributing.md
R lldb/docs/resources/contributing.rst
A lldb/docs/resources/dataformatters.md
R lldb/docs/resources/dataformatters.rst
A lldb/docs/resources/debugging.md
R lldb/docs/resources/debugging.rst
A lldb/docs/resources/extensions.md
R lldb/docs/resources/extensions.rst
A lldb/docs/resources/formatterbytecode.md
R lldb/docs/resources/formatterbytecode.rst
A lldb/docs/resources/fuzzing.md
R lldb/docs/resources/fuzzing.rst
M lldb/docs/resources/lldbgdbremote.md
A lldb/docs/resources/overview.md
R lldb/docs/resources/overview.rst
A lldb/docs/resources/projects.md
R lldb/docs/resources/projects.rst
A lldb/docs/resources/qemu-testing.md
R lldb/docs/resources/qemu-testing.rst
A lldb/docs/resources/sbapi.md
R lldb/docs/resources/sbapi.rst
A lldb/docs/resources/test.md
R lldb/docs/resources/test.rst
A lldb/docs/use/links.md
R lldb/docs/use/links.rst
A lldb/docs/use/ondemand.md
R lldb/docs/use/ondemand.rst
A lldb/docs/use/python-reference.md
R lldb/docs/use/python-reference.rst
A lldb/docs/use/repeat-commands.md
R lldb/docs/use/repeat-commands.rst
M lldb/include/lldb/Host/MainLoopBase.h
M lldb/include/lldb/Target/Memory.h
M lldb/include/lldb/Target/Process.h
M lldb/include/lldb/Utility/AcceleratorGDBRemotePackets.h
M lldb/include/lldb/Utility/StringExtractorGDBRemote.h
M lldb/include/lldb/ValueObject/DILAST.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/include/lldb/ValueObject/DILLexer.h
M lldb/include/lldb/ValueObject/DILParser.h
M lldb/include/lldb/ValueObject/ValueObject.h
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/source/Host/common/MainLoopBase.cpp
M lldb/source/Host/common/PythonRuntimeLoader.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCClassDescriptorV2.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCClassDescriptorV2.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.h
M lldb/source/Plugins/Process/gdb-remote/LLDBServerAcceleratorPlugin.h
M lldb/source/Target/Memory.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Utility/AcceleratorGDBRemotePackets.cpp
M lldb/source/Utility/StringExtractorGDBRemote.cpp
M lldb/source/ValueObject/DILAST.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILLexer.cpp
M lldb/source/ValueObject/DILParser.cpp
M lldb/source/ValueObject/ValueObject.cpp
M lldb/test/API/accelerator/mock/TestMockAcceleratorPlugin.py
A lldb/test/API/commands/frame/var-dil/expr/Assignment/Makefile
A lldb/test/API/commands/frame/var-dil/expr/Assignment/TestFrameVarDILAssign.py
A lldb/test/API/commands/frame/var-dil/expr/Assignment/TestFrameVarDILCompositeAssign.py
A lldb/test/API/commands/frame/var-dil/expr/Assignment/main.cpp
M lldb/tools/lldb-server/Plugins/Accelerator/Mock/LLDBServerMockAcceleratorPlugin.cpp
M lldb/tools/lldb-server/Plugins/Accelerator/Mock/LLDBServerMockAcceleratorPlugin.h
M lldb/unittests/Host/CMakeLists.txt
M lldb/unittests/Target/MemoryTest.cpp
A lldb/unittests/Utility/AcceleratorGDBRemotePacketsTest.cpp
M lldb/unittests/Utility/CMakeLists.txt
M llvm/docs/LangRef.rst
A llvm/docs/ProjectGovernance.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/index.rst
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/TargetProcessControlTypes.h
A llvm/include/llvm/ExecutionEngine/Orc/SymbolLookupSet.h
M llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/ExecutorResolver.h
M llvm/include/llvm/Frontend/Offloading/Utility.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/Operator.h
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/Analysis/CaptureTracking.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
M llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutorResolutionGenerator.cpp
M llvm/lib/ExecutionEngine/Orc/SelfExecutorProcessControl.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/ExecutorResolver.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleExecutorDylibManager.cpp
M llvm/lib/Frontend/Offloading/Utility.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Operator.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
M llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
M llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
M llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
A llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/lib/Transforms/IPO/HotColdSplitting.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform.mir
M llvm/test/Analysis/ValueTracking/memory-dereferenceable.ll
M llvm/test/Assembler/fast-math-flags.ll
A llvm/test/Assembler/invalid-phi-fast-math-flags.ll
A llvm/test/Assembler/invalid-select-fast-math-flags.ll
M llvm/test/Bitcode/compatibility.ll
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload-from-sextinreg.mir
M llvm/test/CodeGen/AArch64/arm64-csel.ll
M llvm/test/CodeGen/AArch64/bitfield-insert.ll
M llvm/test/CodeGen/AArch64/bswap-known-bits.ll
M llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
M llvm/test/CodeGen/AArch64/dup.ll
M llvm/test/CodeGen/AArch64/fcvt-i256.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/read-fp-reg.ll
A llvm/test/CodeGen/AArch64/read-reg-non-entry.ll
M llvm/test/CodeGen/AArch64/select-constant-xor.ll
M llvm/test/CodeGen/AArch64/sshl_sat.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-frintz.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
A llvm/test/CodeGen/AArch64/sve-frintz.ll
M llvm/test/CodeGen/AArch64/ushl_sat.ll
M llvm/test/CodeGen/AArch64/write-volatile-register.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sincos.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/divrem24-assume.ll
M llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
M llvm/test/CodeGen/AMDGPU/fptoui_uitofp.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
A llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
M llvm/test/CodeGen/AMDGPU/sched-ldsdma-mask.mir
M llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
A llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
M llvm/test/CodeGen/ARM/elf-preemption.ll
A llvm/test/CodeGen/ARM/weak-hidden-pic.ll
A llvm/test/CodeGen/DirectX/SampleGrad.ll
A llvm/test/CodeGen/Hexagon/hvc-remarks.ll
A llvm/test/CodeGen/Hexagon/hwloop-remarks.ll
A llvm/test/CodeGen/Hexagon/loop-idiom-remarks.ll
A llvm/test/CodeGen/Hexagon/vlcr-remarks.ll
A llvm/test/CodeGen/LoongArch/pr198339.ll
M llvm/test/CodeGen/NVPTX/global-ordering.ll
M llvm/test/CodeGen/NVPTX/globals_init.ll
A llvm/test/CodeGen/NVPTX/insert-vector-elt-bitcast-legalize.ll
M llvm/test/CodeGen/PowerPC/ucmp.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/div-by-constant.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/srem-lkk.ll
M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
A llvm/test/CodeGen/RISCV/stack-offset-large.ll
A llvm/test/CodeGen/X86/GlobalISel/calllowering-inalloca.ll
A llvm/test/CodeGen/X86/aext-and-trunc-avx512.ll
A llvm/test/CodeGen/X86/aext-and-trunc.ll
M llvm/test/CodeGen/X86/and-with-overflow.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/clmul.ll
M llvm/test/CodeGen/X86/combine-srem.ll
A llvm/test/CodeGen/X86/freeze-fp.ll
M llvm/test/CodeGen/X86/freeze-vector.ll
M llvm/test/CodeGen/X86/llvm.frexp.ll
M llvm/test/CodeGen/X86/madd.ll
M llvm/test/CodeGen/X86/masked_load.ll
M llvm/test/CodeGen/X86/masked_store.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-innerouter.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbits.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-lowhigh.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/Xtensa/inline-asm-invalid.ll
M llvm/test/CodeGen/Xtensa/setcc.ll
R llvm/test/Instrumentation/InstrProfiling/amdgpu-instrumentation.ll
R llvm/test/Instrumentation/InstrProfiling/amdgpu-profc-arrays.ll
R llvm/test/Instrumentation/InstrProfiling/gpu-weak.ll
A llvm/test/MC/RISCV/rvv/zvfqwdota8f.s
A llvm/test/MC/RISCV/rvv/zvfwdota16bf.s
A llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s
A llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-hoisting-cxx.td
M llvm/test/ThinLTO/X86/memprof-icp-recursive.ll
M llvm/test/Transforms/Attributor/nofpclass.ll
M llvm/test/Transforms/Attributor/nonnull.ll
M llvm/test/Transforms/Attributor/nosync.ll
M llvm/test/Transforms/CodeExtractor/input-value-debug.ll
M llvm/test/Transforms/FunctionAttrs/2009-01-02-LocalStores.ll
M llvm/test/Transforms/FunctionAttrs/atomic.ll
M llvm/test/Transforms/FunctionAttrs/initializes.ll
M llvm/test/Transforms/FunctionAttrs/nocapture.ll
M llvm/test/Transforms/FunctionAttrs/nofpclass.ll
M llvm/test/Transforms/FunctionAttrs/nofree.ll
M llvm/test/Transforms/FunctionAttrs/nonnull.ll
M llvm/test/Transforms/FunctionAttrs/optnone.ll
M llvm/test/Transforms/FunctionAttrs/out-of-bounds-iterator-bug.ll
M llvm/test/Transforms/FunctionAttrs/readattrs.ll
M llvm/test/Transforms/FunctionAttrs/writeonly.ll
M llvm/test/Transforms/InstCombine/AMDGPU/wave-shuffle-patterns.ll
A llvm/test/Transforms/InstCombine/gep-canonicalize-index-constfold.ll
M llvm/test/Transforms/InstCombine/log-pow.ll
M llvm/test/Transforms/JumpThreading/noalias-scope-decl.ll
A llvm/test/Transforms/LoopFusion/peel-preserve-lcssa.ll
A llvm/test/Transforms/LoopInterchange/atomic-memory-ordering.ll
M llvm/test/Transforms/LoopInterchange/call-instructions-remarks.ll
A llvm/test/Transforms/LoopInterchange/invoke.ll
A llvm/test/Transforms/LoopInterchange/non-phi-uses-lcssa-phi.ll
A llvm/test/Transforms/LoopInterchange/reduction2mem-extra-lcssa.ll
A llvm/test/Transforms/LoopVectorize/AArch64/arith-costs.ll
R llvm/test/Transforms/LoopVectorize/AArch64/binop-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/cmp_cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/early_exit_costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/f128-fmuladd-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-scalable-vectorization-always.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fully-unrolled-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-usabs.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reg-pressure-spills.ll
M llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/WebAssembly/memory-interleave.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-ptradd-with-replicated-operand.ll
M llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll
M llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
R llvm/test/Transforms/PGOProfile/amdgpu-disable-value-profiling.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/constraint-elimination-placement.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/interleave_vec.ll
M llvm/test/Transforms/PhaseOrdering/branch-dom-cond.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-intrinsics.ll
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs.ll.generated.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs.ll.nogenerated.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs_prefix_reuse.ll.generated.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs_prefix_reuse.ll.nogenerated.globals.expected
M llvm/tools/lli/ForwardingMemoryManager.h
M llvm/tools/llvm-exegesis/lib/LlvmState.cpp
M llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
M llvm/tools/llvm-exegesis/lib/MCInstrDescView.h
M llvm/unittests/ExecutionEngine/Orc/ObjectLinkingLayerTest.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp
M llvm/utils/LLVMVisualizers/llvm.natvis
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.h
M llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
M llvm/utils/gn/secondary/lldb/include/lldb/Host/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Host/BUILD.gn
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/DTLTO/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-lto2/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn
M llvm/utils/lit/tests/lit.cfg
M llvm/utils/lit/tests/shtest-cat.py
M llvm/utils/lit/tests/shtest-format.py
M llvm/utils/lit/tests/shtest-output-printing.py
M llvm/utils/profcheck-xfail.txt
M llvm/utils/release/github-upload-release.py
M mlir/include/mlir/Bindings/Python/IRCore.h
M mlir/include/mlir/Conversion/MemRefToEmitC/MemRefToEmitC.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosa.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitCPass.cpp
M mlir/lib/Conversion/TosaToSPIRVTosa/CMakeLists.txt
M mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosa.cpp
A mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaConstants.cpp
M mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaOps.cpp
M mlir/lib/Conversion/TosaToSPIRVTosa/TosaToSPIRVTosaPass.cpp
M mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACCCG.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCComputeLowering.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Conversion/ConvertToSPIRV/arith.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-dealloc.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-failed.mlir
A mlir/test/Conversion/TosaToSPIRVTosa/graph-constant-invalid.mlir
A mlir/test/Conversion/TosaToSPIRVTosa/graph-constant-mark-invalid.mlir
A mlir/test/Conversion/TosaToSPIRVTosa/graph-constant-mark.mlir
M mlir/test/Conversion/TosaToSPIRVTosa/tosa-to-spirv.mlir
M mlir/test/Dialect/Arith/emulate-wide-int.mlir
M mlir/test/Dialect/Linalg/roundtrip-morphism-linalg-category-ops.mlir
M mlir/test/Dialect/Linalg/roundtrip-morphism-linalg-named-ops.mlir
A mlir/test/Dialect/OpenACC/acc-compute-lowering-compute-async-wait.mlir
A mlir/test/Dialect/OpenACC/acc-compute-lowering-compute-device-type.mlir
A mlir/test/Dialect/OpenACC/acc-compute-lowering-loop-device-type.mlir
M mlir/test/Dialect/OpenACC/canonicalize.mlir
M mlir/test/Dialect/Tosa/constant_folding.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
M mlir/test/Dialect/XeGPU/ops.mlir
M mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir
M mlir/test/Target/LLVMIR/omptarget-declare-target-to-host.mlir
M mlir/test/python/ir/location.py
M offload/libomptarget/OpenMP/API.cpp
M offload/plugins-nextgen/level_zero/include/L0Program.h
M offload/plugins-nextgen/level_zero/src/L0Program.cpp
M offload/test/api/omp_indirect_func_basic.c
A offload/test/offloading/array_reductions.cpp
M offload/test/offloading/cuda_no_devices.c
M offload/test/offloading/multiple_reductions.cpp
M offload/test/offloading/shared_lib_fp_mapping.c
M offload/unittests/OffloadAPI/memory/olMemFill.cpp
M offload/unittests/OffloadAPI/symbol/olGetSymbolInfo.cpp
M orc-rt/include/orc-rt/NativeDylibManager.h
M orc-rt/lib/executor/NativeDylibManager.cpp
M orc-rt/lib/executor/Unix/NativeDylibAPIs.inc
M orc-rt/lib/executor/sps-ci/NativeDylibManagerSPSCI.cpp
M orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
M orc-rt/unittests/NativeDylibManagerTest.cpp
Log Message:
-----------
Merge branch 'main' into users/hvdijk/directx-delay-converting-debug-info
Compare: https://github.com/llvm/llvm-project/compare/abf77fee1784...9a87c6e30242
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