[all-commits] [llvm/llvm-project] c41194: [AArch64][llvm] Restrict luti6 (4 regs, 8-bit) to ...

[Jonathan Thackray via All-commits]

  Branch: refs/heads/users/jthackray/restrict_luti6_z0_z7
  Home:   https://github.com/llvm/llvm-project
  Commit: c411947b575c6f58bbcdf121e3809d93dbd30345
      https://github.com/llvm/llvm-project/commit/c411947b575c6f58bbcdf121e3809d93dbd30345
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2026-06-04 (Thu, 04 Jun 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/test/MC/AArch64/SME2p3/luti6-diagnostics.s

  Log Message:
  -----------
  [AArch64][llvm] Restrict luti6 (4 regs, 8-bit) to 0 <= Zn <= 7

The `luti6` instruction (table, four registers, 8-bit) should only
allow `0 <= Zn <= 7`, since there's only 3 bits. It actually allows:
```
   luti6 { z0.b - z3.b }, zt0, { z8 - z10 }
```
which produces a duplicate encoding to the following:
```
   luti6 { z0.b - z3.b }, zt0, { z0 - z2 }
```

Fix tablegen to ensure Zn is only allowed in correct range of 0 to 7.


  Commit: 79cf6b6b566975f96f6bbbdb420f8e066915dd4c
      https://github.com/llvm/llvm-project/commit/79cf6b6b566975f96f6bbbdb420f8e066915dd4c
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2026-06-04 (Thu, 04 Jun 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td

  Log Message:
  -----------
  fixup! Address CR comments


  Commit: bb138cbee2120e50c93d4ac6d71a9babb78c7a45
      https://github.com/llvm/llvm-project/commit/bb138cbee2120e50c93d4ac6d71a9babb78c7a45
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2026-06-04 (Thu, 04 Jun 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp

  Log Message:
  -----------
  fixup! Address more CR comments


Compare: https://github.com/llvm/llvm-project/compare/d3b5f2e57d64...bb138cbee212

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