[all-commits] [llvm/llvm-project] b0e72b: [clang][cmake] Move perf-training out of CLANG_INC...
Ryotaro Kasuga via All-commits
all-commits at lists.llvm.org
Wed Jun 3 11:34:23 PDT 2026
Branch: refs/heads/users/kasuga-fj/loop-interchange-fix-non-phi-lcssa-use
Home: https://github.com/llvm/llvm-project
Commit: b0e72b7c3f240cdc7e20eb6692d4662e7315bbc6
https://github.com/llvm/llvm-project/commit/b0e72b7c3f240cdc7e20eb6692d4662e7315bbc6
Author: markyang92 <80628866+markyang92 at users.noreply.github.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/CMakeLists.txt
M clang/utils/perf-training/lit.site.cfg.in
Log Message:
-----------
[clang][cmake] Move perf-training out of CLANG_INCLUDE_TESTS (#192163)
perf-training defines the generate-profdata target used by the PGO
bootstrap build.
However, it is currently enabled only when CLANG_INCLUDE_TESTS=ON.
For distribution builds such as Yocto/OE, tests are usually disabled by
setting this to OFF.
But perf-training is a PGO utility, not a test target, and it is
currently gated by that block.
As a result, generate-profdata is unavailable to the PGO bootstrap build
when
CLANG_INCLUDE_TESTS=OFF.
Move perf-training out of the CLANG_INCLUDE_TESTS block.
This is safe because utils/perf-training/CMakeLists.txt adds targets
only when
LLVM_BUILD_INSTRUMENTED or CLANG_BOLT is enabled, so moving it out does
not add
any targets unless PGO or BOLT is actually in use.
Also fix the path in lit.site.cfg.in for standalone builds.
When llvm_src_dir is set from CMAKE_SOURCE_DIR, standalone clang builds
end up
using the clang source directory instead of the LLVM source directory.
Set it to the proper LLVM source location instead.
Assisted-by: claude
Commit: 0a52250e27e87b6b29492fc5223f9634acb948b1
https://github.com/llvm/llvm-project/commit/0a52250e27e87b6b29492fc5223f9634acb948b1
Author: 陈子昂 <2802328816 at qq.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/RISCV/strided-access-wide-stride.ll
Log Message:
-----------
[LV][RISCV] Add crash test for wide pointer stride in convertToStridedAccesses (#200985)
Pre-commit test for https://github.com/llvm/llvm-project/issues/199640.
The test demonstrates a crash when the pointer stride exceeds the
canonical IV type (i32) range. To be updated by #199647.
Commit: edeffec62d462e0d162c6bcb41050c9afe192815
https://github.com/llvm/llvm-project/commit/edeffec62d462e0d162c6bcb41050c9afe192815
Author: Zhige Chen <zhige_chen at outlook.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/test/tools/llubi/controlflow.ll
A llvm/test/tools/llubi/global.ll
A llvm/test/tools/llubi/global_constant_store.ll
A llvm/test/tools/llubi/global_constexpr_initializer.ll
A llvm/test/tools/llubi/global_external.ll
M llvm/tools/llubi/lib/Context.cpp
M llvm/tools/llubi/lib/Context.h
M llvm/tools/llubi/lib/ExecutorBase.cpp
M llvm/tools/llubi/lib/Interpreter.cpp
M llvm/tools/llubi/lib/Value.cpp
M llvm/tools/llubi/lib/Value.h
M llvm/tools/llubi/llubi.cpp
Log Message:
-----------
[llubi] Global variables with simple initializers and global-address constants (#200547)
This PR implements global variables with simple initializers and
global-address constants. Support for constant expressions, alias, etc.,
are left for future PRs.
Commit: 88e96462dec6f3bbab7901a85b33bd15d4df6736
https://github.com/llvm/llvm-project/commit/88e96462dec6f3bbab7901a85b33bd15d4df6736
Author: Joshua Rodriguez <josh.rodriguez at arm.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/test/CodeGen/AArch64/arm64-int-neon.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
Log Message:
-----------
[AArch64][GlobalISel] Add handling for scalar sqabs intrinsic (#200222)
sqabs is a neon intrinsic, so can only be performed on vector register
banks. To handle intrinsic properly, coerce regbankselection to put
sqabs on fpr banks.
Commit: 32c7aaa3326f920cafd8474c6d5774ed5c0b3558
https://github.com/llvm/llvm-project/commit/32c7aaa3326f920cafd8474c6d5774ed5c0b3558
Author: Ömer Sinan Ağacan <omeragacan at gmail.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/test/Transforms/MemCpyOpt/memcpy.ll
Log Message:
-----------
Remove an invalid FIXME in a MemCpyOpt test (#200809)
Call slot optimization explicitly [requires `writable` and `noalias`][0]
when the destination is an argument, and `sret` doesn't imply any of
these.
So the `memcpy` into the return value pointer cannot be optimized away
in this test.
The test for doing this optimization when the `sret` argument is also
`writable` and `noalias` is [here][1].
Relevant commits:
- 369c9b791bc3f380e884bcad444287998c32ae16 requires writability in call
slot optimization and adds the `writable` attribute in the test linked
above, which already has `sret`, so that it optimizes as before. So
`sret` does not imply `writable`.
- f445e39ab271d07733f0f45048badd9e58905aec updates `isWritable` used in
the commit above to check for `noalias` on arguments before concluding
"writable".
The FIXME should probably have been removed with one of these commits.
[0]:
https://github.com/llvm/llvm-project/blob/356d7e6bf429a7ff3ae798bb994631ef33891a44/llvm/lib/Analysis/AliasAnalysis.cpp#L1009-L1019
[1]:
https://github.com/llvm/llvm-project/blob/356d7e6bf429a7ff3ae798bb994631ef33891a44/llvm/test/Transforms/MemCpyOpt/sret.ll#L9
Commit: ecf8b039e5e80a609a4446b29e83600062179cc6
https://github.com/llvm/llvm-project/commit/ecf8b039e5e80a609a4446b29e83600062179cc6
Author: Igor Wodiany <igor.wodiany at amd.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
Log Message:
-----------
[AMDGPU] Recompute EXEC liveness in SIWholeQuadMode::toExact (#200866)
This is required as stale liveness information can lead to an incorrect
optimization in `SIOptimizeExecMaskingPreRA`. For example, when `hi16`
is removed from EXEC, `optimizeElseBranch` produces an incorrect result
by removing `S_AND`.
This is caused by the following code:
```c++
SlotIndex StartIdx = LIS->getInstructionIndex(SaveExecMI);
SlotIndex EndIdx = LIS->getInstructionIndex(*AndExecMI);
for (MCRegUnit Unit : TRI->regunits(ExecReg)) {
LiveRange &RegUnit = LIS->getRegUnit(Unit);
if (RegUnit.find(StartIdx) != std::prev(RegUnit.find(EndIdx)))
return false;
}
```
When `hi16` is available there are two `RegUnit`s, one for `hi16` and
one for `lo16`. In the case of `wqm.ll` test it produces two live
ranges:
```
0: [320r,320d:3)[368r,368d:2)[736r,736d:4)[832r,832d:1)[944r,944d:0) 0 at 944r 1 at 832r 2 at 368r 3 at 320r 4 at 736r
1: [12r,12d:1)[320r,320d:5)[368r,368d:4)[736r,736d:6)[744r,744d:0)[832r,832d:3)[944r,944d:2) 0 at 744r 1 at 12r 2 at 944r 3 at 832r 4 at 368r 5 at 320r 6 at 736r
```
When `hi16` is removed there is only one range:
```
0: [320r,320d:3)[368r,368d:2)[736r,736d:4)[832r,832d:1)[944r,944d:0) 0 at 944r 1 at 832r 2 at 368r 3 at 320r 4 at 736r
```
If only the first range is considered the loop will finish without
returning false and continue to remove `S_AND`. It is because EXEC
register for `S_AND` added by `SIWholeQuadMode::toExact` is not in the
range. This is incorrect.
When `hi16` is present the incorrect behavior is masked by the second
live range coming from `hi16`, causing the loop to return. This can be
most likely explained by the fact that `hi16` is only computed after the
new `S_AND` was added so contains more up to date information. Removing
EXEC from `LiveIntervals` forces the live range to be recomputed.
Commit: 2fc8a3e84ec08659e33b63e91f1d9b4be0890cfc
https://github.com/llvm/llvm-project/commit/2fc8a3e84ec08659e33b63e91f1d9b4be0890cfc
Author: Elvina Yakubova <eyakubova at nvidia.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Passes/VeneerElimination.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
A bolt/test/AArch64/veneer-erratum-843419.s
Log Message:
-----------
[BOLT][AArch64] Eliminate e843419 veneers (#187955)
Detect and eliminate A53 843419 errata veneers with the drop-cortex-a53-843419-veneers option.
Commit: 7d62e753bb9ef0c21d1be9d155e4f6456391a406
https://github.com/llvm/llvm-project/commit/7d62e753bb9ef0c21d1be9d155e4f6456391a406
Author: David Spickett <david.spickett at arm.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/test/API/functionalities/thread/jump/TestThreadJump.py
Log Message:
-----------
[lldb][test] Disable part of TestThreadJump.py on WoA (#201074)
See https://github.com/llvm/llvm-project/issues/201068.
Commit: 4cfbf8ec82cb7e6f06c3f382a1b4ec082bd42b18
https://github.com/llvm/llvm-project/commit/4cfbf8ec82cb7e6f06c3f382a1b4ec082bd42b18
Author: Kshitij Paranjape <kshitijvparanjape at gmail.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
M llvm/test/Transforms/SimplifyCFG/speculate-derefable-load.ll
Log Message:
-----------
[ValueTracking] Conservative NoSync check prevents vectorization (#199002)
Conservative nosync check in ValueTracking.cpp returns false causing
potentially faulting load preventing vectorization. Instead check if any
instructions betweenAssume Instruction and Ctx Instruction are synchronizing.
Fixes #180180.
Commit: 924388cd4bffe04cd6f191da0cd7015a19c673ef
https://github.com/llvm/llvm-project/commit/924388cd4bffe04cd6f191da0cd7015a19c673ef
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/riscv/headers.txt
M libc/config/linux/x86_64/headers.txt
Log Message:
-----------
[libc] Add sys/sendfile.h to the public header list (#201062)
Commit: 4b212e5418097e31b13ab51dd9574c8cc6a3fdab
https://github.com/llvm/llvm-project/commit/4b212e5418097e31b13ab51dd9574c8cc6a3fdab
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-metadata.ll
Log Message:
-----------
[VPlan] Propagate interleave-group metadata to narrowed wide load/store. (#199356)
VPInterleaveRecipe now carries the common metadata valid for all members
and as such hold for any member. Propagate it to narrowed load and
stores.
PR: https://github.com/llvm/llvm-project/pull/199356
Commit: c3ea53cd814abd924fd004357f357823b180ace8
https://github.com/llvm/llvm-project/commit/c3ea53cd814abd924fd004357f357823b180ace8
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/interleaved_cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter-cost.ll
M llvm/test/Transforms/LoopVectorize/ARM/interleaved_cost.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/mem-interleaving-costs-02.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/mem-interleaving-costs.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/WebAssembly/memory-interleave.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/handle-iptr-with-data-layout-to-not-assert.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2-indices-0u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-01u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-0uu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-01uu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-0uuu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-store-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll
M llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/x86-loopvectorize-costmodel.ll
M llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/x86-loopvectorize-costmodel.ll.expected
M llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/loopvectorize-costmodel.test
Log Message:
-----------
[VPlan] Don't print interleave group insert position. (#200023)
This patch updates interleave group printing to drop the insert
position. It does not add any information (the position of the
interleave group is determined by the position in VPlan), and for stores
we currently were printing <badref> anyways (trying to print a value
with void type).
PR: https://github.com/llvm/llvm-project/pull/200023
Commit: bae4566a422cba33fb41a072320b36fb51cb67ee
https://github.com/llvm/llvm-project/commit/bae4566a422cba33fb41a072320b36fb51cb67ee
Author: Amit Kumar Pandey <pandey.kumaramit2023 at gmail.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M compiler-rt/lib/asan/asan_interceptors.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_common.h
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_mac.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_win.cpp
M compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
Log Message:
-----------
[compiler-rt][sanitizer_common] Generalize CheckNoDeepBind as OnDlOpen (#200748)
Rename the dlopen pre-check hook to OnDlOpen so platform-specific dlopen
handling can be extended beyond the RTLD_DEEPBIND guard on Linux.
Windows and macOS keep no-op implementations. All dlopen interceptors
call the shared hook.
Commit: bbc8fcb0e850984efa54eb815717f7ab905c4c05
https://github.com/llvm/llvm-project/commit/bbc8fcb0e850984efa54eb815717f7ab905c4c05
Author: Luke Lau <luke at igalia.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
Log Message:
-----------
[VPlan] Fix assertion when VPReductionPHIRecipe is simplified (#201023)
When replacing an invariant store of a reduction, we assert that the
stored value is the backedge value. However in some cases the
VPReductionPHIRecipe may be simplified away completely, so account for
this.
Fixes #201020
Fixes #200742
Commit: 969f6415b69cce63e98c19a03e8940b89cd8b285
https://github.com/llvm/llvm-project/commit/969f6415b69cce63e98c19a03e8940b89cd8b285
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/vplan-incomplete-cases.ll
Log Message:
-----------
[VPlan] Replace VPTypeAnalysis with VPValue::getScalarType. (NFC) (#200256)
Now that all VPValues have their scalar type set at construction,
replace calls to VPTypeAnalysis::inferScalarType with direct calls to
VPValue::getScalarType, and remove the no-longer-needed VPTypeAnalysis
members from VPCostContext and VPTransformState. Also remove the
getScalarTypeOrInfer fallback helper.
Depends on https://github.com/llvm/llvm-project/pull/200255
PR: https://github.com/llvm/llvm-project/pull/200256
Commit: 238bd57ccc283a3dec84afcd0b092b4e7a378491
https://github.com/llvm/llvm-project/commit/238bd57ccc283a3dec84afcd0b092b4e7a378491
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
Log Message:
-----------
[AArch64][TG] Migrate AArch64 backend from !cond to !switch(NFC) (#200949)
Making exact matches more compact. The \!switch operator has been
introduced by: https://github.com/llvm/llvm-project/pull/199659
Commit: f341dab9edfa97d7a4a01f9bc0fe981055dc5cc9
https://github.com/llvm/llvm-project/commit/f341dab9edfa97d7a4a01f9bc0fe981055dc5cc9
Author: Ming-Yi Lai <ming-yi.lai at mediatek.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/test/CodeGen/RISCV/riscv-cf-protection.c
Log Message:
-----------
[clang][RISCV][Zicfilp] Force user to use `-mcf-branch-label-scheme=unlabeled` (#152122)
Expected Behavior:
When `-fcf-protection=branch|full` is specified, it's an error to omit
`-mcf-branch-label-scheme=unlabeled`.
Context:
When using forward-edge control flow integrity feature based on the
RISC-V Zicfilp extension, the `-mcf-branch-label-scheme` option selects
the encoding scheme used in the landing pad labels. The spec defines 2
schemes: `func-sig` and `unlabeled`, with the former specified as the
default. However the `func-sig` backend is still under active
development and won't land anytime soon; in the meanwhile, the
`unlabeled` scheme almost has complete support in the toolchain now.
Given that Clang currently accepts and defaults to
`-mcf-branch-label-scheme=func-sig` but doesn't work correctly, we want
to formally forbid the user from using
`-mcf-branch-label-scheme=func-sig` for now until the `func-sig` scheme
is properly supported. We choose to do so by forcing the user to specify
`-mcf-branch-label-scheme=unlabeled` (instead of changing the default to
`unlabeled`) so the default of `func-sig` can be retained according to
the spec and build scripts targeting the current Clang can be
forward-compatible with the Clang that supports the complete `func-sig`
scheme.
Commit: 016f53e2df9dae2177623d369eb5a1373fa6dc3c
https://github.com/llvm/llvm-project/commit/016f53e2df9dae2177623d369eb5a1373fa6dc3c
Author: Mel Chen <mel.chen at sifive.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-access-wide-stride.ll
A llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-narrow-iv.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
Log Message:
-----------
[VPlan] Use pointer index type for stride in convertToStridedAccesses (#199647)
The type of StrideInBytes should be index type, not the canonical IV
type. When the type of canonical IV is narrower than index type (e.g.,
i32 canonical IV on a RV64), using CanonicalIVType for stride may cause
crash.
The assertion failure in SelectionDAG was a secondary symptom, and the
root cause is a semantic mismatch in the stride type.
Fixes #199509
Commit: 67aaa03dac582b5ccf65776e449eb6c7517eb11c
https://github.com/llvm/llvm-project/commit/67aaa03dac582b5ccf65776e449eb6c7517eb11c
Author: Matthias Springer <me at m-sp.org>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M mlir/docs/Dialects/LLVM.md
M mlir/docs/LangRef.md
A mlir/docs/Tokens.md
M mlir/docs/Traits/_index.md
M mlir/include/mlir/Dialect/Async/IR/Async.h
M mlir/include/mlir/Dialect/Async/IR/AsyncOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
M mlir/include/mlir/IR/BuiltinDialectBytecode.td
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/include/mlir/IR/OpBase.td
M mlir/include/mlir/IR/OpDefinition.h
M mlir/lib/AsmParser/TokenKinds.def
M mlir/lib/AsmParser/TypeParser.cpp
M mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
M mlir/lib/Dialect/Async/IR/Async.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncRuntimeRefCounting.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/Verifier.cpp
M mlir/lib/Target/LLVMIR/TypeFromLLVM.cpp
M mlir/lib/Target/LLVMIR/TypeToLLVM.cpp
M mlir/test/Conversion/AsyncToLLVM/convert-coro-to-llvm.mlir
M mlir/test/Dialect/ArmSME/invalid.mlir
M mlir/test/Dialect/Builtin/Bytecode/builtin_fixed.mlir
M mlir/test/Dialect/Builtin/Bytecode/builtin_fixed_0.mlirbc
M mlir/test/Dialect/Builtin/Bytecode/types.mlir
M mlir/test/Dialect/LLVMIR/types.mlir
M mlir/test/Dialect/Linalg/invalid.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
M mlir/test/Dialect/SparseTensor/invalid.mlir
M mlir/test/Dialect/Tensor/invalid.mlir
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Dialect/traits.mlir
M mlir/test/IR/operand.mlir
M mlir/test/IR/result.mlir
A mlir/test/IR/token-type.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/mlir-tblgen/predicate.td
M mlir/test/mlir-tblgen/types.mlir
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Log Message:
-----------
[mlir][IR] Add builtin `TokenType` (#195640)
Introduces a new parameterless, opaque, builtin SSA value type,
`!token`. A token cannot appear in a value-forwarding position such as
`cf.br`, `arith.select`, `scf.for` iter-args or function call/return.
Walking back from any token use reaches the producing operation without
crossing such a boundary. Tokens carry no runtime data and cannot
constant-fold.
This contract is enforced by changing the default ODS `AnyType`
predicate to exclude tokens. In addition, token-producing and
token-consuming ops must opt in by implementing the `ProducesToken` and
`ConsumesToken` traits. The IR verifier checks for the presence of these
traits.
Note: CSE, DCE, hoisting, and `OperationEquivalence` remain unchanged. A
stronger contract (e.g., uniqueness, arity, paired lifetime), if
desirable based on the semantics of token-producing and token-consuming
ops, can be expressed at the op level via existing mechanisms (side
effects, block arguments, traits, attributes), keeping the type
orthogonal to operation-level transformations. This mirrors LLVM's
`token` type.
Other changes:
* Builtin bytecode: new entry for `TokenType`.
* AsmParser / AsmPrinter: `token` keyword for the textual format.
* Remove `LLVMTokenType` from the LLVM dialect and use the builtin
`TokenType` instead.
* Async dialect: references to `async::TokenType` are qualified to
disambiguate from the new builtin `TokenType`.
* Documentation: new `mlir/docs/Tokens.md` covering the structural
contract, design rationale, and ODS integration.
No changes to `Operation`, the generic op syntax, the bytecode op
encoding, or core C++ APIs around `Operation`.
This commit is in preparation of adding support for breaking exit from
regions. (E.g., early exit from loops.)
RFC:
https://discourse.llvm.org/t/rfc-add-a-builtin-token-type-to-mlir/90706
Assisted-by: claude-opus-4.7-thinking-high
---------
Co-authored-by: Mehdi Amini <joker.eph at gmail.com>
Commit: 9def57af57cc61ebaa83106f056ef3bbc59e0244
https://github.com/llvm/llvm-project/commit/9def57af57cc61ebaa83106f056ef3bbc59e0244
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Remove stale references to VPTypeInfo. (#201088)
VPTypeInfo has been removed, and (#199647) a016f53e2 add dead reference,
causing the build to fail on main.
Commit: c51296345de89f80fbaeac85e92d72d0df06c0cb
https://github.com/llvm/llvm-project/commit/c51296345de89f80fbaeac85e92d72d0df06c0cb
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/source/Host/windows/PipeWindows.cpp
Log Message:
-----------
[lldb][windows] Close pipe HANDLE if _open_osfhandle fails (#200882)
Commit: 3c0daa26db4ba76359ca3285af6b709d8199c1cc
https://github.com/llvm/llvm-project/commit/3c0daa26db4ba76359ca3285af6b709d8199c1cc
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/source/Host/windows/PseudoConsole.cpp
Log Message:
-----------
[lldb][Windows] Default-initialize PseudoConsole Kernel32 members (#200880)
Commit: 6e1f2f513c84759e0d0727925dbb8c3a3e8b5199
https://github.com/llvm/llvm-project/commit/6e1f2f513c84759e0d0727925dbb8c3a3e8b5199
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/bindings/python/CMakeLists.txt
Log Message:
-----------
[lldb][windows] copy vcpkg runtime dlls (#200416)
Commit: 6b6cb5fb35183b156f8acf648184b61b985bee8f
https://github.com/llvm/llvm-project/commit/6b6cb5fb35183b156f8acf648184b61b985bee8f
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/ObjCopy/DXContainer/DXContainerObjcopy.cpp
M llvm/test/tools/llvm-objcopy/DXContainer/copy-headers.yaml
M llvm/test/tools/llvm-objcopy/DXContainer/dump-section.yaml
Log Message:
-----------
Reapply "[llvm-objcopy] Strip header from DXContainer's ILDB part during `--dump-section`" (#200906)
The patch is reapplied with adjustments for the test failing on some
buildbots.
It strips the header from ILDB part of DXContainer during `llvm-objcopy
--dump-section`, so that the output contains bitcode only.
Commit: 78cf6cde9fbb6f08dacb3de5bc529243f9f85d9b
https://github.com/llvm/llvm-project/commit/78cf6cde9fbb6f08dacb3de5bc529243f9f85d9b
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp
Log Message:
-----------
[NFC][analyzer] Simplify ExprEngine::Visit, eliminate NodeBuilders (#200837)
Remove NodeBuilder use from `ExprEngine::Visit` to reduce its size from
700 lines to 600 lines of source code.
This commit also moves the "for instance method operators, make sure the
'this' argument has a valid region" logic (~10 lines) from the huge
`ExprEngine::Visit` to the more specific `VisitCallExpr`; and applies a
few other very minor code quality improvements.
Commit: 3191c78697c8b499a108e917a9590811db723969
https://github.com/llvm/llvm-project/commit/3191c78697c8b499a108e917a9590811db723969
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/module_asm_unsupported.ll
Log Message:
-----------
[SPIR-V] Reject module-level inline assembly with a diagnostic (#199992)
Module level inline asm is unsupported, even with extension
Commit: 7139d0b46f6d71334b74049bbd540ac4b18a1bc5
https://github.com/llvm/llvm-project/commit/7139d0b46f6d71334b74049bbd540ac4b18a1bc5
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/include/clang/Basic/arm_neon.td
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
A clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
M clang/test/Sema/aarch64-neon-immediate-ranges/dotprod.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
A llvm/test/CodeGen/AArch64/aarch64-f16f32dot-intrinsics.ll
Log Message:
-----------
[AArch64] Add intrinsic support for Fdot instr. (#189987)
This patch adds intrinsics for new NEON Fdot instruction variants. The
implementation is based on the
[proposal](https://github.com/ARM-software/acle/pull/428) and adds these
ACLE builtins:
```
float32x2_t vdot_f32_f16(float32x2_t r, float16x4_t a, float16x4_t b);
float32x4_t vdotq_f32_f16(float32x4_t r, float16x8_t a, float16x8_t b);
float32x2_t vdot_lane_f32_f16(float32x2_t r, float16x4_t a, float16x4_t b, const int lane);
float32x4_t vdotq_laneq_f32_f16(float32x4_t r, float16x8_t a, float16x8_t b, const int lane);
float32x2_t vdot_laneq_f32_f16(float32x2_t r, float16x4_t a, float16x8_t b, const int lane);
float32x4_t vdotq_lane_f32_f16(float32x4_t r, float16x8_t a, float16x4_t b, const int lane);
```
Commit: 67b3b87e6d64d7d706e14be8c5bba6acdc200623
https://github.com/llvm/llvm-project/commit/67b3b87e6d64d7d706e14be8c5bba6acdc200623
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll
Log Message:
-----------
[LLVM][GlobalISel] Make CSEMIRBuilder::buildFConstant scalable vector aware. (#200386)
Commit: ad9e5bfcaf38580b2596967d3e1b7c3746d31bb1
https://github.com/llvm/llvm-project/commit/ad9e5bfcaf38580b2596967d3e1b7c3746d31bb1
Author: Weronika Lewandowska <weronika.lewandowska at intel.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/runtimes/CMakeLists.txt
Log Message:
-----------
[Offload] Forward LIBOMPTARGET_ cmake options to offload (#199906)
Add LIBOMPTARGET for offload so LIBOMPTARGET_* options are forwarded.
Note that the LIBOMPTARGET_* prefix was inherited from OpenMP's CMake
setup.
Commit: 3c86ffb3bd282cfad0bf1e3aa2cedf1e4895b057
https://github.com/llvm/llvm-project/commit/3c86ffb3bd282cfad0bf1e3aa2cedf1e4895b057
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/IR/Verifier.cpp
M llvm/test/Verifier/immarg-param-attribute-invalid.ll
Log Message:
-----------
[LLVM][Verifier] Reject "splat (...)" as an invalid value for an immarg operand. (#200445)
This makes the behaviour consistent with ConstantDataVector based
values.
Commit: b29352f7ea1d46fa7d90900d7a279851b6de9f74
https://github.com/llvm/llvm-project/commit/b29352f7ea1d46fa7d90900d7a279851b6de9f74
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang-tools-extra/clang-tidy/misc/DefinitionsInHeadersCheck.cpp
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/refactor/tweaks/DefineInline.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/JSONNodeDumper.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/ASTMatchers/ASTMatchersInternal.h
M clang/include/clang/Basic/Specifiers.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTDumper.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/Comment.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/ASTMatchers/Dynamic/Registry.cpp
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/Index/IndexingContext.cpp
M clang/lib/InstallAPI/Visitor.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
M clang/lib/Tooling/Syntax/BuildTree.cpp
M clang/test/AST/ast-dump-templates-pattern.cpp
M clang/test/CXX/basic/basic.link/p11.cpp
M clang/test/CXX/temp/temp.arg/temp.arg.template/p3-2a.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.decl/p4.cpp
M clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp
M clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/test/SemaTemplate/friend-template.cpp
M clang/test/SemaTemplate/instantiate-scope.cpp
M clang/test/Templight/templight-default-func-arg.cpp
M clang/test/Templight/templight-empty-entries-fix.cpp
M clang/tools/libclang/CIndex.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
Revert "[clang] fix getTemplateInstantiationArgs" (#201093)
This caused bootstrap builds on macOS to fail with
error: definition with same mangled name ... as another definition
in JSONGenerator.cpp. See comments on the original PR.
Reverts llvm/llvm-project#199528
Commit: 1872f06d60f35133bbc06e047c763b490c2d31be
https://github.com/llvm/llvm-project/commit/1872f06d60f35133bbc06e047c763b490c2d31be
Author: khaki3 <47756807+khaki3 at users.noreply.github.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M flang/include/flang/Optimizer/HLFIR/Passes.td
M flang/lib/Optimizer/HLFIR/Transforms/CMakeLists.txt
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
A flang/lib/Optimizer/HLFIR/Transforms/SeparateAllocatableAssign.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/test/Driver/mlir-debug-pass-pipeline.f90
M flang/test/Driver/mlir-pass-pipeline.f90
M flang/test/Fir/basic-program.fir
A flang/test/HLFIR/opt-bufferization-dealloc-conflict.fir
A flang/test/HLFIR/separate-allocatable-assign.fir
M flang/test/Integration/OpenMP/workshare-axpy.f90
Log Message:
-----------
[flang][HLFIR] Add SeparateAllocatableAssign pass (#197814)
Example:
```fortran
!$acc kernels
B = A ! A, B allocatable
!$acc end kernels
```
In this code, `B = A` lowers to `hlfir.assign ... realloc`, which
becomes a `_FortranAAssign` runtime call inside the compute region — the
allocation can't be separated from the copy, and it crashes when `B` is
unallocated.
Fix: add `SeparateAllocatableAssign`, which splits the realloc assign
into an explicit conditional [re-]allocation followed by a plain
`hlfir.assign`, exposing the allocation as plain FIR. For variable RHS
it skips aliasing cases (`a = a(:n)`) by loading the LHS `fir.box` and
querying `fir::AliasAnalysis` on the data. For `hlfir.expr` RHS it
leaves ordering to bufferization, and fixes
`ElementalAssignBufferization` to stop fusing an elemental across a
deallocation.
Commit: f85f70fe78bd9d787d5414a79224c2e6b60fa472
https://github.com/llvm/llvm-project/commit/f85f70fe78bd9d787d5414a79224c2e6b60fa472
Author: Fangrui Song <i at maskray.me>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetStreamer.h
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVTypeInst.h
M llvm/lib/Target/X86/X86OptimizeLEAs.cpp
Log Message:
-----------
[Target] Remove unused DenseMapInfo::getTombstoneKey (#200955)
#200595 changed DenseMap to no longer create tombstone buckets, so
DenseMapInfo<T>::getTombstoneKey() is never called. Remove dead
definitions and dead tombstone branches.
Commit: 414b8b986705d24e415e8ef17bc8ddbbd6839712
https://github.com/llvm/llvm-project/commit/414b8b986705d24e415e8ef17bc8ddbbd6839712
Author: Fangrui Song <i at maskray.me>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/include/llvm/CodeGen/AccelTable.h
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/CodeGen/MachineOperand.h
M llvm/include/llvm/CodeGen/PBQP/CostAllocator.h
M llvm/include/llvm/CodeGen/Register.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/DebugInfo/CodeView/TypeHashing.h
M llvm/include/llvm/DebugInfo/CodeView/TypeIndex.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h
M llvm/include/llvm/DebugInfo/GSYM/FileEntry.h
M llvm/include/llvm/Transforms/IPO/Attributor.h
M llvm/include/llvm/Transforms/IPO/FunctionSpecialization.h
M llvm/include/llvm/Transforms/IPO/IROutliner.h
M llvm/include/llvm/Transforms/Scalar/GVNExpression.h
M llvm/include/llvm/Transforms/Utils/BypassSlowDivision.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.h
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h
M llvm/lib/CodeGen/MachineOutliner.cpp
M llvm/lib/CodeGen/StackMaps.cpp
M llvm/lib/DebugInfo/CodeView/TypeHashing.cpp
M llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp
M llvm/lib/DebugInfo/PDB/Native/GSIStreamBuilder.cpp
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp
M llvm/lib/Transforms/Scalar/EarlyCSE.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/GVNSink.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Utils/CanonicalizeFreezeInLoops.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[CodeGen][Transforms] Remove unused DenseMapInfo::getTombstoneKey (#200956)
#200595 changed DenseMap to no longer create tombstone buckets, so
DenseMapInfo<T>::getTombstoneKey() is never called. Remove dead
definitions and dead tombstone branches.
Commit: e0f5ce18c04a5c55e5eb4e35e5ab1f1980e15c31
https://github.com/llvm/llvm-project/commit/e0f5ce18c04a5c55e5eb4e35e5ab1f1980e15c31
Author: Fangrui Song <i at maskray.me>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/AliasAnalysis.h
M llvm/include/llvm/Analysis/AssumeBundleQueries.h
M llvm/include/llvm/Analysis/IRSimilarityIdentifier.h
M llvm/include/llvm/Analysis/MemoryLocation.h
M llvm/include/llvm/Analysis/MemorySSA.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/IR/Attributes.h
M llvm/include/llvm/IR/BasicBlock.h
M llvm/include/llvm/IR/DebugInfo.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/Dominators.h
M llvm/include/llvm/IR/Metadata.h
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/include/llvm/IR/ValueHandle.h
M llvm/include/llvm/IR/ValueMap.h
M llvm/lib/Analysis/IRSimilarityIdentifier.cpp
M llvm/lib/Analysis/MemorySSA.cpp
M llvm/lib/IR/ConstantsContext.h
M llvm/lib/IR/LLVMContextImpl.h
Log Message:
-----------
[IR][Analysis] Remove unused DenseMapInfo::getTombstoneKey (#200958)
#200595 changed DenseMap to no longer create tombstone buckets, so
DenseMapInfo<T>::getTombstoneKey() is never called. Remove dead
definitions and dead tombstone branches.
Commit: 17f85f467249d08508fe29f5c01f6a046d9a68e3
https://github.com/llvm/llvm-project/commit/17f85f467249d08508fe29f5c01f6a046d9a68e3
Author: Fangrui Song <i at maskray.me>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/include/llvm/BinaryFormat/Minidump.h
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/BinaryFormat/WasmTraits.h
M llvm/include/llvm/CAS/CASID.h
M llvm/include/llvm/CAS/CASReference.h
M llvm/include/llvm/CodeGenTypes/LowLevelType.h
M llvm/include/llvm/DWARFLinker/Classic/DWARFLinkerDeclContext.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/ExecutorAddress.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/MemoryFlags.h
M llvm/include/llvm/ExecutionEngine/Orc/SymbolStringPool.h
M llvm/include/llvm/Frontend/OpenMP/OMPContext.h
M llvm/include/llvm/Linker/IRMover.h
M llvm/include/llvm/MC/MCRegister.h
M llvm/include/llvm/Object/ObjectFile.h
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
M llvm/include/llvm/ProfileData/FunctionId.h
M llvm/include/llvm/ProfileData/SampleProf.h
M llvm/include/llvm/SandboxIR/Context.h
M llvm/include/llvm/TextAPI/SymbolSet.h
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/Object/Minidump.cpp
M llvm/tools/dsymutil/BinaryHolder.h
M llvm/tools/llvm-c-test/echo.cpp
M llvm/tools/llvm-reduce/deltas/Delta.h
M llvm/tools/llvm-split/llvm-split.cpp
M llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
M llvm/utils/gdb-scripts/prettyprinters.py
Log Message:
-----------
[llvm] Remove unused DenseMapInfo::getTombstoneKey (#200957)
#200595 changed DenseMap to no longer create tombstone buckets, so
DenseMapInfo<T>::getTombstoneKey() is never called. Remove dead
definitions and dead tombstone branches.
Commit: 10d3c6779d9faffed0a1d686ea76ee2cec48bd06
https://github.com/llvm/llvm-project/commit/10d3c6779d9faffed0a1d686ea76ee2cec48bd06
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M libc/include/limits.yaml
M libc/include/llvm-libc-macros/limits-macros.h
M libc/test/src/__support/CPP/limits_test.cpp
Log Message:
-----------
[libc] Define SSIZE_MAX in limits-macros.h (#201087)
Defined SSIZE_MAX in limits-macros.h to support POSIX compliance.
Applications compiling against LLVM libc require SSIZE_MAX to be defined
in limits.h.
SSIZE_MAX is defined strictly in terms of __PTRDIFF_MAX__, matching
ssize_t defined as __PTRDIFF_TYPE__, ensuring they are always
structurally aligned and compile-time safe.
Added Doxygen comments for SSIZE_MAX.
Added SSIZE_MAX to limits.yaml and added a unit test in limits_test.cpp
to verify the definition.
Assisted-by: Automated tooling, human reviewed.
Commit: 9a9b9d92db959447c32c63a931f269189c3c0893
https://github.com/llvm/llvm-project/commit/9a9b9d92db959447c32c63a931f269189c3c0893
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/include/llvm/DebugInfo/PDB/Native/PDBFile.h
M llvm/include/llvm/DebugInfo/PDB/Native/PDBFileBuilder.h
M llvm/include/llvm/DebugInfo/PDB/Native/PDBStringTableBuilder.h
M llvm/include/llvm/DebugInfo/PDB/Native/RawConstants.h
M llvm/lib/DebugInfo/PDB/Native/PDBFile.cpp
M llvm/lib/DebugInfo/PDB/Native/PDBFileBuilder.cpp
A llvm/test/tools/llvm-pdbutil/dxcontainer.test
M llvm/tools/llvm-pdbutil/PdbYaml.cpp
M llvm/tools/llvm-pdbutil/PdbYaml.h
M llvm/tools/llvm-pdbutil/YAMLOutputStyle.cpp
M llvm/tools/llvm-pdbutil/YAMLOutputStyle.h
M llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp
M llvm/tools/llvm-pdbutil/llvm-pdbutil.h
Log Message:
-----------
Reapply "[PDB][llvm-pdbutil] Add DXContainer support for `pdb2yaml` and `yaml2pdb`" (#201092)
This reapplies #198351 with 2 issues fixed:
- `-Wchanges-meaning` causing an error in `PdbYaml.h`
- UB when parsing DXContainer header from a null buffer, fixed in
#200865
Original patch description:
This patch enables the following:
1. Attempting to parse a `DXContainer` from stream 5 (generated by
DirectX tools) of a PDB file, to be used later in `llvm-pdbutil`.
2. Outputting a PDB file with a built in DXContainer as YAML. Existing
DirectX tools form a PDB container with empty DBI, TPI and IPI streams,
so this patch also allows them to be empty when dumping a PDB file as
YAML.
3. Creating a PDB file from YAML with an built in DXContainer. When
creating a PDB with a DXContainer, streams DBI, TPI and IPI can be
completely empty, so this patch also includes adjustments to allow
forming such a PDB file. This is done to maintain compatibility with
other DirectX tools.
Commit: 0012320e60cddc1f98a9835f7d4ce8552fe12fe7
https://github.com/llvm/llvm-project/commit/0012320e60cddc1f98a9835f7d4ce8552fe12fe7
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add.ll
Log Message:
-----------
[LLVM][ComplexDeinterleaving] Update identifyDeinterleave to support all forms of zero. (#200400)
The original code misses ConstantFP based zeros.
Commit: 574243d7fad23da3532699caf0eadf36dfc321d8
https://github.com/llvm/llvm-project/commit/574243d7fad23da3532699caf0eadf36dfc321d8
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
A llvm/test/CodeGen/SPIRV/transcoding/func_param_attr.ll
Log Message:
-----------
[SPIR-V] Emit missing Sext function parameter decoration for signext args and test other param decorations (#200801)
Commit: 94fcaf5110e21451fed27c61e1f1e0b5fb3bdb33
https://github.com/llvm/llvm-project/commit/94fcaf5110e21451fed27c61e1f1e0b5fb3bdb33
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
M llvm/test/Transforms/SandboxVectorizer/load_store_vec.ll
Log Message:
-----------
[LLVM][SandboxVec][LoadStoreVec] Add support for vector ConstantInt/FP. (#200437)
The current implementation treats all ConstantInt/FP values as scalar,
leading to the wrong number of elements being used when combining them.
Commit: 9942a38e64b2333dc3816eebe6ac9230b1993220
https://github.com/llvm/llvm-project/commit/9942a38e64b2333dc3816eebe6ac9230b1993220
Author: A. Jiang <de34 at live.cn>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M libcxx/include/__mutex/unique_lock.h
M libcxx/include/shared_mutex
M libcxx/test/libcxx/thread/nodiscard.verify.cpp
Log Message:
-----------
[libc++] Apply `[[nodiscard]]` to `unique_lock` and `<shared_mutex>` (#200986)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html
- https://wg21.link/thread.sharedmutex.class
- https://wg21.link/thread.sharedtimedmutex.class
- https://wg21.link/thread.lock.unique
- https://wg21.link/thread.lock.shared
Remarks:
- All constructors of `shared_lock` are marked `[[nodiscard]]`, which is
consistent with handling for constructors of `unique_lock`.
Commit: 2a7524b4e33c8dfd667fa28341ec7c6c529d9c50
https://github.com/llvm/llvm-project/commit/2a7524b4e33c8dfd667fa28341ec7c6c529d9c50
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/DebuggerThread.cpp
M lldb/source/Plugins/Process/Windows/Common/IDebugDelegate.h
M lldb/source/Plugins/Process/Windows/Common/LocalDebugDelegate.cpp
M lldb/source/Plugins/Process/Windows/Common/LocalDebugDelegate.h
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.h
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.h
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h
A lldb/test/Shell/Process/Windows/output_debug_string.cpp
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[lldb][Windows] Support OutputDebugString (#196395)
This picks https://reviews.llvm.org/D128541 back up. It implements
support for `OutputDebugStringA/W` on Windows. It's used by some logging
systems.
The main changes since the original patch:
- Use `WaitForDebugEventEx` for getting debug events over
`WaitForDebugEvent`. According to the
[docs](https://learn.microsoft.com/en-us/windows/win32/api/debugapi/nf-debugapi-waitfordebugeventex),
the only difference is that the -Ex version correctly outputs Unicode
strings.
- Support strings longer than 64 KiB. I set an arbitrary limit of 1 MiB
for the strings we read. The debugger interface only tells us the length
modulo 64 KiB which is a bit awkward. Libraries like Qt already chunk
calls to `OutputDebugString`, so strings shouldn't be too big in
practice.
- Output to stdout instead of a log channel, so the output is always
enabled. I don't know if this should go to stdout or stderr.
Tested that it works with lldb-dap and shows up in the debug console in
all modes.
Closes #185891.
---------
Co-authored-by: Alvin Wong <alvin at alvinhc.com>
Commit: 6180a4899ff913e0a0e2338e4d019b683f8f06da
https://github.com/llvm/llvm-project/commit/6180a4899ff913e0a0e2338e4d019b683f8f06da
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/source/Plugins/DynamicLoader/Windows-DYLD/CMakeLists.txt
M lldb/source/Plugins/DynamicLoader/Windows-DYLD/DynamicLoaderWindowsDYLD.cpp
A lldb/source/Plugins/DynamicLoader/Windows-DYLD/MSVCRTCFrameRecognizer.cpp
A lldb/source/Plugins/DynamicLoader/Windows-DYLD/MSVCRTCFrameRecognizer.h
M lldb/source/Plugins/Process/Windows/Common/CMakeLists.txt
R lldb/source/Plugins/Process/Windows/Common/MSVCRTCFrameRecognizer.cpp
R lldb/source/Plugins/Process/Windows/Common/MSVCRTCFrameRecognizer.h
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
Log Message:
-----------
[lldb][Windows] Register MSVCRTCFrameRecognizer from DynamicLoaderWindowsDYLD (#201097)
Commit: 2790e61b41949e4ce61faebdb1faed614ca14416
https://github.com/llvm/llvm-project/commit/2790e61b41949e4ce61faebdb1faed614ca14416
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/NonConstParameterCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/readability/non-const-parameter.cpp
Log Message:
-----------
[clang-tidy] Fix crash in readability-non-const-parameter with redecls (#200178)
The check matches `VarDecls` with `hasInitializer()`, which uses
`getAnyInitializer()` and may therefore match a redeclaration whose
initializer is attached to another declaration. So calling
`IgnoreParenCasts()` on `VD->getInit()` directly would crash when that
redeclaration had no initializer of its own.
This commit fixes the problem by using a new matcher that only matches
VarDecls with an initializer on the current declaration.
Closes https://github.com/llvm/llvm-project/issues/199197
Commit: 52fd3ec25a3d9a20efae59c453a2450bf633a970
https://github.com/llvm/llvm-project/commit/52fd3ec25a3d9a20efae59c453a2450bf633a970
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M libc/include/llvm-libc-macros/linux/unistd-macros.h
M libc/include/unistd.yaml
M libc/src/unistd/linux/sysconf.cpp
M libc/test/include/CMakeLists.txt
A libc/test/include/unistd_macros_test.cpp
M libc/test/src/unistd/sysconf_test.cpp
Log Message:
-----------
[libc] Define _POSIX_THREADS and support _SC_THREADS in sysconf (#201091)
Defined the _POSIX_THREADS macro to 202405L in unistd-macros.h for Linux
to signal POSIX thread support.
Also implemented runtime support for _SC_THREADS in sysconf, returning
_POSIX_THREADS, and added _SC_THREADS and _POSIX_THREADS to the public
unistd.yaml specification.
Added compile-time and runtime tests to verify _POSIX_THREADS definition
and sysconf(_SC_THREADS) behavior. Standardized header comments in
unistd-macros.h to conform to LLVM style.
Assisted-by: Automated tooling, human reviewed.
---------
Co-authored-by: Pavel Labath <pavel at labath.sk>
Commit: 0bbb91b73430cf6e436cb9c0fe61a2f280d9453b
https://github.com/llvm/llvm-project/commit/0bbb91b73430cf6e436cb9c0fe61a2f280d9453b
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
Log Message:
-----------
[lldb][NFCI] Cleanup AppleObjCClassDescriptorV2::ivar_t API (#200777)
Commit: bd85a10b0cbfde6e944da773c435b8006130848f
https://github.com/llvm/llvm-project/commit/bd85a10b0cbfde6e944da773c435b8006130848f
Author: Mirko Brkušanin <Mirko.Brkusanin at amd.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
A llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation-direct-chain.ll
A llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation-indirect.ll
A llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation.ll
M llvm/test/CodeGen/AMDGPU/dvgpr_sym_fail_too_many_block_size_16.ll
M llvm/test/CodeGen/AMDGPU/dvgpr_sym_fail_too_many_block_size_16_anon.ll
Log Message:
-----------
[AMDGPU] Do not propagate vgpr count in dVGPR mode (#187078)
When dVGPR mode is enabled chain functions should not propagate VGPR
counts from other chain callees. VGPRs are allocated before chaining to
a chain functions. We only propagate counts from non-chain callees.
Commit: 3db25f80895d281d2d3921bb15677e0c8de03c7a
https://github.com/llvm/llvm-project/commit/3db25f80895d281d2d3921bb15677e0c8de03c7a
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M libc/src/__support/File/linux/CMakeLists.txt
M libc/src/__support/File/linux/dir.cpp
M libc/src/__support/File/linux/file.cpp
M libc/src/__support/OSUtil/linux/CMakeLists.txt
M libc/src/__support/OSUtil/linux/auxv.h
M libc/src/__support/threads/linux/CMakeLists.txt
M libc/src/__support/threads/linux/thread.cpp
M libc/src/fcntl/linux/CMakeLists.txt
M libc/src/fcntl/linux/creat.cpp
M libc/src/spawn/linux/CMakeLists.txt
M libc/src/spawn/linux/posix_spawn.cpp
Log Message:
-----------
[libc] Use linux_syscalls::open instead of manual SYS_open ifdefs (#201089)
I needed to clean up a few types in file.cpp in order to match the
wrapper prototype.
Assisted by Gemini.
Commit: fda34a97729f254d1a184d341683132c4ec65489
https://github.com/llvm/llvm-project/commit/fda34a97729f254d1a184d341683132c4ec65489
Author: Christian Sigg <csigg at google.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/test/CodeGen/RISCV/riscv-cf-protection.c
Log Message:
-----------
[clang] Fix lit test after f341dab for envs that cannot write to file (#201121)
Commit: 023248a62673ce82045fa284022673882f209677
https://github.com/llvm/llvm-project/commit/023248a62673ce82045fa284022673882f209677
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/DebuggerThread.cpp
Log Message:
-----------
[lldb][Windows] Use LazyImport for WaitForDebugEventEx (#201118)
From
https://github.com/llvm/llvm-project/pull/196395#pullrequestreview-4409209050.
This uses `LazyImport` for `WaitForDebugEventEx` to simplify the import.
Commit: 492202ec237f97299c6c2070a79be4c10826992f
https://github.com/llvm/llvm-project/commit/492202ec237f97299c6c2070a79be4c10826992f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/shuffle-strided-with-offset-512.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
Log Message:
-----------
[X86] lowerShuffleWithPSHUFB - use getConstVector to create shuffle mask (#201122)
Avoids wasteful SDValue creation if the shuffle matching fails - and
makes it easier to match+merge compatible constant pool entries
Commit: 47347d24f0a9f68ae60a54ce2ab46a023b739b8d
https://github.com/llvm/llvm-project/commit/47347d24f0a9f68ae60a54ce2ab46a023b739b8d
Author: vsimion26 <vlad.simion at intel.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/Quant/IR/QuantTypes.h
M mlir/lib/Dialect/Quant/IR/QuantOps.cpp
M mlir/lib/Dialect/Quant/IR/QuantTypes.cpp
M mlir/lib/Dialect/Quant/IR/TypeDetail.h
M mlir/lib/Dialect/Quant/IR/TypeParser.cpp
A mlir/test/Dialect/Quant/invalid-quantile-types.mlir
M mlir/test/Dialect/Quant/parse-uniform-invalid.mlir
M mlir/test/Dialect/Quant/parse-uniform.mlir
A mlir/test/Dialect/Quant/quantile-types.mlir
Log Message:
-----------
Quantile Type and Low FP Support (#190321)
# **QuantileType: Composing with Interface-Based Storage Types in MLIR
Quantization**
## **Context**
Recent [community
work](https://discourse.llvm.org/t/rfc-extending-uniformquantizedtype-with-interface-based-support-for-new-storage-types-in-quant-dialect/87803)
(RFC by Roman-Pevnyi, Aug 2025)
successfully extended UniformQuantizedType with a StorageTypeInterface.
This
made the quantization framework extensible, allowing new storage types
(Integer, Float8E5M2, Float8E4M3FN, NF4) to be plugged in without
modifying
core quantization logic.
## **Building on that work**
QuantileType follows the same interface-driven philosophy but addresses
a
different level of abstraction: the storage type itself.
The observation: Many low-precision storage types (ui4, si8, f8, NF4)
can be enhanced with a quantile lookup table. Rather than creating a new
complete quantized type for each variant (QuantileQuantizedType,
QuantileQuantizedPerAxisType, etc.), we insert an abstraction layer.
QuantileType is a builtin that wraps any storage type with quantile
metadata:
quantile<ui4:f16, {-1.0, -0.696, ..., 1.0}>
quantile<si8:f32, {-2.0, -1.0, 0.0, 1.0, 2.0}>
quantile<f8E4M3FN:f16, {...}>
This storage abstraction then composes naturally with existing
quantization:
!quant.uniform<quantile<ui4:f16, {...}>:f32, scale:zeropoint>
## **Architecture**
Roman's StorageTypeInterface allows UniformQuantizedType to work with
any
compliant storage type. QuantileType extends this by making it possible
to
augment any storage type WITH quantile information, creating composable
layers:
Builtin QuantileType (unified storage + quantiles)
↓ (implements StorageTypeInterface)
UniformQuantizedType (uniform quantization logic)
↓
Hardware-specific lowering
## **Key benefits**
1. SINGLE INTERFACE FOR ALL QUANTILE SCHEMES
With QuantileType: One parameterized abstraction
quantile<ui4:f16, {nf4_table}>
quantile<ui4:f16, {custom_table}>
All compose with !quant.uniform naturally
[NF4
Type](https://github.com/openvinotoolkit/npu_compiler/blob/90b6098b9ee96055d633dc520354434bae22e336/src/vpux_compiler/include/vpux/compiler/core/types/quantile_float/types.hpp#L62)
& [NF4
Table](https://github.com/openvinotoolkit/npu_compiler/blob/90b6098b9ee96055d633dc520354434bae22e336/src/vpux_compiler/src/core/types/quantile_float/types.cpp#L116-L132)
2. EXTENSIBILITY FOR NEW STORAGE TYPES
When a new low-fp storage type is added (FP3, FPx, etc.),
it automatically works with quantiles:
quantile<fpx:f16, {...}>
No new dialect types needed. The type just implements
StorageTypeInterface
and QuantileType wraps it.
3. CLEAN SEPARATION OF CONCERNS
StorageTypeInterface:
- Defines what storage types must provide (width, signedness, min/max
values)
QuantileType (builtin abstraction):
- Wraps any StorageTypeInterface-compliant type with a lookup table
- Acts as a "storage + quantile mapping" layer
UniformQuantizedType (quantization logic):
- Works with any StorageTypeInterface, including QuantileType
## **Example IR**
In uniform quantization context:
!elem_type = !quant.uniform<quantile<ui4:f16, {-1.0, ..., 1.0}>:f32,
0.01:128>
QuantileType is a natural extension of the StorageTypeInterface
architecture. It:
- Provides a unified abstraction for quantile-enhanced storage
- Avoids type explosion by parameterizing rather than creating variants
- Maintains clean separation between storage concerns and quantization
logic
- Enables portability and reusability across MLIR consumers
Commit: 16853f627616581293a8561b5c00dad33056c75f
https://github.com/llvm/llvm-project/commit/16853f627616581293a8561b5c00dad33056c75f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/records.cpp
Log Message:
-----------
[clang][bytecode] Variadic ctors also start lifetime (#201113)
This is the same thing we do in the non-variadic `Call()`.
Commit: d25f10e8b4a37c2759925883fb59a9da4ea0eb94
https://github.com/llvm/llvm-project/commit/d25f10e8b4a37c2759925883fb59a9da4ea0eb94
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/docs/dil-expr-lang.ebnf
M lldb/include/lldb/ValueObject/DILAST.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/include/lldb/ValueObject/DILLexer.h
M lldb/include/lldb/ValueObject/DILParser.h
M lldb/source/ValueObject/DILAST.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILLexer.cpp
M lldb/source/ValueObject/DILParser.cpp
A lldb/test/API/commands/frame/var-dil/expr/Bitwise/Makefile
A lldb/test/API/commands/frame/var-dil/expr/Bitwise/TestFrameVarDILBitwise.py
A lldb/test/API/commands/frame/var-dil/expr/Bitwise/main.cpp
Log Message:
-----------
[lldb] Add bitwise shift operators and fix literals' sign in DIL (#192506)
This patch add bitwise shift operators and fixes the Scalar's sign
inside of the literals with signed types. The only way to test this fix,
for now, is to use these literals in an arithmetic right shift that does
sign extension, so this is included in this patch.
Commit: 720e796af81205c8cc215bf957db8f51d757fc8c
https://github.com/llvm/llvm-project/commit/720e796af81205c8cc215bf957db8f51d757fc8c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M flang-rt/lib/runtime/io-api-server.cpp
Log Message:
-----------
[flang-rt] Fix weak RPC stub on Mac-OS (#200998)
Summary:
This does not work like the ELF extern weak. Attempt to just provide a
weak function that will get overridden if it is linked in.
Commit: c24ae339133c6c893914a823613096f2334bba30
https://github.com/llvm/llvm-project/commit/c24ae339133c6c893914a823613096f2334bba30
Author: Christian Sigg <csigg at google.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
Log Message:
-----------
[bazel] Port 6180a48 (#201128)
Commit: 384c17f8259d1bad41afb40ada89a763aaa3615f
https://github.com/llvm/llvm-project/commit/384c17f8259d1bad41afb40ada89a763aaa3615f
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/test/TableGen/aarch64-apple-tuning-features.td
Log Message:
-----------
[AArch64] Use awk on aarch64-apple-tuning-features for AIX(NFC) (#200656)
See https://github.com/llvm/llvm-project/pull/197777
Commit: 47abd870986690ed50eab4de59c9dffa56ac24b7
https://github.com/llvm/llvm-project/commit/47abd870986690ed50eab4de59c9dffa56ac24b7
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/CaptureTracking.cpp
M llvm/test/Transforms/FunctionAttrs/writeonly.ll
Log Message:
-----------
[CaptureTracking] Don't require offset to stay the same (#201106)
For isIntrinsicReturningPointerAliasingArgumentWithoutCapturing() we
don't need the offset to stay the same. Even if the intrinsic applies an
offset to the pointer (like ptrmask), we can still continue by analyzing
the return value of the intrinsic, rather than considering the intrinsic
itself capturing.
Also clarify that this needs to stay in sync with isEscapeSource()
specifically, not getUnderlyingObject() or DecomposeGEP (which isn't
even possible, as they use different values for the argument). This used
to be different historically.
This was set to true in fd72bf21c958ae2fdfaa8654df55367c72575d3a, which
set all users to true, so I don't believe there was a specific reason
for this choice.
I ran into this when trying to replace some home-grown code in
FunctionAttrs with CaptureTracking.
Commit: 4d5a79542cef700f8201f113f370f35054a4e7d9
https://github.com/llvm/llvm-project/commit/4d5a79542cef700f8201f113f370f35054a4e7d9
Author: Christian Sigg <csigg at google.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel] Port 3db25f8 (#201131)
Commit: 68883a8b839f3f7f2adbae7a0e2dda3a0dd6b301
https://github.com/llvm/llvm-project/commit/68883a8b839f3f7f2adbae7a0e2dda3a0dd6b301
Author: Christian Sigg <csigg at google.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel] Port 3db25f8 (#201132)
Commit: 06978156c7ba8a8c8aca60033ea65c8335cca24c
https://github.com/llvm/llvm-project/commit/06978156c7ba8a8c8aca60033ea65c8335cca24c
Author: Kelvin Li <kli at ca.ibm.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M flang/lib/Lower/OpenMP/Atomic.cpp
Log Message:
-----------
[flang] Fix possibly unused variable (NFC) (#200905)
Commit: 5d9e965c3f9983278308a00c282810e0f04754cc
https://github.com/llvm/llvm-project/commit/5d9e965c3f9983278308a00c282810e0f04754cc
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/test/Sema/constexpr.c
Log Message:
-----------
[clang][ExprConst] Support DesignatedInitUpdateExpr of array type (#201000)
I think this should work.
Commit: ade0e1a49c2118a98b0b34b3136661747bc5aaa0
https://github.com/llvm/llvm-project/commit/ade0e1a49c2118a98b0b34b3136661747bc5aaa0
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/test/CIR/IR/invalid-cast.cir
M clang/test/CIR/Lowering/cast.cir
Log Message:
-----------
[cir] Refine cir::CastOp semantics for int <-> float casts (#200005)
Int-to-float and float-to-int casts in cir::CastOp are lowered directly
to their LLVM equivalents. Update the verifier to reflect this semantics
and ensure that, for vector casts, the source and destination vectors have
the same length.
This lets the CIR verifier reject invalid casts earlier, instead of relying
on errors reported later at the LLVM IR level.
Commit: 8f58a4cab3a7eccad53797a49e16f8a933d149b1
https://github.com/llvm/llvm-project/commit/8f58a4cab3a7eccad53797a49e16f8a933d149b1
Author: Jeremy Kun <jkun at google.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-copy.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-dealloc.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-load-store.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-copy.mlir
M mlir/test/Dialect/EmitC/attrs.mlir
M mlir/test/Dialect/EmitC/invalid_ops.mlir
A mlir/test/Dialect/EmitC/member_call_opaque.mlir
M mlir/test/Dialect/EmitC/ops.mlir
M mlir/test/Target/Cpp/call.mlir
M mlir/test/Target/Cpp/expressions.mlir
Log Message:
-----------
[mlir][emitc]: Add MemberCallOpaque op (#200057)
Cf. https://discourse.llvm.org/t/method-calls-in-emitc/90898
Commit: 87b97d67d401938086edc0602f55fe284bffc24d
https://github.com/llvm/llvm-project/commit/87b97d67d401938086edc0602f55fe284bffc24d
Author: David Spickett <david.spickett at arm.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang-tools-extra/docs/conf.py
Log Message:
-----------
[clang-tools-extra][docs] Do not require myst_parser when building man pages (#201138)
Commit: afd040cb4624c7c7f843367751e22d50b39250f5
https://github.com/llvm/llvm-project/commit/afd040cb4624c7c7f843367751e22d50b39250f5
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M openmp/tools/archer/ompt-tsan.cpp
Log Message:
-----------
[OpenMP][OMPT] Remove unused var in archer (#201140)
Working on enabling the build of OpenMP and Offload in pre-merge checks
surfaced this unused var and pre-merge checks run with -Werror.
As I did not see where it should be used, remove the variable to address
the warning.
The pre-merge running into the warning as error is
https://github.com/llvm/llvm-project/actions/runs/26826349862/job/79094823845?pr=174955
Commit: 8dd51399f8a9f13cbe35fb2060f05bd30acfb6f8
https://github.com/llvm/llvm-project/commit/8dd51399f8a9f13cbe35fb2060f05bd30acfb6f8
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/include/lldb/Target/Memory.h
M lldb/source/Target/Memory.cpp
Log Message:
-----------
[lldb][NFC] Factor out helper code from MemoryCache (#201120)
This will be reused in a subsequent commit.
Commit: f813817e3495c5ab8e0dd7d3c471e531d83a630a
https://github.com/llvm/llvm-project/commit/f813817e3495c5ab8e0dd7d3c471e531d83a630a
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
A llvm/test/CodeGen/SPIRV/transcoding/OpenCL/convert_signedness.ll
Log Message:
-----------
[SPIR-V] Select int-to-int convert opcode from source signedness (#201116)
OpSConvert/OpUConvert sext/zext is determined by the source operand, not
the destination type. Discovered in
https://github.com/llvm/llvm-project/pull/200791/changes#r3341230426
Fix a regression caused by #200791
Commit: 6bcdd843e302063c4f0d36204686155149a6bb0a
https://github.com/llvm/llvm-project/commit/6bcdd843e302063c4f0d36204686155149a6bb0a
Author: Paweł Bylica <pawel at hepcolgum.band>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrFragments.td
M llvm/test/CodeGen/X86/bittest-big-integer.ll
A llvm/test/CodeGen/X86/bt-merge-fuse.ll
Log Message:
-----------
[X86] Merge BT with a matching BTR/BTS/BTC (#193612)
Fixes #165291.
BTR/BTS/BTC set CF from the pre-operation bit value, so a subsequent BT
on the same source and bit index produces the same CF and is redundant.
We were emitting both.
```ll
define i1 @btr_eq_i32(ptr %word, i32 %position) nounwind {
%ofs = and i32 %position, 31
%bit = shl nuw i32 1, %ofs
%mask = xor i32 %bit, -1
%ld = load i32, ptr %word
%test = and i32 %ld, %bit
%res = and i32 %ld, %mask
%cmp = icmp eq i32 %test, 0
store i32 %res, ptr %word
ret i1 %cmp
}
```
Before:
```asm
movl (%rdi), %eax
movl %eax, %ecx
btrl %esi, %ecx
btl %esi, %eax
setae %al
movl %ecx, (%rdi)
retq
```
After:
```asm
movl (%rdi), %ecx
btrl %esi, %ecx
setae %al
movl %ecx, (%rdi)
retq
```
## Approach
- Add three flag-producing DAG nodes `X86ISD::{BTR,BTS,BTC}` that model
the register-register BTR/BTS/BTC as `(res, EFLAGS) = op src, bitno`.
- Pattern-match them to the existing BTR/BTS/BTC *rr encodings.
- Add a DAG combine in `combineBT` that fuses an `X86ISD::BT` with a
sibling `AND(Src, rotl -2, X)` / `OR(Src, shl 1, X)` / `XOR(Src, shl 1,
X)` on the same source into a single flag-producing node. The
bit-position operand can differ from BT's by trunc/zext or by an `and x,
C` that preserves the low `log2(BW)` bits (BT already masks those
implicitly), so peek through those wrappers when matching.
`llvm/test/CodeGen/X86/bittest-big-integer.ll` was regenerated and
shrinks by 78 CHECK lines; dozens of `btl` instructions collapsed into
the preceding bit-modify. All 5442 X86 CodeGen tests pass.
Commit: d81e8afe7a51005f5fa58cf4b25ccfdb41f685b1
https://github.com/llvm/llvm-project/commit/d81e8afe7a51005f5fa58cf4b25ccfdb41f685b1
Author: xgxanq <anqfu at amd.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
A llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll
Log Message:
-----------
[AMDGPU] RewriteMFMAFormStage: fix SpillCost early-return missing reset (#199708)
Extract resetRewriteCandsToVGPR() to consolidate the logic that restores
MFMA candidates from AGPR form back to VGPR form after cost analysis.
getRewriteCost() returned early when SpillCost > 0 without resetting the
AGPR-form register classes set by initHeuristics(), leaving MRI in a
corrupted state. Call resetRewriteCandsToVGPR() on both the early-return
path and the normal exit path to fix this.
Also change getRewriteCost() and rewrite() to take ArrayRef instead of
const std::vector& for cleaner API.
---------
Co-authored-by: Claude Sonnet 4 (1M context) <noreply at anthropic.com>
Commit: e8f518d6613b950958618db9466a5936d844ff26
https://github.com/llvm/llvm-project/commit/e8f518d6613b950958618db9466a5936d844ff26
Author: Sean Clarke <seanedwardsclarke at gmail.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll
M llvm/test/Transforms/InstCombine/masked_intrinsics.ll
M llvm/test/Transforms/InstCombine/pr83947.ll
M llvm/test/Transforms/InstSimplify/call.ll
Log Message:
-----------
[VectorUtils] Replace maskIsAll{Zero,One}OrUndef with PatternMatch (#200040)
As part of the ongoing effort to deprecate UndefValue, and also to take
better advantage of pattern matching, eliminate the VectorUtils
functions `maskIsAllZeroOrUndef`/`maskIsAllOneOrUndef` and replace them
with new matchers `m_ZeroOrPoison` and `m_AllOnesOrPoison`.
The new matchers are simply `m_CombineOr` on `m_Zero`/`m_AllOnes` and
`m_Poison`. `m_Zero` and `m_AllOnes` already match vectors where some
(but not all) elements are poison, so these matchers were created to
also match the case where all elements are poison.
This affects InstCombine/InstSimplify with a mask containing `undef` for
the intrinsics `llvm.masked.load`, `llvm.masked.store`,
`llvm.masked.gather`, and `llvm.masked.scatter`.
Some relevant tests were altered to use poison instead of undef, and
test coverage for masked loads/stores with poison was increased.
Commit: f834b7f55feb37191405bf28cca52f53f4c1873f
https://github.com/llvm/llvm-project/commit/f834b7f55feb37191405bf28cca52f53f4c1873f
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M offload/plugins-nextgen/level_zero/include/L0CmdListManager.h
M offload/plugins-nextgen/level_zero/include/L0Queue.h
M offload/plugins-nextgen/level_zero/src/L0Device.cpp
M offload/plugins-nextgen/level_zero/src/L0Queue.cpp
Log Message:
-----------
[OFFLOAD][L0] Move dataFence logic to L0Queue (#201046)
The dataFence device operation logic was still on L0Device. With this all the operations working on command lists have their logic consolidated in L0Queue.
Commit: 3dfd4f784d7d0837252482f28ed2c0ca99a109b0
https://github.com/llvm/llvm-project/commit/3dfd4f784d7d0837252482f28ed2c0ca99a109b0
Author: Utkarsh Saxena <usx at google.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h
M clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp
M clang/unittests/Analysis/LifetimeSafetyTest.cpp
Log Message:
-----------
[LifetimeSafety] Refactor buildOriginFlowChain to use PImpl pattern (#201071)
Move `buildOriginFlowChain` into `AnalysisImpl`, removing `FactManager`
parameter
Commit: b54d214b77aac2bab9b949bb4bdd3cc511fbe944
https://github.com/llvm/llvm-project/commit/b54d214b77aac2bab9b949bb4bdd3cc511fbe944
Author: Paul Kirth <paulkirth at google.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/test/MC/RISCV/rvi-pseudos.s
Log Message:
-----------
[llvm][RISCV][MC] Fix arithmetic error in pseudo parsing (#200217)
When arithmetic was used in RISCV pseudo instructions, like lla, the
custom parsing breaks the associativity of the operators by parsing the
entire remainder of an expression. This would lead to scenarios where we
would parse `top - 0x100 -0x10` as `top - (0x100 -0x10)` and yield the
wrong offset (`0xF0`(wrong) vs. `0x110`(correct)).
Instead, don't advance the parser and just examine the token to
determine if it's an identifier and if we should handle this case or
bail out. In cases we do handle, just use `parseExpression()`, which
will handle this correctly.
Commit: 0212229ac05d60314db7dfb8ae89c11a015bb7bc
https://github.com/llvm/llvm-project/commit/0212229ac05d60314db7dfb8ae89c11a015bb7bc
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M .ci/green-dragon/lldb-windows.groovy
Log Message:
-----------
[CI] install packaging before running lldb tests on Windows (#201112)
https://ci-external.swift.org/job/lldb-windows/job/main/ is failing
because lldb API tests require the `packaging` module.
This patch installs it before running the `check-lldb` target.
Commit: 63a1b9d6386cb574e3007f7b6174eb6777916815
https://github.com/llvm/llvm-project/commit/63a1b9d6386cb574e3007f7b6174eb6777916815
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir
Log Message:
-----------
[AArch64][SME] Add multi-vector store/load opcodes to getMemOpInfo (#201073)
Follow-up to #200238
Commit: 9083fb24c709238b1f18f0486bcf014e490e1997
https://github.com/llvm/llvm-project/commit/9083fb24c709238b1f18f0486bcf014e490e1997
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/test/API/commands/register/aarch64_dynamic_regset/main.c
M lldb/test/API/commands/register/aarch64_sve_registers/rw_access_static_config/main.c
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
M llvm/test/CodeGen/AArch64/aarch64-sme-za-call-lowering.ll
M llvm/test/CodeGen/AArch64/aarch64-sysreg128.ll
R llvm/test/CodeGen/AArch64/arm64-invalid-sys-reg.ll
A llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll
M llvm/test/CodeGen/AArch64/expand-sme-pseudos.mir
M llvm/test/CodeGen/AArch64/machine-sme-abi-find-insert-pt.mir
M llvm/test/CodeGen/AArch64/machine-sme-abi-skip-debug-inst.mir
M llvm/test/CodeGen/AArch64/sme-abi-eh-liveins.mir
M llvm/test/CodeGen/AArch64/sme-lazy-sve-nzcv-live.mir
M llvm/test/CodeGen/AArch64/special-reg.ll
M llvm/test/MC/AArch64/arm64-system-encoding.s
M llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s
M llvm/test/MC/AArch64/armv9-mrrs.s
M llvm/test/MC/AArch64/armv9-msrr-diagnostics.s
M llvm/test/MC/AArch64/armv9-msrr.s
M llvm/test/MC/AArch64/basic-a64-instructions.s
M llvm/test/MC/Disassembler/AArch64/armv8.2a-uao.txt
M llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt
M llvm/test/MC/Disassembler/AArch64/armv8.5a-dataproc.txt
M llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
M llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt
M llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt
M llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt
M llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
M llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt
M llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
Log Message:
-----------
Revert "[AArch64] Fix definition of system register move instructions" (#201137)
Reverts llvm/llvm-project#185709
Commit: 516867bc96ae3e3a40b296f038d24ee53cf0f5c0
https://github.com/llvm/llvm-project/commit/516867bc96ae3e3a40b296f038d24ee53cf0f5c0
Author: Henry Jiang <henry_jiang2 at apple.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/PseudoProbeInserter.cpp
A llvm/test/CodeGen/AArch64/aarch64-pseudo-probe-tail-call.ll
A llvm/test/CodeGen/X86/pseudo-probe-tail-call.ll
Log Message:
-----------
[PseudoProbe] Preserve pseudoprobe for tailcall pseudo instrs (#197246)
Preserve probes for tail call pseudo instructions.
On AArch64, X86, and other platforms, the lowering of tail calls
requires a pseudo instruction like `TCRETURNdi`. It is often the case
that `TCRETURNdi` is within its own MBB, and the direct call probe
associated with that tail call is considered dangling and removed. This
patch tries to preserve that.
Commit: cf25fb1e0809aaf4dbb13f2b837d47e329f595b8
https://github.com/llvm/llvm-project/commit/cf25fb1e0809aaf4dbb13f2b837d47e329f595b8
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M flang/lib/Semantics/check-omp-metadirective.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
A flang/test/Semantics/OpenMP/declare-variant-match.f90
M flang/test/Semantics/OpenMP/declare-variant.f90
Log Message:
-----------
[flang][OpenMP] Add structure checks for DECLARE VARIANT (#198799)
This PR adds declare-variant structure checking. Following checks are
added:
- Validate [base:]variant arguments (including implicit base for
single-name form).
- Require exactly one MATCH clause; reject a second MATCH on the same
directive.
- Reject duplicate (base, variant) across multiple declare variant
directives.
- Reject clauses not allowed on declare variant.
- Apply shared context-selector checks to MATCH (reuse metadirective
logic).
- Require constant user conditions in MATCH for declare variant (dynamic
selectors deferred).
Refactor metadirective support:
- Extract CheckContextSelectorSpecification for reuse.
- Reject SCORE on trait sets that do not allow it (also affects
metadirective).
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: 9f790fcc1f09ce4237801a7bb357d31a4c6050fb
https://github.com/llvm/llvm-project/commit/9f790fcc1f09ce4237801a7bb357d31a4c6050fb
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/test/CodeGen/SPIRV/transcoding/enqueue_kernel.ll
Log Message:
-----------
[SPIR-V] Fix i8 pointer type for NULL events in OpEnqueueKernel (#201125)
Commit: 7b199bdb2fe3d852684fab77bfdd3141dbc987f9
https://github.com/llvm/llvm-project/commit/7b199bdb2fe3d852684fab77bfdd3141dbc987f9
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/include/lldb/Symbol/Symbol.h
Log Message:
-----------
[lldb] Fix Symbol static_assert for 32 bit Windows (#201130)
Follow up to
https://github.com/llvm/llvm-project/pull/200919#issuecomment-4600914496
Commit: 22ef7baaf6dc409a353af42ff52599b2746107ca
https://github.com/llvm/llvm-project/commit/22ef7baaf6dc409a353af42ff52599b2746107ca
Author: Jake Daly <48452250+jakemdaly at users.noreply.github.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticIDs.h
Log Message:
-----------
[clang][NFC] Bump the maximum number of Sema diagnostics (#200948)
The number of Sema diagnostics in DiagnosticSemaKinds.td has reached the
5000 limit. This PR increases the max limit to 6000.
Commit: af5506c5c12d73439a9fc6f1951caf1cbde183cc
https://github.com/llvm/llvm-project/commit/af5506c5c12d73439a9fc6f1951caf1cbde183cc
Author: Petr Hosek <phosek at google.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
M llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll
M llvm/test/CodeGen/RISCV/frame.ll
M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
M llvm/test/CodeGen/RISCV/ipra.ll
M llvm/test/CodeGen/RISCV/large-stack.ll
M llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
M llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
M llvm/test/CodeGen/RISCV/rvv/stack-probing-dynamic.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
M llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
Log Message:
-----------
Revert "[RISCV] Prefer SP over FP for frame index access when offset fits within compressed immediate range. (#193962)" (#201041)
This reverts commits:
* 46e07d38e078799fa83386ef2b3b5ee423a467c5
* b5d577d3faef34276991fe80b5f869e3f8ef7442
This change is causing a miscompile in zstd, see the discussion under
https://github.com/llvm/llvm-project/pull/193962 for more details.
Commit: a6615588ac141ca87c4197f3484e80cb88899cee
https://github.com/llvm/llvm-project/commit/a6615588ac141ca87c4197f3484e80cb88899cee
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
Log Message:
-----------
[AMDGPU] Add IGLP mutations to CoexecSched (#200981)
Adds IGLP mutations support to CoexecSched -- regular handling of this
mutation in GCNSchedStage is implemented in GCNSchedStrategy.cpp
Commit: b65054f66b0a0d62c1a5fe0b3d7749696058d1c8
https://github.com/llvm/llvm-project/commit/b65054f66b0a0d62c1a5fe0b3d7749696058d1c8
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
A llvm/include/llvm/Transforms/Utils/TriggerCrashPass.h
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Transforms/Utils/CMakeLists.txt
A llvm/lib/Transforms/Utils/TriggerCrashPass.cpp
A llvm/test/Other/trigger-crash-flags.ll
M llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
Log Message:
-----------
Reland [LLVM] Add flags to crash the opt/codegen pipeline (#201146)
Will be used for testing crash reduction.
Reland of #200967. Test needs `REQUIRES: backtrace`.
Commit: 836bf567e622a2e083a0c850b861b450fc97b915
https://github.com/llvm/llvm-project/commit/836bf567e622a2e083a0c850b861b450fc97b915
Author: Fangrui Song <i at maskray.me>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/include/llvm/ADT/APFixedPoint.h
M llvm/include/llvm/ADT/APInt.h
M llvm/include/llvm/ADT/APSInt.h
M llvm/include/llvm/ADT/ArrayRef.h
M llvm/include/llvm/ADT/BitVector.h
M llvm/include/llvm/ADT/CachedHashString.h
M llvm/include/llvm/ADT/DenseMapInfo.h
M llvm/include/llvm/ADT/DenseMapInfoVariant.h
M llvm/include/llvm/ADT/Hashing.h
M llvm/include/llvm/ADT/ImmutableList.h
M llvm/include/llvm/ADT/PointerEmbeddedInt.h
M llvm/include/llvm/ADT/PointerIntPair.h
M llvm/include/llvm/ADT/PointerSumType.h
M llvm/include/llvm/ADT/PointerUnion.h
M llvm/include/llvm/ADT/SmallBitVector.h
M llvm/include/llvm/ADT/SmallVector.h
M llvm/include/llvm/ADT/StringRef.h
M llvm/include/llvm/Support/FileSystem/UniqueID.h
M llvm/include/llvm/Support/TypeSize.h
M llvm/include/llvm/Support/UniqueBBID.h
M llvm/include/llvm/Support/VersionTuple.h
M llvm/lib/Support/StringRef.cpp
M llvm/unittests/ADT/DenseMapTest.cpp
M llvm/unittests/ADT/DenseSetTest.cpp
M llvm/unittests/ADT/MapVectorTest.cpp
M llvm/unittests/Support/ReverseIterationTest.cpp
Log Message:
-----------
[ADT] Remove unused DenseMapInfo::getTombstoneKey (#200959)
#200595 changed DenseMap to no longer create tombstone buckets, so
DenseMapInfo<T>::getTombstoneKey() is never called. Remove dead
definitions and dead tombstone branches.
Commit: e3bc0828d8562468161d64e86a2fb06d39ca8d6f
https://github.com/llvm/llvm-project/commit/e3bc0828d8562468161d64e86a2fb06d39ca8d6f
Author: David Tenty <daltenty at ibm.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
A llvm/test/CodeGen/PowerPC/aix-codemodel.ll
M llvm/test/CodeGen/PowerPC/ppc-i128-cmp.ll
Log Message:
-----------
[AIX][LLVM] Update the default code model for 64-bit (#199301)
This changes the default code model on 64-bit AIX to large.
For many applications, the existing small code model is simply
inadequate to build. Users often then end up relying on expensive linker
fixups (i.e. -Wl,-bigtoc) to work around the issue when they would have
been better served by moving to the larger code model. Our analysis and
benchmarking leads us to believe this's generally a net benefit to
users.
(Assisted by AI)
Commit: 824fc060d46abbeda94c9a787ef94a81fbf12230
https://github.com/llvm/llvm-project/commit/824fc060d46abbeda94c9a787ef94a81fbf12230
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-device-2.mlir
Log Message:
-----------
[Flang][OpenMP] Declare Target fixes for USM and declare target to (#200248)
Currently declare target enter would fall through the if statement even
though it's a synonym of declare target to, so fix this via adding a
simpler and more readable check for link clause instead.
USM declare target to works a little differently to regular link cases,
where the type is actually converted into a pointer, rather than a
global of the original typing. So, add a caveat where we convert the
type to a pointer if requires usm has been triggered. This gets the
correct behaviour in USM mode on USM devices.
Commit: 3658dafe2c26c3e1242ff0505b9e8f95f0f5abf1
https://github.com/llvm/llvm-project/commit/3658dafe2c26c3e1242ff0505b9e8f95f0f5abf1
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/lib/Basic/Targets/OSTargets.h
Log Message:
-----------
[Driver] Switch clang++ to default Solaris 11.4 compilation environment (#201063)
`clang++` has long followed `g++`'s lead predefining `_XOPEN_SOURCE=600`
on Solaris. As detailed in [Switch g++ to default Solaris 11.4
compilation
environment](https://gcc.gnu.org/pipermail/gcc-patches/2026-May/716990.html),
this is no longer necessary in Solaris 11.4.
Tested on `amd64-pc-solaris2.11` and `sparcv9-sun-solaris2.11`.
Commit: 55af104f1c9eeb93ca127104b810bc2520100f9c
https://github.com/llvm/llvm-project/commit/55af104f1c9eeb93ca127104b810bc2520100f9c
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/arm/RegisterContextWindows_arm.cpp
M lldb/source/Plugins/Process/Windows/Common/x64/RegisterContextWindows_x64.cpp
M lldb/source/Plugins/Process/Windows/Common/x86/RegisterContextWindows_x86.cpp
Log Message:
-----------
[lldb][windows] return false in default branch of RegisterContextWindows_*::WriteRegister (#200885)
Commit: bc056ea2c2948d51455f6cf75975e4980b8b908f
https://github.com/llvm/llvm-project/commit/bc056ea2c2948d51455f6cf75975e4980b8b908f
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang-tools-extra/clangd/index/StdLib.cpp
M clang-tools-extra/clangd/index/SymbolCollector.cpp
M clang/include/clang/Basic/FileManager.h
R clang/include/clang/Basic/FileSystemStatCache.h
M clang/lib/Basic/CMakeLists.txt
M clang/lib/Basic/FileManager.cpp
R clang/lib/Basic/FileSystemStatCache.cpp
M clang/lib/Tooling/Tooling.cpp
M clang/unittests/Basic/FileManagerTest.cpp
Log Message:
-----------
[clang] Remove `FileSystemStatCache` (#198411)
This mechanism is not used anywhere, and can be easily reimplemented in
terms of a VFS if needed.
Commit: 13e532562f13ce94c7b7ffc8621252de92a29a42
https://github.com/llvm/llvm-project/commit/13e532562f13ce94c7b7ffc8621252de92a29a42
Author: Alex Langford <alangford at apple.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/decorators.py
Log Message:
-----------
[lldb] Skip simulator platform tests on arm64e (#200505)
Simulators do not support arm64e.
Commit: d9cf2e1bc5aaf2eaacc36c765b63429d42ac0c60
https://github.com/llvm/llvm-project/commit/d9cf2e1bc5aaf2eaacc36c765b63429d42ac0c60
Author: Zibi Sarbinowski <zibi at ca.ibm.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetInfo.h
M clang/lib/CodeGen/Targets/SystemZ.cpp
A clang/test/CodeGen/SystemZ/zos-abi.c
A clang/test/CodeGen/SystemZ/zos-abi.cpp
Log Message:
-----------
[SystemZ][z/OS] Add XPLink ABI on z/OS (#188501)
This patch introduces full support for the XPLINK calling convention on
z/OS within LLVM. XPLINK is documented in the Language Environment
Vendor Interface ([Chapter
22](https://www.ibm.com/docs/en/zos/3.2.0?topic=applications-call-linkage-convention-amode-64))
and in the IBM Redbook [XPLink: OS/390 Extra Performance
Linkage](http://www.redbooks.ibm.com/abstracts/sg245991.html?Open
). It defines a high‑performance linkage model used by the z/OS Language
Environment (LE) and by the XL C/C++ compiler.
This work succeeds and replaces the earlier effort in [PR
101024](https://github.com/llvm/llvm-project/pull/101024). The present
implementation restructures the original approach, significantly expands
test coverage, and aligns more closely with both the architectural
requirements of XPLINK and the de‑facto ABI behaviour of XL C/C++.
Commit: 6dfef47047def67fc141248eb8e7e2a67e4307e7
https://github.com/llvm/llvm-project/commit/6dfef47047def67fc141248eb8e7e2a67e4307e7
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M libcxx/test/libcxx/atomics/builtin_clear_padding.pass.cpp
Log Message:
-----------
[clang] Treat unnamed bitfields as padding in `__builtin_clear_padding` (#201102)
Currently Clang's implementation of `__builtin_clear_padding` diverges
from GCC in its treatment of unnamed bitfields.
GCC treats them as padding (which seems correct since they can't be
named and wouldn't be part of the value representation of an object,
though I'm not sure what the standard has to say about this).
[Gobdolt](https://godbolt.org/z/e9Mo91dhh)
GCC trunk:
```
pre-clear bytes: ff ff ff ff
post-clear bytes: 01 00 00 80
```
Clang trunk:
```
pre-clear bytes: ff ff ff ff
post-clear bytes: ff ff ff ff
```
Note how we cleared the padding with GCC.
This patch skips marking unnamed bitfields as "occupied". The rest of
the machinery works out-of-the-box.
Commit: 2511bdd645ee7b2ce01064b5fc31524c5e532480
https://github.com/llvm/llvm-project/commit/2511bdd645ee7b2ce01064b5fc31524c5e532480
Author: Alex Langford <alangford at apple.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/test/API/qemu/TestQemuLaunch.py
Log Message:
-----------
[lldb] Skip TestQemuLaunch.py on arm64e (#200969)
This test is set up to use a python-based qemu-like stub instead of the
actual qemu (which makes it far more portable). When trying to run the
test as arm64e, LLDB will attempt to launch an arm64e-based qemu.
Because the fake qemu is a python script, LLDB will try to launch python
as arm64e. Neither the python that ships with Xcode nor the python from
python.org have an arm64e slice, so this test will not work for arm64e.
Commit: 05d152bd59372aa3e10bbf06deae5795a81052d9
https://github.com/llvm/llvm-project/commit/05d152bd59372aa3e10bbf06deae5795a81052d9
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/struct_in6_addr.h
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/struct_in6_addr.h
M libc/include/netinet/in.yaml
M libc/test/src/netinet/CMakeLists.txt
A libc/test/src/netinet/in_test.cpp
Log Message:
-----------
[libc] Add definition of struct in6_addr to netinet/in.h (#201057)
This patch implements the struct in6_addr definition for netinet/in.h,
mapping it from netinet/in.yaml to the generated public header.
I've defined struct in6_addr under include/llvm-libc-types/ using an
anonymous union containing s6_addr, s6_addr16, and s6_addr32 (only the
first one is mandated by POSIX). Other implementations achieve this by
using a named union and defining the members as macros. This approach is
cleaner, but could potentially run into compatibility problems with code
which expects s6_addr is a macro. If we do, we may have to re-evaluate
this approach, but I'd like to avoid uglyfying this preemptively.
I added a simple test to check the memory layout of the address.
Assisted by Gemini.
Commit: fe2f7e40994574dd5d7efa4da8be5d9237905416
https://github.com/llvm/llvm-project/commit/fe2f7e40994574dd5d7efa4da8be5d9237905416
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/include/clang/Driver/CommonArgs.h
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/include/flang/Frontend/CodeGenOptions.def
M flang/lib/Frontend/CompilerInstance.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
A flang/test/Driver/function-sections.f90
A flang/test/Integration/function-sections.f90
Log Message:
-----------
[flang] Support -ffunction-sections and -fdata-sections. (#199731)
Wire the flags through the driver, frontend, and TargetMachine, and add
driver and codegen lit tests.
Fixes https://github.com/llvm/llvm-project/issues/163550
---------
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: f3dcf16115f862f6fa5ea8e520b371f7e57a9c3d
https://github.com/llvm/llvm-project/commit/f3dcf16115f862f6fa5ea8e520b371f7e57a9c3d
Author: Chi-Chun, Chen <chichun.chen at hpe.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
R flang/test/Lower/OpenMP/Todo/begin-metadirective.f90
A flang/test/Lower/OpenMP/Todo/metadirective-declarative.f90
A flang/test/Lower/OpenMP/Todo/metadirective-dynamic.f90
R flang/test/Lower/OpenMP/Todo/metadirective-exec.f90
A flang/test/Lower/OpenMP/Todo/metadirective-loop.f90
R flang/test/Lower/OpenMP/Todo/metadirective-spec.f90
A flang/test/Lower/OpenMP/Todo/metadirective-structured-trait-property.f90
A flang/test/Lower/OpenMP/Todo/metadirective-target-device.f90
A flang/test/Lower/OpenMP/metadirective-construct.f90
A flang/test/Lower/OpenMP/metadirective-device-arch.f90
A flang/test/Lower/OpenMP/metadirective-device-isa.f90
A flang/test/Lower/OpenMP/metadirective-device-kind.f90
A flang/test/Lower/OpenMP/metadirective-implementation.f90
A flang/test/Lower/OpenMP/metadirective-nothing.f90
A flang/test/Lower/OpenMP/metadirective-user.f90
M flang/test/Semantics/OpenMP/metadirective-common.f90
Log Message:
-----------
[flang][OpenMP] Support lowering of metadirective (part 1) (#193664)
Add lowering support for OpenMP metadirective variants that can be
selected statically. Selection is performed during lowering with
`llvm::omp::OMPContext`, and only the selected directive variant is
lowered.
For example:
```fortran
subroutine static_vendor()
!$omp metadirective &
!$omp & when(implementation={vendor(llvm)}: barrier) &
!$omp & otherwise(nothing)
end subroutine
```
is lowered to a function containing `omp.barrier`, because `vendor(llvm)` is statically applicable when compiling with Flang.
Applicable variants are represented with `llvm::omp::VariantMatchInfo` and ranked using OpenMP context matching and selector scores from the LLVM frontend.
This patch supports both standalone metadirectives and begin/end
metadirectives. For begin/end metadirectives, the variant is selected
before lowering the enclosed region so that the selected directive
correctly wraps the region.
This initial static-resolution PR supports:
* implementation={vendor(...)}
* device={kind(...), isa(...), arch(...)}
* user={condition(<constant-expr>)}
* construct={parallel, target, teams, for}
* default, nothing, and otherwise clauses
This patch also preserves `score(...)` on constant user conditions so scored conditions participate correctly in variant ranking. When matching nested construct selectors, it includes constructs introduced by an enclosing selected begin/end metadirective.
Dynamic user conditions (#194424), `target_device` selectors, loop-associated directive variants, and complete construct support are deferred to follow-up patches.
This patch is part of the feature work for #188820.
Assisted by GitHub Copilot and GPT-5.4.
Commit: 0d51fec35520f39f9b2f55989f50d694244c7582
https://github.com/llvm/llvm-project/commit/0d51fec35520f39f9b2f55989f50d694244c7582
Author: Justin Lebar <justin.lebar at gmail.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/test/CodeGen/NVPTX/shift-opt.ll
Log Message:
-----------
[NVPTX] PerformSELECTShiftCombine drops high bits of a wide guarded shift amount (#201165)
LLVM shifts produce poison if you shift greater than the width of the
operand. But PTX shifts clamp the shift amount:
> shl/shr: Shift amounts greater than the register width N are clamped
> to N.
NVPTXISelLowering looks for shl/shr which guard against an out-of-range
shift and lower these to an unguarded PTX shift:
define i64 @f(i64 %x, i64 %shift) {
%cmp = icmp ult i64 %shift, 64
%shl = shl i64 %x, %shift
%sel = select i1 %cmp, i64 %shl, i64 0
ret i64 %sel
}
In PTX shifts the shift amount is always i32, whereas in LLVM the shift
amount is the same type as the "shiftee". Therefore in the i64 case,
this lowering is only sound if we know that the upper 32 bits of the
shift amount are all zero.
Commit: e21e5489588c2944d5071b52bdbca684a72c756f
https://github.com/llvm/llvm-project/commit/e21e5489588c2944d5071b52bdbca684a72c756f
Author: Vicky Nguyen <vicky.trucviennguyen at gmail.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[CIR][AArch64] Upstream vector-shift-right-and-accumulate NEON builtins (#200630)
Related to https://github.com/llvm/llvm-project/issues/185382
CIR lowering for vector-shift-right-and-accumulate
(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-right-and-accumulate)
Port tests from `clang/test/CodeGen/AArch64/neon_intrinsics.c` to
`clang/test/CodeGen/AArch64/neon/intrinsics.c`
Commit: ff1c751223a0e99a4563743abaaa5faa50d2ed6e
https://github.com/llvm/llvm-project/commit/ff1c751223a0e99a4563743abaaa5faa50d2ed6e
Author: Jun Wang <jwang_2024 at outlook.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/docs/AMDGPU/AMDGPUAsmGFX12.rst
R llvm/docs/AMDGPU/gfx12_addr.rst
R llvm/docs/AMDGPU/gfx12_attr.rst
R llvm/docs/AMDGPU/gfx12_clause.rst
R llvm/docs/AMDGPU/gfx12_data0_56f215.rst
R llvm/docs/AMDGPU/gfx12_data0_6802ce.rst
R llvm/docs/AMDGPU/gfx12_data0_e016a1.rst
R llvm/docs/AMDGPU/gfx12_data0_fd235e.rst
R llvm/docs/AMDGPU/gfx12_data1_6802ce.rst
R llvm/docs/AMDGPU/gfx12_data1_731030.rst
R llvm/docs/AMDGPU/gfx12_data1_e016a1.rst
R llvm/docs/AMDGPU/gfx12_data1_fd235e.rst
R llvm/docs/AMDGPU/gfx12_delay.rst
R llvm/docs/AMDGPU/gfx12_hwreg.rst
R llvm/docs/AMDGPU/gfx12_imm16.rst
R llvm/docs/AMDGPU/gfx12_ioffset.rst
R llvm/docs/AMDGPU/gfx12_label.rst
R llvm/docs/AMDGPU/gfx12_literal_1f74c7.rst
R llvm/docs/AMDGPU/gfx12_literal_81e671.rst
R llvm/docs/AMDGPU/gfx12_m.rst
A llvm/docs/AMDGPU/gfx12_operands.rst
R llvm/docs/AMDGPU/gfx12_rsrc_5fe6d8.rst
R llvm/docs/AMDGPU/gfx12_rsrc_c9f929.rst
R llvm/docs/AMDGPU/gfx12_saddr_cdc95c.rst
R llvm/docs/AMDGPU/gfx12_saddr_d42b64.rst
R llvm/docs/AMDGPU/gfx12_samp.rst
R llvm/docs/AMDGPU/gfx12_sbase_453b95.rst
R llvm/docs/AMDGPU/gfx12_sbase_47adb7.rst
R llvm/docs/AMDGPU/gfx12_sdata_0974a4.rst
R llvm/docs/AMDGPU/gfx12_sdata_354189.rst
R llvm/docs/AMDGPU/gfx12_sdata_4585b8.rst
R llvm/docs/AMDGPU/gfx12_sdata_5c7b50.rst
R llvm/docs/AMDGPU/gfx12_sdata_6c003b.rst
R llvm/docs/AMDGPU/gfx12_sdata_836716.rst
R llvm/docs/AMDGPU/gfx12_sdata_d725ab.rst
R llvm/docs/AMDGPU/gfx12_sdata_dd9dd8.rst
R llvm/docs/AMDGPU/gfx12_sdst_006c40.rst
R llvm/docs/AMDGPU/gfx12_sdst_20064d.rst
R llvm/docs/AMDGPU/gfx12_sdst_354189.rst
R llvm/docs/AMDGPU/gfx12_sdst_836716.rst
R llvm/docs/AMDGPU/gfx12_sdst_ced58d.rst
R llvm/docs/AMDGPU/gfx12_sdst_e701cc.rst
R llvm/docs/AMDGPU/gfx12_sendmsg.rst
R llvm/docs/AMDGPU/gfx12_sendmsg_rtn.rst
R llvm/docs/AMDGPU/gfx12_simm16_15ccdd.rst
R llvm/docs/AMDGPU/gfx12_simm16_218bea.rst
R llvm/docs/AMDGPU/gfx12_simm16_39b593.rst
R llvm/docs/AMDGPU/gfx12_simm16_3d2a4f.rst
R llvm/docs/AMDGPU/gfx12_simm16_730a13.rst
R llvm/docs/AMDGPU/gfx12_simm16_7ed651.rst
R llvm/docs/AMDGPU/gfx12_simm16_81e671.rst
R llvm/docs/AMDGPU/gfx12_simm16_c98889.rst
R llvm/docs/AMDGPU/gfx12_simm16_cc1716.rst
R llvm/docs/AMDGPU/gfx12_simm16_ee8b30.rst
R llvm/docs/AMDGPU/gfx12_soffset_8ec073.rst
R llvm/docs/AMDGPU/gfx12_soffset_c5b88c.rst
R llvm/docs/AMDGPU/gfx12_soffset_ec005a.rst
R llvm/docs/AMDGPU/gfx12_src0_5727cf.rst
R llvm/docs/AMDGPU/gfx12_src0_5cae62.rst
R llvm/docs/AMDGPU/gfx12_src0_6802ce.rst
R llvm/docs/AMDGPU/gfx12_src0_85aab6.rst
R llvm/docs/AMDGPU/gfx12_src0_c4593f.rst
R llvm/docs/AMDGPU/gfx12_src0_e016a1.rst
R llvm/docs/AMDGPU/gfx12_src0_fd235e.rst
R llvm/docs/AMDGPU/gfx12_src1_5727cf.rst
R llvm/docs/AMDGPU/gfx12_src1_5cae62.rst
R llvm/docs/AMDGPU/gfx12_src1_6802ce.rst
R llvm/docs/AMDGPU/gfx12_src1_731030.rst
R llvm/docs/AMDGPU/gfx12_src1_977794.rst
R llvm/docs/AMDGPU/gfx12_src1_c4593f.rst
R llvm/docs/AMDGPU/gfx12_src1_e016a1.rst
R llvm/docs/AMDGPU/gfx12_src1_fd235e.rst
R llvm/docs/AMDGPU/gfx12_src2_2797bc.rst
R llvm/docs/AMDGPU/gfx12_src2_5727cf.rst
R llvm/docs/AMDGPU/gfx12_src2_5cae62.rst
R llvm/docs/AMDGPU/gfx12_src2_6802ce.rst
R llvm/docs/AMDGPU/gfx12_src2_7b936a.rst
R llvm/docs/AMDGPU/gfx12_src2_96fbd3.rst
R llvm/docs/AMDGPU/gfx12_src2_c4593f.rst
R llvm/docs/AMDGPU/gfx12_src2_e016a1.rst
R llvm/docs/AMDGPU/gfx12_srcx0.rst
R llvm/docs/AMDGPU/gfx12_srcy0.rst
R llvm/docs/AMDGPU/gfx12_ssrc0_007f9c.rst
R llvm/docs/AMDGPU/gfx12_ssrc0_1a9ca5.rst
R llvm/docs/AMDGPU/gfx12_ssrc0_245536.rst
R llvm/docs/AMDGPU/gfx12_ssrc0_2797bc.rst
R llvm/docs/AMDGPU/gfx12_ssrc0_bbb4c6.rst
R llvm/docs/AMDGPU/gfx12_ssrc0_c4593f.rst
R llvm/docs/AMDGPU/gfx12_ssrc1_bbb4c6.rst
R llvm/docs/AMDGPU/gfx12_ssrc1_c4593f.rst
R llvm/docs/AMDGPU/gfx12_tgt.rst
R llvm/docs/AMDGPU/gfx12_vaddr_a972b9.rst
R llvm/docs/AMDGPU/gfx12_vaddr_c12f43.rst
R llvm/docs/AMDGPU/gfx12_vaddr_c8b8d4.rst
R llvm/docs/AMDGPU/gfx12_vaddr_d82160.rst
R llvm/docs/AMDGPU/gfx12_vaddr_f2b449.rst
R llvm/docs/AMDGPU/gfx12_vcc.rst
R llvm/docs/AMDGPU/gfx12_vdata_2eda77.rst
R llvm/docs/AMDGPU/gfx12_vdata_48e42f.rst
R llvm/docs/AMDGPU/gfx12_vdata_69a144.rst
R llvm/docs/AMDGPU/gfx12_vdata_89680f.rst
R llvm/docs/AMDGPU/gfx12_vdata_aac3e8.rst
R llvm/docs/AMDGPU/gfx12_vdata_bdb32f.rst
R llvm/docs/AMDGPU/gfx12_vdst_006c40.rst
R llvm/docs/AMDGPU/gfx12_vdst_227281.rst
R llvm/docs/AMDGPU/gfx12_vdst_2eda77.rst
R llvm/docs/AMDGPU/gfx12_vdst_47d3bc.rst
R llvm/docs/AMDGPU/gfx12_vdst_48e42f.rst
R llvm/docs/AMDGPU/gfx12_vdst_69a144.rst
R llvm/docs/AMDGPU/gfx12_vdst_7de8e7.rst
R llvm/docs/AMDGPU/gfx12_vdst_836716.rst
R llvm/docs/AMDGPU/gfx12_vdst_89680f.rst
R llvm/docs/AMDGPU/gfx12_vdst_bdb32f.rst
R llvm/docs/AMDGPU/gfx12_vdstx.rst
R llvm/docs/AMDGPU/gfx12_vdsty.rst
R llvm/docs/AMDGPU/gfx12_version.rst
R llvm/docs/AMDGPU/gfx12_vsrc0.rst
R llvm/docs/AMDGPU/gfx12_vsrc1_6802ce.rst
R llvm/docs/AMDGPU/gfx12_vsrc1_fd235e.rst
R llvm/docs/AMDGPU/gfx12_vsrc2.rst
R llvm/docs/AMDGPU/gfx12_vsrc3.rst
R llvm/docs/AMDGPU/gfx12_vsrc_56f215.rst
R llvm/docs/AMDGPU/gfx12_vsrc_6802ce.rst
R llvm/docs/AMDGPU/gfx12_vsrc_89fd7b.rst
R llvm/docs/AMDGPU/gfx12_vsrc_e016a1.rst
R llvm/docs/AMDGPU/gfx12_vsrc_fd235e.rst
R llvm/docs/AMDGPU/gfx12_vsrcx1.rst
R llvm/docs/AMDGPU/gfx12_vsrcy1.rst
R llvm/docs/AMDGPU/gfx12_waitcnt.rst
Log Message:
-----------
[AMDGPU][docs][NFC] Update gfx12 documentation (#200976)
Following what we did with the GFX950 documentation, this patch replaces
the multitude of rst files for GFX12 operands with a single file. Some
problems are fixed as well, e.g., different opcodes in the same encoding
(e.g., VDS) may have different modifiers.
Commit: 9c61a544c60b9e100d855aa95fa66b07d56a2bdf
https://github.com/llvm/llvm-project/commit/9c61a544c60b9e100d855aa95fa66b07d56a2bdf
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/copyable-operand-non-scheduled-parent-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/external-bin-op-user.ll
Log Message:
-----------
[SLP] Schedule copyable operands modeled on non-scheduled parent nodes
A node that does not need scheduling (all values used outside the block)
has no schedule bundle, yet it can still model one of its operands as a
copyable element, registering the ScheduleCopyableData on that parent
edge. If the instruction carrying that dependency is scheduled through a
different (duplicate) bundle, the copyable dependency on the non-scheduled
edge was never decremented.
When scheduling a bundle member, also process the instruction's tree
entries that have no registered bundle via pseudo-bundles, so their
copyable operand dependencies are decremented. Real operand dependencies
are guarded against double counting by the per-operand use counter.
Fixes #200831.
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/201182
Commit: c6c633740c305684645ec2b093bf36587fdbc54f
https://github.com/llvm/llvm-project/commit/c6c633740c305684645ec2b093bf36587fdbc54f
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M libc/include/CMakeLists.txt
M libc/include/arpa/inet.yaml
M libc/include/llvm-libc-macros/CMakeLists.txt
A libc/include/llvm-libc-macros/inet-address-macros.h
M libc/include/llvm-libc-macros/netinet-in-macros.h
M libc/include/netinet/in.yaml
M libc/utils/docgen/arpa/inet.yaml
Log Message:
-----------
[libc] Move INET_ADDRSTRLEN and INET6_ADDRSTRLEN to a common header (#201083)
INET_ADDRSTRLEN and INET6_ADDRSTRLEN are needed by both <netinet/in.h>
and <arpa/inet.h>. Previously we had them defined directly inside
netinet-in-macros.h, which meant arpa/inet.h did not have access to
them.
I've moved them to a new inet-address-macros.h header and configured
both YAML header targets to depend on it so they get included in both
generated headers.
I'm also updating the docgen YAML file for arpa/inet.h to document these
macros.
Note that other libc implementations simply have arpa/inet.h include
netinet/in.h (which is permitted by POSIX). This implementation takes a
stricter stance and only exposes the symbols which are specified by
POSIX.
Assisted by Gemini.
Commit: 1d77b84e5133bfd39489ed6f119beff91f9db194
https://github.com/llvm/llvm-project/commit/1d77b84e5133bfd39489ed6f119beff91f9db194
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] incDecVectorConstant - use getConstVector (#201169)
Avoids wasteful SDValue creation if the fold fails
Commit: 6656fa57d610475a55ed1dd909e40b00190a4615
https://github.com/llvm/llvm-project/commit/6656fa57d610475a55ed1dd909e40b00190a4615
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
Log Message:
-----------
[SandboxVec][VecUtils][NFC] Improve VecUtils::areConsecutive() template (#201168)
This helps drop the second template argument.
Commit: 7d2dce084307356948a3ef78c902fd68558afe2e
https://github.com/llvm/llvm-project/commit/7d2dce084307356948a3ef78c902fd68558afe2e
Author: Adrian Prantl <aprantl at apple.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/source/Commands/CommandObjectSettings.cpp
Log Message:
-----------
[LLDB] Add always-on logging for "settings set" (#201185)
When triaging bugreports it can be very useful to understand what LLDB
defaults have been changed. Adding settings to the always-on logging
channel helps with that.
rdar://176482205
Assisted-by: claude
Commit: 51f698d450133946c84b1702f7f460eedf701a84
https://github.com/llvm/llvm-project/commit/51f698d450133946c84b1702f7f460eedf701a84
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/utils/gn/build/sync_source_lists_from_cmake.py
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/bugprone/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/AST/ByteCode/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/DynamicLoader/Windows-DYLD/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Windows/Common/BUILD.gn
Log Message:
-----------
[gn build] Port commits (#201189)
And fix an issue with sync_source_lists_from_cmake.py breaking
Transforms/IPO/BUILD.gn.
5148d2de75ec
6180a4899ff9
bc056ea2c294
ff2fec30ac7c
Commit: f77f5088145b008f17799487e07a92c66e749567
https://github.com/llvm/llvm-project/commit/f77f5088145b008f17799487e07a92c66e749567
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/DWARFLinker/Parallel/DependencyTracker.cpp
A llvm/test/tools/dsymutil/Inputs/drop-module-fwd-decl/debug-map.map
A llvm/test/tools/dsymutil/Inputs/drop-module-fwd-decl/input.ll
A llvm/test/tools/dsymutil/Inputs/keep-module-fwd-decl-template/debug-map.map
A llvm/test/tools/dsymutil/Inputs/keep-module-fwd-decl-template/input.ll
A llvm/test/tools/dsymutil/X86/drop-module-fwd-decl.test
A llvm/test/tools/dsymutil/X86/keep-module-fwd-decl-template.test
M llvm/test/tools/dsymutil/X86/submodules.m
Log Message:
-----------
[DWARFLinker] Preserve module forward decls in parallel linker (#198828)
The parallel linker was dropping forward-declared types nested under
DW_TAG_module skeleton CUs (clang -gmodules input). The classic linker
keeps them when no definition exists and replaces them with the
canonical definition when one does. collectRootsToKeep's default branch
silently fell through, so the forward decl never made it to the
worklist.
Route these through the type pool with MarkTypeEntryRec. Recursive
marking keeps children of templated forward decls (e.g.
DW_TAG_template_type_parameter under Foo<T> [decl]) intact, matching the
classic linker. The existing decl-vs-def race resolution in
allocateTypeDie and getFinalDie handles both ends without new
synchronization.
- No definition anywhere. DeclarationDie is allocated and emitted.
- Definition in some other CU. allocateTypeDie sets Die via the body's
spinlock. At emission, getFinalDie returns Die over DeclarationDie. Both
clone orderings yield the same output.
For non-ODR languages getFinalPlacementForEntry forces PlainDwarf, so
the forward decl stays in place under its module instead of moving to
the artificial type unit.
Commit: 6a55cb00521b57df7c170d9c888b72c4fe48bc17
https://github.com/llvm/llvm-project/commit/6a55cb00521b57df7c170d9c888b72c4fe48bc17
Author: Justin Lebar <justin.lebar at gmail.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/test/CodeGen/NVPTX/globals_init.ll
Log Message:
-----------
[NVPTX] Print the full value of e.g. an i65 global. (#201184)
If you have an integer global whose width is 64 and not a multiple of 8,
the NVPTX asm printer used to drop the top bits!
Commit: eaff67c9838f98d221aa563c9e5d4e714d636674
https://github.com/llvm/llvm-project/commit/eaff67c9838f98d221aa563c9e5d4e714d636674
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/hip-toolchain-no-rdc.hip
M clang/test/Driver/hipspv-toolchain.hip
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper-hip-no-rdc.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td
Log Message:
-----------
[HIP][AMDGPU] Use non-LTO pipeline for non-RDC in the linker wrapper (#201135)
Non-RDC HIP does not need LTO, but the new offload driver compiles all
AMDGPU device code through the LTO pipeline. That makes non-RDC builds
pay
full LTO codegen cost for no benefit.
Fix this in clang-linker-wrapper instead of the driver, so device
codegen
still runs in the wrapper's parallel device-link step (kept fast by
--offload-jobs) rather than being serialized back in the driver.
The driver passes a new --no-lto flag for the non-RDC fat-binary job
(unless the user asked for -foffload-lto). With it, the wrapper drops
-flto
and, because the device images are bitcode stored in object-extension
files, also passes -x ir so clang actually compiles them (cc1 -emit-obj)
instead of handing the bitcode to lld for an LTO link.
Commit: 973b9a7d40ca42571d25f670b74177b1cdcbef61
https://github.com/llvm/llvm-project/commit/973b9a7d40ca42571d25f670b74177b1cdcbef61
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
Log Message:
-----------
Revert "[SandboxVec][VecUtils][NFC] Improve VecUtils::areConsecutive() template" (#201191)
Reverts llvm/llvm-project#201168
Commit: b89bb06afd069aa1b5e9f05ab692b3e6b41318c0
https://github.com/llvm/llvm-project/commit/b89bb06afd069aa1b5e9f05ab692b3e6b41318c0
Author: Ian Anderson <iana at apple.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/include/clang/Basic/DarwinSDKInfo.h
M clang/lib/Basic/DarwinSDKInfo.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Darwin.h
M clang/unittests/Basic/DarwinSDKInfoTest.cpp
Log Message:
-----------
[clang][driver][darwin] Hold onto full triples in Darwin SDKPlatformInfo (#200896)
The architecture can be relevant when determining if an SDK supports a
particular triple. Record the full triples in SDKPlatformInfo instead of
all of the non-architecture triple components.
Assisted-by: Claude Code
rdar://172876443
Commit: e15e51089e6a5faef7643d8dc123788f7e91f9fc
https://github.com/llvm/llvm-project/commit/e15e51089e6a5faef7643d8dc123788f7e91f9fc
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/ARM/extract-cost-scale-nullptr-user.ll
Log Message:
-----------
[SLP][NFC] Add a test with the optimistic extractelements emission, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/201192
Commit: f394094f195b3d593336aab6b76ccd2b7b483e43
https://github.com/llvm/llvm-project/commit/f394094f195b3d593336aab6b76ccd2b7b483e43
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/ARM/extract-cost-scale-nullptr-user.ll
Log Message:
-----------
[SLP] Scale extract cost of external uses with nullptr user
The NCD pre-pass from #199962 only records extract blocks for external
uses that have a real user, so uses with a nullptr user were left
unscaled, making the loop in the report look profitable and get wrongly
vectorized. For a nullptr user vectorizeTree() places the extract right
after the vectorized instruction (entry block) and RAUWs the scalar, so
scale those extracts by the entry block frequency, restoring the
pre-#199962 behavior for that case.
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/201193
Commit: 1fe6d564523982d2efbd28334ef50fe449765eb5
https://github.com/llvm/llvm-project/commit/1fe6d564523982d2efbd28334ef50fe449765eb5
Author: Justin Bogner <mail at justinbogner.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M third-party/benchmark/src/sysinfo.cc
Log Message:
-----------
Fix a warning and an uninitialized variable in benchmark (#200927)
After #198964 I see a -Wcovered-switch-default warning in sysinfo.cc,
but it looks like it's uncovering something a bit worse.
Back in #147357 and #149159 it looks like we tried to fix an MSVC
warning for an uncovered `CacheUnknown` case in this switch, and removed
the initialization of the variable before the switch. The update to
Google Benchmark v1.9.5 has a different fix for this - it's handling
that specific case guarded by some MSVC version macros, but this depends
on the initialization we removed!
Add the initialization back and remove the default case, effectively
reverting #149159 and #147357.
Commit: 798d0f5ee8644d9745922970515071d3fe338cb6
https://github.com/llvm/llvm-project/commit/798d0f5ee8644d9745922970515071d3fe338cb6
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/docs/MarkdownQuickstartTemplate.md
M llvm/docs/README.txt
A llvm/docs/SphinxQuickstartTemplate.md
R llvm/docs/SphinxQuickstartTemplate.rst
M openmp/docs/README.txt
Log Message:
-----------
[docs] Rename SphinxQuickstartTemplate.{rst|md} for blame (#198899)
Renames SphinxQuickstartTemplate.rst to SphinxQuickstartTemplate.md as
an isolated commit to preserve blame history. The file content is not
yet valid Markdown; the rewrite follows in a stacked PR.
Cross-references in MarkdownQuickstartTemplate.md, README.txt, and
openmp/docs/README.txt are updated accordingly.
See RFC:
https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/90840
Commit: f31bc0a478a86e45b2e2745ed097509aca669f81
https://github.com/llvm/llvm-project/commit/f31bc0a478a86e45b2e2745ed097509aca669f81
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/docs/GitHub.rst
M llvm/docs/SphinxQuickstartTemplate.md
Log Message:
-----------
[docs] Rewrite SphinxQuickstartTemplate.md in MyST Markdown (#198896)
Converts SphinxQuickstartTemplate.md from reStructuredText syntax to
MyST Markdown. Updates the overview to mention that MyST is now
preferred for new LLVM documentation, modernizes the authoring
guidelines, and replaces all RST markup constructs with their Markdown
equivalents.
The renamd landed as PR #198899.
See RFC:
https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/90840
An LLM was used to assist with the rewrite.
---------
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
Commit: 3ca3bbcaf1dc8a8b4270cbd896d97e522b72f475
https://github.com/llvm/llvm-project/commit/3ca3bbcaf1dc8a8b4270cbd896d97e522b72f475
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
A llvm/test/CodeGen/Xtensa/landingpad.ll
Log Message:
-----------
[Xtensa] Implement lowering Exception Selector and Pointer Registers. (#198043)
This PR fixes issue https://github.com/llvm/llvm-project/issues/190308
Commit: 9b92e0fe9b0066d58073ee81afa0e5823a474e1e
https://github.com/llvm/llvm-project/commit/9b92e0fe9b0066d58073ee81afa0e5823a474e1e
Author: jofrn <jo7frn1 at gmail.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/X86/atomic-load-store.ll
Log Message:
-----------
[SelectionDAG] Split vector types for atomic store (#197860)
Vector types that aren't widened are split so that a single ATOMIC_STORE
is issued for the entire vector at once. This enables SelectionDAG to
translate vectors with type bfloat,half.
Store-side counterpart to #165818. Stacked on top of #197619; and below
of #197861.
Commit: 162076fe779ea8e1d9008b42e3c5f5ea3ae473dc
https://github.com/llvm/llvm-project/commit/162076fe779ea8e1d9008b42e3c5f5ea3ae473dc
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86PartialReduction.cpp
M llvm/test/CodeGen/X86/sad.ll
Log Message:
-----------
[X86] Check useBWIRegs() instead of hasBWI() before creating x86_avx512_psad_bw_512 intrinsic. (#201167)
Need to check that 512-bit vectors are enabled before using a 512-bit
intrinsic.
Commit: 40ad00beb3e275e1c50d6a718800d197a6b02c4e
https://github.com/llvm/llvm-project/commit/40ad00beb3e275e1c50d6a718800d197a6b02c4e
Author: mleair <leairmark at gmail.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M flang/lib/Lower/Bridge.cpp
A flang/test/Lower/intrinsic-module-array-constant.f90
Log Message:
-----------
[flang] Define array named constants from the iso_fortran_env intrins… (#201190)
…ic module
createIntrinsicModuleDefinitions() only emitted definitions for array
named constants belonging to the __fortran_ieee_exceptions intrinsic
module. Array constants declared directly in the iso_fortran_env
intrinsic module -- in practice character_kinds -- were therefore only
lowered as bodyless `fir.global` external declarations at their use site
and never defined anywhere, producing an undefined reference at link
time.
This is usually hidden because scalar iso_fortran_env parameters fold to
immediates and constant-shape array accesses are folded away, so the
dangling external symbol is DCE'd before linking. It surfaces when the
address of the array genuinely escapes to runtime, e.g.:
```
use iso_fortran_env
integer :: i, x(1)
do i = 1, size(character_kinds)
x = findloc(character_kinds, character_kinds(i))
end do
```
which fails with:
undefined reference to `_QMiso_fortran_envECcharacter_kinds'
Fix by also processing the iso_fortran_env scope in
createIntrinsicModuleDefinitions(), so its array constants are emitted
as linkonce_odr definitions with initializers.
Note that integer_kinds/real_kinds/logical_kinds are unaffected: they
are renamed from iso_fortran_env_impl, a non-intrinsic module that is
compiled into the runtime, so their definitions already exist there.
Assisted-by: AI
Commit: f2a780bbe2d8f66bcffb76e9d5f008d581be7917
https://github.com/llvm/llvm-project/commit/f2a780bbe2d8f66bcffb76e9d5f008d581be7917
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/test/Shell/SymbolFile/DWARF/delayed-definition-die-searching.test
Log Message:
-----------
[lldb][test] Make delayed-definition-die-searching CU-layout agnostic (#201206)
The second `ParseTypeFromDWARF` for t1 (after `p v2`) only fires when
t1's definition lives in a separate CU from its forward declaration:
LLDB parses the forward-decl DIE during `p v1` and a distinct definition
DIE during `p v2`. dsymutil's parallel linker collapses both into a
single DIE in the artificial type unit, so t1 is parsed once during `p
v1` and only re-resolved during `p v2`.
Drop the second-parse CHECK so the test no longer presumes a per-CU type
layout. The remaining `'t1' resolving forward declaration...` CHECK
after `p v2` still verifies what the test was designed to catch: t1's
complete-type resolution is deferred until v2 is evaluated. If LLDB
regressed to eager resolution during `p v1`, that log line would move
and the test would fail. Add a `(t1) (x = 0)` CHECK at the end to cover
the end-to-end value.
Commit: 87d6941017aa6022ce00baa9f1dfae5a49b113f4
https://github.com/llvm/llvm-project/commit/87d6941017aa6022ce00baa9f1dfae5a49b113f4
Author: Mircea Trofin <mtrofin at google.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
M clang/test/CodeGen/lto-newpm-pipeline.c
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
M lld/test/ELF/lto/devirt_vcall_vis_export_dynamic.ll
M lld/test/ELF/lto/devirt_vcall_vis_public.ll
M lld/test/ELF/lto/devirt_vcall_vis_shared_def.ll
M llvm/include/llvm/Analysis/CtxProfAnalysis.h
M llvm/include/llvm/Bitcode/BitcodeReader.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/IR/GlobalObject.h
M llvm/include/llvm/IR/GlobalValue.h
M llvm/include/llvm/IR/Module.h
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/include/llvm/LTO/LTO.h
R llvm/include/llvm/Transforms/Utils/AssignGUID.h
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/GlobalMerge.cpp
M llvm/lib/IR/Globals.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/lib/LTO/LTOBackend.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Transforms/IPO/ConstantMerge.cpp
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/Instrumentation/PGOCtxProfFlattening.cpp
M llvm/lib/Transforms/Instrumentation/PGOCtxProfLowering.cpp
M llvm/lib/Transforms/Scalar/JumpTableToSwitch.cpp
R llvm/lib/Transforms/Utils/AssignGUID.cpp
M llvm/lib/Transforms/Utils/CMakeLists.txt
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
M llvm/lib/Transforms/Utils/CloneModule.cpp
M llvm/lib/Transforms/Utils/FunctionImportUtils.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/test/Assembler/index-value-order.ll
M llvm/test/Bitcode/thinlto-alias.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph-partial-sample-profile-summary.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph-pgo.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph-profile-summary.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph-sample-profile-summary.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph.ll
M llvm/test/Bitcode/thinlto-function-summary-refgraph.ll
M llvm/test/Bitcode/thinlto-function-summary.ll
M llvm/test/CodeGen/X86/fat-lto-section.ll
M llvm/test/LTO/Resolution/X86/not-prevailing-alias.ll
M llvm/test/LTO/Resolution/X86/not-prevailing-weak-aliasee.ll
M llvm/test/Linker/funcimport2.ll
M llvm/test/Other/new-pm-O0-defaults.ll
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
M llvm/test/ThinLTO/AArch64/aarch64_inline.ll
M llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions1.ll
M llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions2.ll
M llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions3.ll
M llvm/test/ThinLTO/X86/ctor-dtor-alias.ll
M llvm/test/ThinLTO/X86/ctor-dtor-alias2.ll
M llvm/test/ThinLTO/X86/deadstrip.ll
M llvm/test/ThinLTO/X86/devirt_function_alias.ll
M llvm/test/ThinLTO/X86/devirt_function_alias2.ll
M llvm/test/ThinLTO/X86/devirt_pure_virtual_base.ll
M llvm/test/ThinLTO/X86/devirt_vcall_vis_public.ll
M llvm/test/ThinLTO/X86/distributed_import.ll
M llvm/test/ThinLTO/X86/funcattrs-prop-exported-internal.ll
M llvm/test/ThinLTO/X86/funcattrs-prop-unknown.ll
M llvm/test/ThinLTO/X86/funcattrs-prop-weak.ll
M llvm/test/ThinLTO/X86/globals-import.ll
M llvm/test/ThinLTO/X86/hidden-escaped-symbols-alt.ll
M llvm/test/ThinLTO/X86/hidden-escaped-symbols.ll
M llvm/test/ThinLTO/X86/import-ro-constant.ll
M llvm/test/ThinLTO/X86/index-const-prop-alias.ll
M llvm/test/ThinLTO/X86/index-const-prop.ll
M llvm/test/ThinLTO/X86/linkonce_resolution_comdat.ll
M llvm/test/ThinLTO/X86/memprof-dups.ll
M llvm/test/ThinLTO/X86/memprof_callee_type_mismatch.ll
M llvm/test/ThinLTO/X86/memprof_imported_internal.ll
M llvm/test/ThinLTO/X86/memprof_imported_internal2.ll
M llvm/test/ThinLTO/X86/prevailing_weak_globals_import.ll
M llvm/test/ThinLTO/X86/visibility-elf.ll
M llvm/test/ThinLTO/X86/visibility-macho.ll
M llvm/test/ThinLTO/X86/weak_resolution.ll
M llvm/test/ThinLTO/X86/windows-vftable.ll
M llvm/test/ThinLTO/X86/writeonly.ll
R llvm/test/Transforms/AssignGUID/assign_guid.ll
M llvm/test/Transforms/ConstantMerge/merge-dbg.ll
M llvm/test/Transforms/EmbedBitcode/embed-wpd.ll
M llvm/test/Transforms/EmbedBitcode/embed.ll
M llvm/test/Transforms/FunctionImport/funcimport-debug-retained-nodes.ll
M llvm/test/Transforms/FunctionImport/funcimport.ll
R llvm/test/Transforms/GlobalMerge/guid.ll
M llvm/test/Transforms/LowerTypeTests/cfi-icall-alias.ll
M llvm/test/Transforms/PGOProfile/thinlto_indirect_call_promotion.ll
M llvm/test/Transforms/PhaseOrdering/speculative-devirt-then-inliner.ll
M llvm/test/Transforms/SampleProfile/ctxsplit.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal-typeid.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal1.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal2.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc-internal.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/unsplittable.ll
M llvm/test/Transforms/WholeProgramDevirt/branch-funnel-profile.ll
M llvm/test/Transforms/WholeProgramDevirt/export-single-impl.ll
M llvm/test/Transforms/WholeProgramDevirt/export-vcp.ll
M llvm/test/tools/gold/X86/devirt_vcall_vis_export_dynamic.ll
M llvm/test/tools/gold/X86/devirt_vcall_vis_public.ll
M llvm/test/tools/gold/X86/devirt_vcall_vis_shared_def.ll
M llvm/test/tools/gold/X86/thinlto_weak_library.ll
M llvm/test/tools/gold/X86/thinlto_weak_resolution.ll
M llvm/test/tools/gold/X86/v1.16/devirt_vcall_vis_export_dynamic.ll
M llvm/tools/llvm-link/llvm-link.cpp
M llvm/tools/opt/NewPMDriver.cpp
M llvm/tools/opt/optdriver.cpp
Log Message:
-----------
Reverting PR #184065 and #200323 to address some interplay with CFI (#201194)
There is a relation between CFI and ThinLTO GUIDs that still needs to be
disentangled first. Note that we leave the `MD_unique_id` in
`FixedMetadataKinds.def` to avoid needing to re-number it later. Plus
the metadata string ("guid") itself is used by ctxprof.
Commit: 70edfe91f4fc6bd0b2137d20f3508a6fcd85bcde
https://github.com/llvm/llvm-project/commit/70edfe91f4fc6bd0b2137d20f3508a6fcd85bcde
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang-tools-extra/clang-tidy/misc/CMakeLists.txt
M clang-tools-extra/clang-tidy/misc/ConfusableTable/CMakeLists.txt
M llvm/cmake/modules/AddLLVM.cmake
Log Message:
-----------
[cmake] Fix host tool path with driver build on Windows (#199152)
On Windows, the llvm-shlib dylib build uses the llvm-nm host tool to
make all symbols visible by default. The LLVM_TOOL_LLVM_DRIVER_BUILD=ON
build would fail because $<TARGET_FILE:llvm-nm> was invalid. This change
passes the name of the symlink / executable copy as a custom property so
things work out and the llvm-nm.exe host tool can be found.
Commit: b29bf9fa25bdb906a61ec361fba68796020cc6b9
https://github.com/llvm/llvm-project/commit/b29bf9fa25bdb906a61ec361fba68796020cc6b9
Author: Peter Hawkins <phawkins at google.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M mlir/include/mlir/Bytecode/BytecodeWriter.h
M mlir/lib/Bytecode/Writer/BytecodeWriter.cpp
M mlir/lib/Bytecode/Writer/IRNumbering.cpp
M mlir/lib/Bytecode/Writer/IRNumbering.h
M mlir/unittests/Bytecode/BytecodeTest.cpp
Log Message:
-----------
[mlir][bytecode] Add option to elide locations during serialization (#201183)
Adds a setElideLocations option to BytecodeWriterConfig to elide
locations during bytecode serialization. When enabled, all LocationAttrs
are mapped to UnknownLoc during numbering and writing to produce
location-invariant bytecode (e.g., for stable fingerprinting).
Another way to achieve the same thing would be to apply the
strip-debuginfo pass,
but that requires mutating the module, which in turn requires cloning
the module if one still requires the unstripped original.
Assisted-by: Antigravity / Gemini
Commit: f2dd83075571265427547b94e06aabda61aff974
https://github.com/llvm/llvm-project/commit/f2dd83075571265427547b94e06aabda61aff974
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td
Log Message:
-----------
[RISCV][GISel] Add GPRPair to GPRB register bank and use getXLen() for GPRSize
Map GPRPair register classes to the GPRB register bank during GlobalISel
instruction selection. This is required because the introduction of HwMode-dependent
base pointer register classes (e.g. via PtrRegClassByHwMode) causes TableGen to
emit register bank checks for GPRPair variants in RISCVGenGlobalISel.inc.
Without this mapping, instruction selection crashes on unsupported classes.
To avoid assertion failures when GPRB's maximum size increases to 128-bit on RV64
due to the register pairs, update RISCVRegisterBankInfo::getInstrMapping to query
Subtarget.getXLen() for the scalar register width instead of relying on the bank's
getMaximumSize(). This matches AArch64's design pattern of mapping register pairs
(XSeqPairsClass) to GPR and resolving scalar register sizes dynamically.
This was fine previously but was exposed by the HwMode changes in
https://github.com/llvm/llvm-project/pull/177073.
Pull Request: https://github.com/llvm/llvm-project/pull/200510
Commit: 155c6e4f887a9b4fb8900ec655124303e7308b4b
https://github.com/llvm/llvm-project/commit/155c6e4f887a9b4fb8900ec655124303e7308b4b
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/cmake/caches/Apple-lldb-macOS.cmake
Log Message:
-----------
[lldb] Add lldb-mcp to LLVM_DISTRIBUTION_COMPONENTS (#201225)
Add lldb-mcp to LLVM_DISTRIBUTION_COMPONENTS
Commit: 08e8df51ce23b79e50774453e7ae120c1b5de2ef
https://github.com/llvm/llvm-project/commit/08e8df51ce23b79e50774453e7ae120c1b5de2ef
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
M llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/SimpleExecutorDylibManager.h
M llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleExecutorDylibManager.cpp
Log Message:
-----------
[ORC] Make SimpleExecutorDylibManager::resolve an instance method. (#201211)
Promote the lambda inside resolveWrapper to a public method on
SimpleExecutorDylibManager. This brings SimpleExecutorDylibManager into
better alignment with the NativeDylibManager implementation in the new
ORC runtime, and is a step towards allowing NativeDylibManager to be
used as a drop-in replacement for SimpleExecutorDylibManager.
Commit: 72a05d59bc8cba3728ad1e3f60bdcc8504f7a708
https://github.com/llvm/llvm-project/commit/72a05d59bc8cba3728ad1e3f60bdcc8504f7a708
Author: Jason Molenda <jmolenda at apple.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/test/API/python_api/run_locker/TestRunLocker.py
Log Message:
-----------
[lldb] Have TestRunLocker run both styles of launch (#200978)
While debugging flakey behavior with TestRunLocker, I noticed that is
intended to run its test once with a stop at the entry function (and
then Continues) and once where we launch to the main() loop. But we were
never exercising the stop-at-entry codepath.
This doesn't fix the flakey behavior, although that only happens with
the launch-directly-into-main() codepath; I don't get failures when I
stop at the entry point and then continue.
Commit: 04d9e8687b3836af1eede7df15ecc43ac5c1f67d
https://github.com/llvm/llvm-project/commit/04d9e8687b3836af1eede7df15ecc43ac5c1f67d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Don't expand SCEVs without uses to VPInstructions (NFC). (#201221)
If a VPExpandSCEVRecipe does not have users, there's no benefit to
expand it to VPInstructions, which then have to get cleaned up.
This also prevents DCE from removing VPInstructions pointed to by
TripCount after expansion.
Commit: 2a936ce9316042cd7e45e72b528ad1d55aa2fe3c
https://github.com/llvm/llvm-project/commit/2a936ce9316042cd7e45e72b528ad1d55aa2fe3c
Author: Jason Molenda <jmolenda at apple.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/tools/debugserver/source/DNB.cpp
Log Message:
-----------
[lldb][debugserver] Arguments to kill(2) are reversed (#201226)
This codepath is only executed as an attempt to clean up during a failed
launch, so the reversed arguments were rarely actually used.
rdar://175507620
Commit: ce465594e2394ebe6894c6f0dfc9d0817b63c9da
https://github.com/llvm/llvm-project/commit/ce465594e2394ebe6894c6f0dfc9d0817b63c9da
Author: Justin Lebar <justin.lebar at gmail.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp
M llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll
Log Message:
-----------
[NVPTX] Fix aggregate load/store lowering for (potentially) overlapping copies (#201177)
NVPTXLowerAggrCopies lowers load/store pairs of large values into a loop
of smaller copies.
However, it was incorrectly assuming that the load/store pairs it found
never alias.
This patch adds an alias check. If the pointers may alias, we emit a
memmov, which handles overlap correctly.
CUDA reproducer:
typedef char vec __attribute__((vector_size(256)));
__global__ void boom(char *p) {
*(vec *)(p + 8) = *(vec *)p;
}
Commit: 26e44e62fdaf0467e153d2f83251e2d48eb1f10e
https://github.com/llvm/llvm-project/commit/26e44e62fdaf0467e153d2f83251e2d48eb1f10e
Author: adams381 <adams at nvidia.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
A clang/test/CIR/CodeGen/func-linkage-weak-import.c
A clang/test/CIR/CodeGen/inline-forward-decl.c
Log Message:
-----------
[CIR] Set ExternalWeakLinkage on weak/weak_import function declarations (#198422)
Classic CodeGen's `SetFunctionAttributes` calls `setLinkageForGV` to force `ExternalWeakLinkage` on `__attribute__((weak))` and Darwin `weak_import` declarations. CIR had no equivalent: weak function declarations were emitted with `ExternalLinkage` instead of `ExternalWeakLinkage`.
This adds `setLinkageForFunction` — the same weak/external-weak logic as `setLinkageForGV` — and calls it from `setFunctionAttributes`. The underlying crash on inline forward declarations (the original motivation) is already fixed by #195257; what remains is this linkage gap.
`inline-forward-decl.c` covers `__attribute__((weak))` on an inline forward declaration; `func-linkage-weak-import.c` covers Darwin `weak_import` (→ `extern_weak` in CIR and LLVM).
Commit: d59899763f0df2bf16fca98ab11421646957602a
https://github.com/llvm/llvm-project/commit/d59899763f0df2bf16fca98ab11421646957602a
Author: Yury Plyakhin <yury.plyakhin at intel.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper-image.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
Log Message:
-----------
[clang-linker-wrapper] Drop SYCL dry-run stub-image special case (#201222)
Remove the `DryRun` branch in `bundleSYCL` that emitted a stub
`OffloadBinary`. SYCL goes through the same empty-buffer path as other
offload kinds, so the special case is no longer needed.
Update `linker-wrapper-image.c` to expect the resulting `[0 x i8]
zeroinitializer` constant and a size of `0` in the register/unregister
calls.
Assisted by Claude.
Commit: 142ad481b6254104a51da7d636ad9e3f30518a32
https://github.com/llvm/llvm-project/commit/142ad481b6254104a51da7d636ad9e3f30518a32
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/CMakeLists.txt
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/include/lldb/Host/Config.h.cmake
A lldb/include/lldb/Host/ScriptInterpreterRuntimeLoader.h
M lldb/include/module.modulemap
M lldb/source/Host/CMakeLists.txt
A lldb/source/Host/common/PythonRuntimeLoader.cpp
A lldb/source/Host/common/PythonRuntimeLoaderInternal.h
A lldb/source/Host/common/ScriptInterpreterRuntimeLoader.cpp
A lldb/source/Host/linux/PythonRuntimeLoaderLinux.cpp
A lldb/source/Host/macosx/PythonRuntimeLoaderDarwin.cpp
A lldb/source/Host/windows/PythonRuntimeLoaderWindows.cpp
M lldb/unittests/Host/CMakeLists.txt
A lldb/unittests/Host/PythonRuntimeLoaderTest.cpp
Log Message:
-----------
[lldb] Add PythonRuntimeLoader for runtime libpython lookup (NFC) (#200524)
Generalizes the Windows-only Python lookup in PythonPathSetup into a
cross-platform abstraction. Adds an abstract ScriptInterpreterRuntimeLoader
with a per-language factory. The Python implementation dynamically loads Python
library into the current process.
The loader no-ops when Python is already in the process, then walks
LLDB_PYTHON_LIBRARY env override, the build-time Python
(LLDB_PYTHON_RUNTIME_LIBRARY_BUILD_PATH) and finally a platform candidate list:
- Darwin: DEVELOPER_DIR, the bundled Xcode.app, and Command Line Tools joined
against Python3.framework. Then python.org, /opt/homebrew, and /usr/local
joined against Python.framework. Then xcrun -f python3 and if that fails,
libpython3.dylib as a last resort.
- Linux: libpython3.so plus descending stable-ABI SONAMEs.
- Windows: the LLDB_PYTHON_RUNTIME_LIBRARY_FILENAME bare name (resolved via the
loader's default search list) and the exe-relative
LLDB_PYTHON_DLL_RELATIVE_PATH fallback (built off GetModuleFileNameW).
Pre-mapping python3xx.dll lets the script interpreter plugin's delay-load
thunks resolve against the already-loaded module by base name on first use.
This commit only introduces the abstraction. No existing call site is changed,
and the script interpreter plugin still hard-links Python, which are part of
two follow-up PRs.
Commit: 3eb13f8db39ed42827122489c830c414cb6660e3
https://github.com/llvm/llvm-project/commit/3eb13f8db39ed42827122489c830c414cb6660e3
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M lldb/source/API/SystemInitializerFull.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/CMakeLists.txt
M lldb/test/CMakeLists.txt
Log Message:
-----------
[lldb] Stop hard-linking libpython into the dynamic Python plugin (#200530)
Drops ${Python3_LIBRARIES} from the SHARED build of
lldbPluginScriptInterpreterPython and lets undefined Python symbols
through at link time (`-undefined dynamic_lookup` on Darwin,
`--allow-shlib-undefined` on Linux; Windows keeps its existing
delay-load + import lib).
SystemInitializerFull::Initialize resolves the Python runtime loader
via ScriptInterpreterRuntimeLoader::Get(eScriptLanguagePython) and
calls Load() before initializing any plugin, so libpython is mapped
into the process before either entry point that references it: the
static script interpreter's Initialize() (which invokes Python via
the LLDB_PLUGIN_INITIALIZE loop) and the dynamic plugin's dlopen
(whose undefined references resolve against the in-process
libpython). This covers both LLDB_ENABLE_DYNAMIC_SCRIPTINTERPRETERS
=ON and =OFF, and keeps Windows working in static builds where the
delay-load thunks live in liblldb itself. The loader is
once_flag-cached, and errors propagate out via the existing Expected
return.
`import lldb` from a running Python works because libpython is
already mapped into the process. The Python runtime loader probes
for stable-ABI symbols (Py_IsInitialized, Py_InitializeFromConfig)
via dlsym(RTLD_DEFAULT) / GetProcAddress and, finding them, returns
success without dlopen'ing a second libpython on top.
The dynamic plugins are added as test-suite dependencies so
check-lldb-shell and check-lldb-api wait for them; they can't be
build-order deps of liblldb itself because the plugins link against
liblldb (CMake SHARED cycle).
The unit-test static variant lldbStaticScriptInterpreterPython keeps
hard-linking libpython so link-time symbol checking is preserved.
Commit: 678891b586ab0f3b97c83987eb2df0d2d5743ffb
https://github.com/llvm/llvm-project/commit/678891b586ab0f3b97c83987eb2df0d2d5743ffb
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenConstantEmitter.h
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
A clang/test/CIR/CodeGen/compound_literal.c
Log Message:
-----------
[CIR] Implement lowering for const-emitted global compound literals (#201152)
This came up in a test suite as a NYI, it is just emitting a
constant-backing literal for an initializer. These are specific to C, as
global compound literals have static storage duration in C. This patch,
just like classic codgen, just creates a '.compoundliteral' object as
backing for these variables, and lets us create references to them.
---------
Co-authored-by: Andy Kaylor <akaylor at nvidia.com>
Commit: 243ddf607bbe4841cfe734507120c8d8ddc41eca
https://github.com/llvm/llvm-project/commit/243ddf607bbe4841cfe734507120c8d8ddc41eca
Author: Schrodinger ZHU Yifan <yfzhu at google.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M libc/src/__support/block.h
M libc/src/__support/freelist_heap.h
M libc/src/__support/freestore.h
M libc/test/src/__support/CMakeLists.txt
M libc/test/src/__support/block_test.cpp
M libc/test/src/__support/freelist_heap_test.cpp
Log Message:
-----------
[libc] add shrink in-place support for reallocations (#200272)
This PR adds shrinking in-place for the freelist heap. This allows the
heap to reuse the place if the reallocation shrinks the size larger than
a minimal block unit.
Synthesized random action tests show that that increase heap utilization
rate from 87% to 97% percent, basically aligns with the expectation of
dlmalloc.
Assisted-by: AI tools, manually checked.
Commit: a6745c933a3828f4e2cac4d94754688fe3b03f9f
https://github.com/llvm/llvm-project/commit/a6745c933a3828f4e2cac4d94754688fe3b03f9f
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/InlineSpiller.cpp
A llvm/test/CodeGen/X86/apx/memfold-origVNI-crash.ll
Log Message:
-----------
[X86][APX] Extend original LI to the same range as DstReg (#199182)
The #189222 folds NDD+Load to non-NDD when NDD memory variant not
preferred. However, this will changes DstReg from regular def to
early-clobber def, which causes "corrupted sub-interval" in
reMaterializeFor, because the OrigLI is not updated at the same time.
Fixes: https://godbolt.org/z/7n8ozz1EG
Assisted-by: Claude Sonnet 4.6
Commit: 0e40e9e341cf78662ab468fb8cdd6cac7e58ad1f
https://github.com/llvm/llvm-project/commit/0e40e9e341cf78662ab468fb8cdd6cac7e58ad1f
Author: Yury Plyakhin <yury.plyakhin at intel.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/test/OffloadTools/clang-sycl-linker/basic.ll
M clang/test/OffloadTools/clang-sycl-linker/split-mode.ll
M clang/test/OffloadTools/clang-sycl-linker/triple.ll
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
Log Message:
-----------
[clang-sycl-linker][test] Improve dry-run mode and tighten test coverage (#200513)
- Rework `--dry-run` in `clang-sycl-linker` so it skips all real output
(writing bitcode, executing tools, etc.).
- The `link:`, `sycl-module-split:`, and a new `sycl-bundle:` summary
line are now gated on `-v` alone.
- Tighten `sycl-bundle:` checks in `basic.ll`, `split-mode.ll`, and
`triple.ll` to pin kind, triple, and arch (instead of just kind),
and add `-NOT: {{.+}}` after fully-covered dry-run check groups.
- replace the `clang-sycl-linker` + `llvm-objdump --offloading`
round-trip with a single `--dry-run -v` invocation.
- add dedicated `non-dry-run` mode test to verify code paths not exposed
in `dry-run`.
Assisted by Claude.
Commit: f132e926290fe1cc69946addfb90d61b56c9402a
https://github.com/llvm/llvm-project/commit/f132e926290fe1cc69946addfb90d61b56c9402a
Author: adams381 <adams at nvidia.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.h
A clang/test/CIR/Transforms/abi-lowering/coerce-int-to-record.cir
A clang/test/CIR/Transforms/abi-lowering/coerce-record-return-larger.cir
A clang/test/CIR/Transforms/abi-lowering/coerce-record-to-int.cir
A clang/test/CIR/Transforms/abi-lowering/coerce-record-to-record-via-memory.cir
A clang/test/CIR/Transforms/abi-lowering/coerce-vector-to-complex.cir
Log Message:
-----------
[CIR] Coerce Direct args and returns in CallConvLowering (#195879)
Fourth PR in the split of #192119/#192124. Implements the
Direct-with-coercion path in CallConvLowering.
Every Direct argument or return whose ABI type differs from its source
type is now coerced through a store/reload roundtrip via an entry-block
alloca, mirroring classic codegen's CreateCoercedLoad/CreateCoercedStore.
The temporary alloca uses max(srcAlign, dstAlign) from the DataLayout and
is hoisted into the entry block so it composes with HoistAllocas
regardless of pipeline order. When the coerced type is larger than the
source -- e.g. a 12-byte aggregate returned as { i64, i64 } -- the slot is
sized to the larger type and accessed through a source-typed view for the
store and a destination-typed view for the load, so neither side
over-reads.
CallConvLowering is split into three phases (function-definition
coercion, call-site rewriting, and Ignore cleanup) because in-place
block-argument type changes from Direct-with-coerce otherwise confused the
earlier ordering, synthesizing alloca/load chains for call-site uses of
Ignore'd arguments that were about to be dropped.
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: 45bddca21c65106b41fa47a485a30c863e75da53
https://github.com/llvm/llvm-project/commit/45bddca21c65106b41fa47a485a30c863e75da53
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCleanup.cpp
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
A clang/test/CIR/CodeGen/switch-cleanup.cpp
Log Message:
-----------
[CIR] Fix insertion point tracking for switch with cleanups (#201210)
We had some problems where we would incorrectly maintain the insertion
point for switch statements that contained cleanup scopes. This resulted
in cir.scope statements without a terminator, tripping a verification
error.
This change adds a RunCleanupsScope RAII object for the switch statement
and adds a check inside popCleanup() to avoid moving the insertion point
to the point after the now-closed cleanup scope if the insertion point
had previously been somewhere other than inside the cleanup scope.
Assisted-by: Cursor / claude-opus-4.8
Commit: 19c7fdb3c3c68a9d6861627c85cd0251b7854f6f
https://github.com/llvm/llvm-project/commit/19c7fdb3c3c68a9d6861627c85cd0251b7854f6f
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
A clang/test/CIR/CodeGen/global-temp-dtor.cpp
M clang/test/CIR/CodeGen/self-ref-temporaries.cpp
M clang/test/CIR/CodeGenCXX/global-refs.cpp
Log Message:
-----------
[CIR] Implement destruction of TLS and static global references (#200227)
This implements destruction of lifetime-extended reference temporaries
used to initialize TLS or static duration reference variables.
Assisted-by: Cursor / claude-opus-4.7
Commit: f48e6b81c3acb7007aa94ac768c95122796df08c
https://github.com/llvm/llvm-project/commit/f48e6b81c3acb7007aa94ac768c95122796df08c
Author: Justin Lebar <justin.lebar at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVVMIntrRange.cpp
M llvm/test/CodeGen/NVPTX/intr-range.ll
Log Message:
-----------
[NVPTX] NVVMIntrRange: Handle maxntid > UINT32_MAX. (#201245)
Previously we computed the overall maxntid and downcast it to unsigned
int. This is not correct; it can be larger than UINT32_MAX.
This would cause reads of tid.xyz and ntid.xyz to have incorrect range
information. Also if maxntid was an exact multiple of 2^32, we'd get an
ICE (because we'd incorrectly think that maxntid is 0).
Commit: 8763a68723b0dbd1ef2e7cc0ac61b2635ceef000
https://github.com/llvm/llvm-project/commit/8763a68723b0dbd1ef2e7cc0ac61b2635ceef000
Author: Jessica Clarke <jrtc27 at jrtc27.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/M68k/AsmParser/CMakeLists.txt
Log Message:
-----------
[M68k] Add to LINK_COMPONENTS to fix BUILD_SHARED_LIBS build (#201248)
Fixes: 6897c5e24ce5 ("[M68k][MC] Add MC support for PCI w/ base
displacement addressing mode (#200696)")
Commit: 53938ba7f3631583f79f1b7c1cf8a5d2347ba4d1
https://github.com/llvm/llvm-project/commit/53938ba7f3631583f79f1b7c1cf8a5d2347ba4d1
Author: Boyao Wang <wangboyao at bytedance.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
R llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/pr148084.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
M llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
R llvm/test/MC/RISCV/xrivosvizip-invalid.s
R llvm/test/MC/RISCV/xrivosvizip-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Remove experimental XRivosVizip support (#200761)
Remove experimental XRivosVizip support which will not be maintained by
RVIOS any more.
Commit: 83318d027abdbd4694d6a070194c82f1e2a34739
https://github.com/llvm/llvm-project/commit/83318d027abdbd4694d6a070194c82f1e2a34739
Author: Fan Mo <w007878 at hotmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl04.rst
Log Message:
-----------
[docs][Kaleidoscope] fix function name InitializeModuleAndManagers in Kaleidoscope (#199601)
### Description
resloves #199477
The Kaleidoscope tutorial was not fully updated with the new Pass
Manager. This pr aligns the tutorial doc with the example code.
### Changes
- Use `InitializeModuleAndManagers` instead of
`InitializeModuleAndPassManager`.
- Remove `TheModule->setDataLayout(TheJIT->getDataLayout());` in line
141, as the `setDataLayout` was introduced later.
- Use `KaleidoscopeJIT` instead of `my cool jit` as the ModuleName, to
align with the final code.
Commit: 45c4ebb92ae393a541105c120e0dba2992237c03
https://github.com/llvm/llvm-project/commit/45c4ebb92ae393a541105c120e0dba2992237c03
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M lldb/docs/conf.py
Log Message:
-----------
[lldb] Enable MyST colon_fence and deflist extensions (NFC) (#201250)
Enable the colon_fence and deflist MyST parser extensions in the LLDB
docs configuration. This is a preparatory step for converting the
remaining reStructuredText documentation pages to Markdown, where these
two extensions are needed to translate RST admonition directives
(:::{note}) and definition lists.
Context:
https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/
Commit: ee20b106ec70d3494890a707a32ac677c64c409d
https://github.com/llvm/llvm-project/commit/ee20b106ec70d3494890a707a32ac677c64c409d
Author: Thrrreeee <shijinrui at bytedance.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M bolt/include/bolt/Core/BinaryContext.h
M bolt/include/bolt/Core/DIEBuilder.h
M bolt/lib/Core/DIEBuilder.cpp
M bolt/lib/Rewrite/DWARFRewriter.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/X86/dwarf5-df-types-dup-dwp-input.test
A bolt/test/X86/dwarf5-dwp-tsan-data-race.test
Log Message:
-----------
[BOLT] Fix data race in multi-threaded DWP type unit processing and DWP type unit duplication (#197359)
## Summary
This PR fixes a race condition in LLVM BOLT's
DIEBuilder::buildTypeUnits() that is triggered when DWARF5 split-DWARF
(.dwo/.dwp) inputs are processed with multi-threaded CU processing.
Concurrent invocations from different worker threads share the same DWP
type-unit state, which results in duplicated DIE extraction, assertion
failures, and intermittent crashes. The fix serializes buildTypeUnits()
for DWP inputs via a function-local static std::mutex, leaving the
non-DWO fast path unchanged.
## Problem Description
When BOLT processes DWARF debug info with --debug-thread-count=4
--cu-processing-batch-size=4 on testcase
dwarf5-df-types-dup-dwp-input.test, multiple threads concurrently call
DIEBuilder::buildTypeUnits() on shared DWP type units. Since type units
within a DWP file are shared across compilation units, multiple threads
may attempt to extract DIEs from the same type unit simultaneously,
violating the assertion.
**Note:** This is an intermittent failure — due to its dependence on
thread scheduling and interleaving, it does not reproduce on every run,
and may require multiple executions under the multi-threaded
configuration to surface, which is why it escaped earlier
single-threaded testing.
Commit: 6d7962db9397eefe3a287115d413fd4c562e4178
https://github.com/llvm/llvm-project/commit/6d7962db9397eefe3a287115d413fd4c562e4178
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaOverload.cpp
M clang/test/SemaCUDA/addr-of-overloaded-fn.cu
A clang/test/SemaCUDA/addr-of-overloaded-template-fn.cu
Log Message:
-----------
[clang][CUDA] Avoid ambiguity in host/device template specializations (#201049)
This commit changes SemaOverload to resolve an otherwise diagnosed
ambiguity between addresses of template specializations of functions
that are overloaded for both device and host. Similar to how it works
for non-templated function overloads, these changes prioritizes the
specializations that corresponds to the target of the owning function,
i.e. if compiling for host, the address of the host specialization takes
precedence over the device specialization and vice versa.
Fixes https://github.com/llvm/llvm-project/issues/199299
---------
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
Commit: a47bddccec30255619bb8c37fa59700e661d4e66
https://github.com/llvm/llvm-project/commit/a47bddccec30255619bb8c37fa59700e661d4e66
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang-tools-extra/clangd/InlayHints.cpp
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
Log Message:
-----------
[clangd] Handle dependent call to function with explicit object parameter in InlayHintVisitor (#201264)
Dependent calls do not yet have the implicit object argument preprended
to the CallExpr's argument list, so the first argument should not be
expected to be present and dropped in this case.
Fixes https://github.com/llvm/llvm-project/issues/198588
Commit: 70bca0f9af520569daa85959c56d95b2d1cd0389
https://github.com/llvm/llvm-project/commit/70bca0f9af520569daa85959c56d95b2d1cd0389
Author: Piyou Chen <piyou.chen at sifive.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
A llvm/test/CodeGen/RISCV/rvv/xsfmm-insert-vsetvl-TMTK.mir
Log Message:
-----------
[RISCV] Make VSETTM/VSETTK not affect the VSETVL emit (#197890)
VSETTM/TK will modify VTYPE, but it only affects the TM/TK bits. This
modification is safe for other RVV operations. The TM/TK value will be
maintained in insertVSETMTK.
Commit: 866c39b61f475ca4dffd9eae280d146f59cdede6
https://github.com/llvm/llvm-project/commit/866c39b61f475ca4dffd9eae280d146f59cdede6
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAGCombiner] Remove no longer tested VP_MUL handling. (#201238)
We no longer use VP_MUL in SelectionDAG on RISC-V so this code isn't
tested.
This effectively reverts db6de1a20f75cbfe1024f41e64ad39def91fa70f
Commit: e0b580a724dc58afa119eb2ce25620ebd8d5f275
https://github.com/llvm/llvm-project/commit/e0b580a724dc58afa119eb2ce25620ebd8d5f275
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAGCombiner] Remove untested visitVP_FADD and visitVP_FSUB. (#201247)
RISC-V no longer uses VP_FADD/FSUB in SelectionDAG.
Commit: f91f589aaa82514952f7a13b3e3bd2910d32559a
https://github.com/llvm/llvm-project/commit/f91f589aaa82514952f7a13b3e3bd2910d32559a
Author: JoshuaGrindstaff <99843934+JoshuaGrindstaff at users.noreply.github.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
M llvm/test/MC/AMDGPU/mcexpr_amd.s
M llvm/test/MC/AMDGPU/mcexpr_amd_err.s
A llvm/unittests/Target/AMDGPU/AMDGPUMCExprTest.cpp
M llvm/unittests/Target/AMDGPU/CMakeLists.txt
Log Message:
-----------
[AMDGPU] Added min operation for MCExprs (#199746)
The min operation is needed in MC Expressions for a future change that
caps the max number of registers used for indirect calls.
---------
Co-authored-by: JoshuaGrindstaff <jgrindst at amd.com>
Commit: c7b4b4a33350e3805deae64f17d6185b184d7887
https://github.com/llvm/llvm-project/commit/c7b4b4a33350e3805deae64f17d6185b184d7887
Author: Justin Lebar <justin.lebar at gmail.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll
Log Message:
-----------
[NVPTX] Fix the build after ce465594e239. (#201268)
ce465594e239 (#201177) added sm_90 / PTX ISA 7.8 instructions to
lower-aggr-copies.ll, so we need to guard the RUN line appropriately.
Commit: baa8da34e6745536288edb042e89871d89376469
https://github.com/llvm/llvm-project/commit/baa8da34e6745536288edb042e89871d89376469
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
A mlir/test/Dialect/SPIRV/IR/tosa-ops-dynamic.mlir
Log Message:
-----------
[mlir][spirv] Allow dynamic rescale parameter lengths (#200155)
The SPIR-V TOSA rescale verifier checked multiplier and shift lengths
with a direct equality against the input channel dimension. That rejects
otherwise valid operations when either side of the shape comparison is
dynamic.
Express the check with reusable dimension predicates so unranked or
dynamic dimensions pass, while static dimensions still enforce the
per-channel and scalar length requirements. Add dedicated dynamic-shape
op coverage for dynamic input channel dimensions and dynamic
multiplier/shift lengths.
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: 4a74b4472833d57e0ecfaaa5d06a2c607bcceeae
https://github.com/llvm/llvm-project/commit/4a74b4472833d57e0ecfaaa5d06a2c607bcceeae
Author: Lang Hames <lhames at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M orc-rt/include/orc-rt/NativeDylibManager.h
M orc-rt/lib/executor/NativeDylibManager.cpp
M orc-rt/lib/executor/sps-ci/NativeDylibManagerSPSCI.cpp
M orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
M orc-rt/unittests/NativeDylibManagerTest.cpp
Log Message:
-----------
[orc-rt] Add required/weak-ref attribute to NativeDylibManager lookup. (#201272)
Replace the std::vector<std::string> argument to lookup() with a
SymbolLookupSet (a vector of (name, LookupFlags) pairs, where
LookupFlags is RequiredSymbol or WeaklyReferencedSymbol).
This brings NativeDylibManager more closely into alignment with the
SimpleExecutorDylibManager implementation in the LLVM OrcTargetProcess
library.
Commit: c264e07c2f3d9f25a2526e69926daea3a68be74b
https://github.com/llvm/llvm-project/commit/c264e07c2f3d9f25a2526e69926daea3a68be74b
Author: Konstantin Belochapka <konstantin.belochapka at sony.com>
Date: 2026-06-02 (Tue, 02 Jun 2026)
Changed paths:
M cross-project-tests/dtlto/dtlto-cache.test
M cross-project-tests/dtlto/savetemps-lock.test
M lld/COFF/LTO.cpp
M lld/ELF/LTO.cpp
M lld/test/ELF/dtlto/timetrace.test
M llvm/include/llvm/DTLTO/DTLTO.h
M llvm/include/llvm/LTO/Config.h
M llvm/include/llvm/LTO/LTO.h
M llvm/lib/DTLTO/CMakeLists.txt
M llvm/lib/DTLTO/DTLTO.cpp
A llvm/lib/DTLTO/DTLTODistributionDriver.cpp
A llvm/lib/DTLTO/DTLTOInputFiles.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/test/ThinLTO/X86/dtlto/timetrace.ll
M llvm/tools/llvm-lto2/CMakeLists.txt
M llvm/tools/llvm-lto2/llvm-lto2.cpp
Log Message:
-----------
[DTLTO] Refactor the DTLTO code. (#192629)
DTLTO implementation code has been moved from `llvm/lib/LTO/` to
`llvm/lib/DTLTO/`. This refactor does not change any externally visible
behavior, so existing DTLTO tests and documentation remain valid. The
move was done to reduce code duplication, improve maintainability, and
make it easier to adopt future performance improvements.
Commit: 9bb17a0092a16a3c72a4b701bda9271af02fcfb2
https://github.com/llvm/llvm-project/commit/9bb17a0092a16a3c72a4b701bda9271af02fcfb2
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang-tools-extra/clangd/unittests/CMakeLists.txt
Log Message:
-----------
[clangd] Disable PCH reuse for ClangdTests (#201232)
Fixes https://github.com/llvm/llvm-project/issues/200999
Commit: 57b09398b60d6bc95993435e51989bfcc032ad49
https://github.com/llvm/llvm-project/commit/57b09398b60d6bc95993435e51989bfcc032ad49
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M libc/src/unistd/linux/alarm.cpp
Log Message:
-----------
[libc] Fix alarm layout mismatch on 32-bit time64 (#201276)
Fixed alarm implementation on 32-bit architectures with 64-bit time_t
(like RISC-V 32-bit). The SYS_setitimer syscall on these platforms
expects the legacy 32-bit struct itimerval (with 32-bit tv_sec and
tv_usec). Convert the arguments to this layout before invoking the
syscall to avoid the kernel misinterpreting the timeout.
Assisted-by: Automated tooling, human reviewed.
Commit: d0af9c8e3f32c28e259ea90bbb179e713e62c384
https://github.com/llvm/llvm-project/commit/d0af9c8e3f32c28e259ea90bbb179e713e62c384
Author: Christian Sigg <csigg at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[bazel] Port 142ad48 (#201283)
Commit: c2ed0b1d825d7c75ca15b57812767ec3858c60db
https://github.com/llvm/llvm-project/commit/c2ed0b1d825d7c75ca15b57812767ec3858c60db
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Analysis/CaptureTracking.cpp
Log Message:
-----------
[CaptureTracking] Remove allocator comparison special case (#201143)
CaptureTracking had a special case that (incorrectly) reported
`captures(none)` for comparisons of allocation functions with null.
Remove this special case and return the correct
`captures(address_is_null)` result instead.
It seems like this doesn't have any practical benefit anymore, as things
like AA will ignore address-only captures nowadays.
Commit: 6e6c51be667e95ee456efdc6d28b2184ceb6ed32
https://github.com/llvm/llvm-project/commit/6e6c51be667e95ee456efdc6d28b2184ceb6ed32
Author: Vinay Deshmukh <vinay_deshmukh at outlook.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/include/__iterator/erase_if_container.h
M libcxx/include/__node_handle
M libcxx/include/__tree
M libcxx/include/__type_traits/make_transparent.h
M libcxx/include/__utility/default_three_way_comparator.h
M libcxx/include/__utility/lazy_synth_three_way_comparator.h
M libcxx/include/__utility/try_key_extraction.h
M libcxx/include/map
M libcxx/include/version
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/for_each.associative.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/ranges.for_each.associative.pass.cpp
M libcxx/test/std/containers/associative/from_range_associative_containers.h
M libcxx/test/std/containers/associative/map/compare.pass.cpp
M libcxx/test/std/containers/associative/map/get_allocator.pass.cpp
M libcxx/test/std/containers/associative/map/incomplete_type.pass.cpp
M libcxx/test/std/containers/associative/map/map.access/at.pass.cpp
M libcxx/test/std/containers/associative/map/map.access/empty.pass.cpp
M libcxx/test/std/containers/associative/map/map.access/index_key.pass.cpp
M libcxx/test/std/containers/associative/map/map.access/index_rv_key.pass.cpp
M libcxx/test/std/containers/associative/map/map.access/index_tuple.pass.cpp
M libcxx/test/std/containers/associative/map/map.access/iterator.pass.cpp
M libcxx/test/std/containers/associative/map/map.access/max_size.pass.cpp
M libcxx/test/std/containers/associative/map/map.access/size.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/alloc.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/assign_initializer_list.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/compare.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/compare_alloc.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/copy.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/copy_alloc.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/copy_assign.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/deduct.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/deduct_const.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/default.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/default_noexcept.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/dtor_noexcept.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/from_range.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/initializer_list.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/initializer_list_compare.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/initializer_list_compare_alloc.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/iter_iter.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/iter_iter_comp.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/iter_iter_comp_alloc.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/move.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/move_alloc.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/move_assign.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/move_noexcept.pass.cpp
M libcxx/test/std/containers/associative/map/map.erasure/erase_if.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/clear.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/emplace.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/emplace_hint.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/erase_iter.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/erase_iter_iter.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/erase_key.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/extract_iterator.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/extract_key.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_cv.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_initializer_list.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_iter_cv.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_iter_iter.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_iter_rv.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_node_type.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_node_type_hint.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_or_assign.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_range.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_rv.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/merge.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/try.emplace.pass.cpp
M libcxx/test/std/containers/associative/map/map.nonmember/compare.three_way.pass.cpp
M libcxx/test/std/containers/associative/map/map.nonmember/op_compare.pass.cpp
M libcxx/test/std/containers/associative/map/map.observers/key_comp.pass.cpp
M libcxx/test/std/containers/associative/map/map.observers/value_comp.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/contains.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/contains_transparent.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/count.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/count0.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/count_transparent.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/equal_range.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/equal_range0.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/equal_range_transparent.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/find.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/find0.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/lower_bound.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/lower_bound0.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/upper_bound.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/upper_bound0.pass.cpp
M libcxx/test/std/containers/associative/map/map.special/member_swap.pass.cpp
M libcxx/test/std/containers/associative/map/map.special/non_member_swap.pass.cpp
M libcxx/test/std/containers/associative/map/map.special/swap_noexcept.pass.cpp
M libcxx/test/std/containers/associative/map/map.value_compare/invoke.pass.cpp
M libcxx/test/std/containers/associative/map/types.pass.cpp
M libcxx/test/std/containers/container.node/node_handle.pass.cpp
M libcxx/test/std/containers/insert_range_maps_sets.h
M libcxx/test/std/language.support/support.limits/support.limits.general/map.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
A libcxx/test/support/CopyConstructible.h
M libcxx/test/support/is_transparent.h
M libcxx/test/support/private_constructor.h
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++] Make `<map>` `std::map` constexpr as part of P3372R3 (#134330)
Fixes https://github.com/llvm/llvm-project/issues/128660
Adds `constexpr` support for `std::map` as per P3372R3
---------
Co-authored-by: A. Jiang <de34 at live.cn>
Commit: 6a7b8876153815cf3847d952614440e79e82fc86
https://github.com/llvm/llvm-project/commit/6a7b8876153815cf3847d952614440e79e82fc86
Author: Wenju He <wenju.he at intel.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M libclc/CMakeLists.txt
M libclc/README.md
Log Message:
-----------
[libclc] Use generic spirv*-unknown-unknown clang triple for SPIR-V targets (#199618)
spirv-diff shows only numbering change to
spirv64-unknown-unknown/libclc.spv. No change in `llvm-spirv -to-text`
outputs. llvm-diff shows no change on reverse-translated bitcode files.
Also fixes a bug that spirv32-unknown-unknown was incorrectly using
64-bit triple.
Update README.md to use the generic target triple for SPIR-V targets.
Commit: 6b5bb08d3aa3f498b7bd9f6bb43376719bddfa60
https://github.com/llvm/llvm-project/commit/6b5bb08d3aa3f498b7bd9f6bb43376719bddfa60
Author: Wenju He <wenju.he at intel.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/test/CodeGen/target-data.c
M clang/test/Frontend/spirv-target-validation.c
Log Message:
-----------
Revert "[OpenCL] Allow mesa3d OS in spirv32 and spirv64 targets" (#200727)
Reverts llvm/llvm-project#197148
libclc will use generic target triple spirv32[64]-unknown-unknown for use in mesa.
Commit: edcafdb6af16350da3444ac6bde10897a4c4ceee
https://github.com/llvm/llvm-project/commit/edcafdb6af16350da3444ac6bde10897a4c4ceee
Author: Raphael Isemann <rise at apple.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbpexpect.py
M lldb/test/API/commands/apropos/formatting/TestAproposFormatting.py
M lldb/test/API/commands/expression/multiline-completion/TestMultilineCompletion.py
M lldb/test/API/commands/expression/multiline-navigation/TestMultilineNavigation.py
M lldb/test/API/commands/gui/basic/TestGuiBasic.py
M lldb/test/API/commands/gui/basicdebug/TestGuiBasicDebug.py
M lldb/test/API/commands/gui/breakpoints/TestGuiBreakpoints.py
M lldb/test/API/commands/gui/expand-threads-tree/TestGuiExpandThreadsTree.py
M lldb/test/API/commands/gui/spawn-threads/TestGuiSpawnThreads.py
M lldb/test/API/commands/gui/viewlarge/TestGuiViewLarge.py
M lldb/test/API/iohandler/autosuggestion/TestAutosuggestion.py
M lldb/test/API/iohandler/completion/TestIOHandlerCompletion.py
M lldb/test/API/iohandler/resize/TestIOHandlerResize.py
M lldb/test/API/iohandler/sigint/TestIOHandlerPythonREPLSigint.py
M lldb/test/API/iohandler/sigint/TestProcessIOHandlerInterrupt.py
M lldb/test/API/iohandler/stdio/TestIOHandlerProcessSTDIO.py
M lldb/test/API/iohandler/unicode/TestUnicode.py
M lldb/test/API/repl/clang/TestClangREPL.py
M lldb/test/API/terminal/TestDisabledBreakpoints.py
M lldb/test/API/terminal/TestEditline.py
Log Message:
-----------
[lldb][test] Always call quit when tearing down pexpect tests (#201100)
Right now we manually have to call quit at the end of each pexpect test.
This patches makes this call automatic.
This also makes tests that missed the call and where previously waiting
for a timeout faster. For example, TestClangREPL.py now only takes about
10 seconds to run instead of 1 minute.
Commit: 97bb7ec082b675cabae8c9e5001a8a8c14d03731
https://github.com/llvm/llvm-project/commit/97bb7ec082b675cabae8c9e5001a8a8c14d03731
Author: Xavier Roche <xavier.roche at algolia.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M libcxx/include/__type_traits/integer_traits.h
M libcxx/test/libcxx/concepts/concepts.arithmetic/__libcpp_signed_integer.compile.pass.cpp
M libcxx/test/libcxx/concepts/concepts.arithmetic/__libcpp_unsigned_integer.compile.pass.cpp
M libcxx/test/std/containers/views/mdspan/extents/index_type.verify.cpp
M libcxx/test/std/numerics/numeric.ops/numeric.ops.sat/saturating_cast.compile.pass.cpp
M libcxx/test/std/utilities/utility/utility.intcmp/intcmp.verify.cpp
Log Message:
-----------
[libc++] Reject cv-qualified types in __is_signed/unsigned_integer_v (#200377)
`__is_signed_integer_v` and `__is_unsigned_integer_v` previously
admitted cv-qualified types, contradicting `[basic.fundamental]/p1-2`.
The fix adds `__is_unqualified_v<_Tp>` to both predicates.
Reported by @jwakely on
[#185027](https://github.com/llvm/llvm-project/pull/185027#issuecomment-4574289895).
Trait-level tests cover all consumers via the shared concept; cast-like
templates (`in_range`, `saturating_cast`, `extents`) get explicit
cv-rejection tests.
Assisted-by: Claude (Anthropic)
---------
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
Commit: 8d42953f1518d3123ad01e4e9ccbed67042e08af
https://github.com/llvm/llvm-project/commit/8d42953f1518d3123ad01e4e9ccbed67042e08af
Author: Christian Sigg <csigg at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Port c264e07 (#201292)
Commit: 7b0d00f374097fc364ff7a40c846bb98f4950945
https://github.com/llvm/llvm-project/commit/7b0d00f374097fc364ff7a40c846bb98f4950945
Author: Aayush Shrivastava <iamaayushrivastava at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/docs/CommandGuide/llvm-objcopy.rst
M llvm/docs/CommandGuide/llvm-strip.rst
M llvm/include/llvm/ObjCopy/CommonConfig.h
M llvm/include/llvm/ObjCopy/ObjCopy.h
M llvm/lib/ObjCopy/Archive.cpp
M llvm/lib/ObjCopy/ObjCopy.cpp
A llvm/test/tools/llvm-objcopy/verbose.test
M llvm/tools/llvm-objcopy/CommonOpts.td
M llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
M llvm/tools/llvm-objcopy/llvm-objcopy.cpp
Log Message:
-----------
[llvm-objcopy] Add --verbose option to llvm-strip/llvm-objcopy (#196611)
Added `--verbose / -v` option to `llvm-strip` and `llvm-objcopy` as part
of #123041, matching GNU strip's output format. When the flag is passed,
the tool prints one line per file processed.
copy from `'input.o' [elf64-x86-64] to 'output.o' [elf64-x86-64]`
Commit: e579340c15c1c2fa814351cde0352e9be5c4878c
https://github.com/llvm/llvm-project/commit/e579340c15c1c2fa814351cde0352e9be5c4878c
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
[AMDGPU][NFC] Use generated hasMinMaxI64Insts subtarget feature query (#201052)
Replace the custom GCNSubtarget::hasIntMinMax64 helper with the
generated hasMinMaxI64Insts from AMDGPUSubtargetFeature.
Commit: 1bd2a0ecbafce9fbea329f1b06bb3987126c4581
https://github.com/llvm/llvm-project/commit/1bd2a0ecbafce9fbea329f1b06bb3987126c4581
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
A llvm/test/CodeGen/SystemZ/vec-move-25.ll
Log Message:
-----------
[SystemZ] Don't zero extend after a VLGV[BHF] instruction. (#201109)
The VLGV already zero extends up to 64 bits, so a following zero extend
is not needed.
New TableGen patterns for these cases as well as a handling to avoid
tryRISBGZero() selecting i64 cases.
Commit: f1620435a384c56e718a80ca0b2695285b6ce978
https://github.com/llvm/llvm-project/commit/f1620435a384c56e718a80ca0b2695285b6ce978
Author: A. Jiang <de34 at live.cn>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M libcxx/test/support/nasty_string.h
Log Message:
-----------
[libc++][test] Make narrowing in `nasty_char_traits::to_char_type` more explicit (#138375)
Previously, the cast was allowed due to
[P0960R3](https://wg21.link/p0960r3), which made narrowing implicitly
done in the parenthesized aggregate initialization. MSVC doesn't seem
happy with such an implicit manner, despite not being
copy-initialization or list-initialization, and emits warning C4242.
This patch makes the narrowing more explicit to MSVC with `static_cast`.
Follows up 3e7be494f84e51d5f4245d6f39e380a500f226a6.
Commit: 74bf9b5666a6450ef87b130070b5df3da365183d
https://github.com/llvm/llvm-project/commit/74bf9b5666a6450ef87b130070b5df3da365183d
Author: Martin Wehking <martin.wehking at arm.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Basic/arm_sve_sme_incl.td
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2_fp_int_cvtn_x2.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2_int_fp_cvt.c
M clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_LP_sve2p3_OR_sme2p3_RP___sme_AND_LP_sve2p3_OR_sme2p3_RP.c
M clang/utils/TableGen/SveEmitter.cpp
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics-fp-converts.ll
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics-fp-converts_x2.ll
Log Message:
-----------
[AArch64] Add 9.7 CVT data processing intrinsics (#186807)
Add Clang intrinsics
svcvtt_f16_s8, _f32_s16, _f64_s32, _f16_u8, _f32_u16, _f64_u32
svcvtb_f16_s8, _f32_s16, _f64_s32, _f16_u8, _f32_u16, _f64_u32
+ lowering to AARCH64 Instrs. SCVTF, SCVTFLT, UCVTF, UCVTFLT
and Clang instrinsics:
svcvtn_s8[_f16_x2], _s32[_f64_x2], _u8[_f16_x2], _u16[_f32_x2],
_u32[_f64_x2]
+ lowering to AARCH64 Instrs. FCVTZSN, FCVTZUN
The Clang intrinsics are guarded by the sve2.3 and sme2.3 feature flags.
ACLE Patch:
https://github.com/ARM-software/acle/pull/428
The patch reuses `IsReductionQV` for resolving the overload of
intrinsics.
This naming is misleading and needs changed
Commit: e202047408e85b061a936a985ee9fe1e5b651633
https://github.com/llvm/llvm-project/commit/e202047408e85b061a936a985ee9fe1e5b651633
Author: eiytoq <eiytoq at outlook.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/span
M libcxx/test/std/containers/views/views.span/span.objectrep/as_bytes.pass.cpp
M libcxx/test/std/containers/views/views.span/span.objectrep/as_writable_bytes.pass.cpp
R libcxx/test/std/containers/views/views.span/span.objectrep/as_writable_bytes.verify.cpp
Log Message:
-----------
[libc++][span] LWG4243: `as_bytes`/`as_writable_bytes` is broken with `span<volatile T>` (#200993)
Closes #171317
Commit: 6bfca10b7a9da1b35717f16a820c8e837f87ea17
https://github.com/llvm/llvm-project/commit/6bfca10b7a9da1b35717f16a820c8e837f87ea17
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
Log Message:
-----------
[AArch64] Tidy up getMemOpInfo cases where Width == Scale (NFC) (#201153)
Commit: 39658a8fa9d1900f90f218a5eeeb205c227e1262
https://github.com/llvm/llvm-project/commit/39658a8fa9d1900f90f218a5eeeb205c227e1262
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M flang-rt/test/CMakeLists.txt
Log Message:
-----------
[Flang-RT][test] Add flang-rt-mod dependency (#201297)
Flang-RT's tests require the modules since #198793. #171515 did not
account for this additional dependency.
Fixes #201254
Commit: 74f1c9417e916aed314fd429ce2faee49668ffa6
https://github.com/llvm/llvm-project/commit/74f1c9417e916aed314fd429ce2faee49668ffa6
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/lib/AST/ASTContext.cpp
A clang/test/Modules/pr195905.cppm
Log Message:
-----------
[C++20] [Modules] Ask for definition before calling isInlineDefinitionExternallyVisible (#201291)
Close https://github.com/llvm/llvm-project/issues/195905
The root cause of the problem is, after decl merging, one of the
destructor for `base` (see test case) is chosen, and its body is not
deserialized for performance as we alreday see its body in current TU.
And then, the code call
FunctionDecl::isInlineDefinitionExternallyVisible from the destructor
without a serialized body, but
FunctionDecl::isInlineDefinitionExternallyVisible's implementation
requires to see a body. Then assertion failed.
Decl merging and function decl merging is common. We can't always make
sure we find the definition without checking. It is much more
fundamental. So the PR doesn't try to touch the decl merging mechanism
or how we handle the result of lookups.
We tried to fix the issue at the calling point to make sure we have a
definition for isInlineDefinitionExternallyVisible. Other use of
isInlineDefinitionExternallyVisible does the similar thing.
Commit: 1023990a57d5824a6fc2f7a899b8f36977bbcf66
https://github.com/llvm/llvm-project/commit/1023990a57d5824a6fc2f7a899b8f36977bbcf66
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M flang/lib/Semantics/CMakeLists.txt
R flang/lib/Semantics/check-omp-metadirective.cpp
M flang/lib/Semantics/check-omp-structure.h
A flang/lib/Semantics/check-omp-variant.cpp
Log Message:
-----------
[flang][OpenMP] Rename check-omp-metadirective.cpp (NFC). (#201159)
Both METADIRECTIVE and DECLARE VARIANT fall into the "variant
directives" category, so check-omp-variant.cpp is a more accurate name
for the file that hosts their semantic checks.
Suggested in
https://github.com/llvm/llvm-project/pull/198799#issuecomment-4576970335
Commit: ceca0519375094ca3c950bbdc2b8bf3f79cdaf4b
https://github.com/llvm/llvm-project/commit/ceca0519375094ca3c950bbdc2b8bf3f79cdaf4b
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll
Log Message:
-----------
[AArch64] Fix arm64-zero-cycle-zeroing-fpr.ll check lines(NFC) (#200192)
Fix `mov`->`fmov` + add `--match-full-lines` to avoid such a pitfall
again.
Commit: 1a03c29cab6bc8c67023181cfdafbd5e0dbac815
https://github.com/llvm/llvm-project/commit/1a03c29cab6bc8c67023181cfdafbd5e0dbac815
Author: Igor Wodiany <igor.wodiany at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/test/CodeGen/AMDGPU/asm-printer-check-vcc.mir
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
M llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir
M llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
M llvm/test/CodeGen/AMDGPU/sched-image-sample-post-RA.mir
M llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
M llvm/test/MC/AMDGPU/gfx11_asm_t16_err.s
M llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
Log Message:
-----------
[AMDGPU] Remove definition of hi16 for scalar registers (#197467)
The sub-register is not supported by the back-end pipelines and will
eventually cause an assert. With this change machine verifier can
enforce that hi16 is not being used. Asm parser is also updated to error
on invalid sub-registers, instead of asserting.
This is a follow up change on #188781.
Assisted-by: Claude Code
Commit: d27b4b6c1c15d3e99d35749cefcf296500b0944e
https://github.com/llvm/llvm-project/commit/d27b4b6c1c15d3e99d35749cefcf296500b0944e
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/cast-costs.ll
Log Message:
-----------
[LV][NFC] Add another case to cast-costs.ll test (#201117)
Commit: 75dece729ccdbae01e1d09d4adf9604ea1103905
https://github.com/llvm/llvm-project/commit/75dece729ccdbae01e1d09d4adf9604ea1103905
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang-tools-extra/clang-tidy/fuchsia/StaticallyConstructedObjectsCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/fuchsia/statically-constructed-objects.cpp
Log Message:
-----------
[clang-tidy] Avoid evaluating value-dependent static initializers in fuchsia-statically-constructed-objects (#201287)
Static data member initializers in class templates could crash the check
when they used non-type template parameters. This commit skips them
during analysis.
Closes https://github.com/llvm/llvm-project/issues/201110
Commit: 62eaec6c723129d0db2c2e7112fcf1579a94f0a6
https://github.com/llvm/llvm-project/commit/62eaec6c723129d0db2c2e7112fcf1579a94f0a6
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
Log Message:
-----------
[LV] Support partial reduce subs/fsubs without a mul operand (#199664)
This allows the `UpdateR(PrevValue, ext(...))` form for fsub/sub updates
(i.e, AddWithSub or Sub reductions). For sub reductions the
codegen/handling is identical to add reductions (with the sub handled
out of loop). For AddWithSub, reductions the sub is handled in-loop with
a NegatedExtendedReduction VP expression, which the encapsulates
`reduce.[f]add(neg(ext(op)))`.
Commit: 5d0074316a86de1019c5850584f5b5cdde9edefa
https://github.com/llvm/llvm-project/commit/5d0074316a86de1019c5850584f5b5cdde9edefa
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udivrem24.ll
Log Message:
-----------
[AMDGPU] Fix LowerDIVREM24 for the unsigned case (#196418)
This PR fixes the miscompilation bug found in
https://github.com/llvm/llvm-project/issues/194829.
The test revealed that there were missing checks for the unsigned case
in LowerDIVREM24. Without those checks, the optimization is wrongly
applied assuming that the division operands do fit in 24-bit integers,
triggering the miscompilation. One of the operands was 0xFFFFFFFF.
The bug is a regression introduced in
https://github.com/llvm/llvm-project/commit/81a709503d378c188462465918df161d664c4205.
The commit refactored the conditions that validated whether the
optimization could be applied. It moved them from each call site (signed
and unsigned cases) into the function, but missed the ones for the
unsigned case.
---------
Co-authored-by: Carlo Bertolli <carlo.bertolli at amd.com>
Commit: fb6153a65039b06319cb4b9ce2fafa84d75daa6b
https://github.com/llvm/llvm-project/commit/fb6153a65039b06319cb4b9ce2fafa84d75daa6b
Author: 陈子昂 <2802328816 at qq.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/ShrinkWrap.cpp
A llvm/test/CodeGen/RISCV/shrinkwrap-save-restore-fixed-reg.ll
Log Message:
-----------
[CodeGen] Fix ShrinkWrap crash when FindIDom receives empty predecessor/successor list (#198995)
When using `-msave-restore` with `-ffixed-x5` on RISC-V,
`canUseAsPrologue` returns false for all blocks because the save-restore
prologue requires t0 (x5) which is reserved. This causes the shrink-wrap
loop to keep searching for a valid save point, eventually reaching the
entry block. On the next iteration, it calls FindIDom with the entry
block's empty predecessor list, triggering an assertion in
findNearestCommonDominator.
Fix by returning nullptr from FindIDom when the block list is empty,
which signals the caller to stop searching and give up the optimization.
Fixes #166759
Commit: 1bde29e83bc4d077d9f553d89846c4eba402f3e6
https://github.com/llvm/llvm-project/commit/1bde29e83bc4d077d9f553d89846c4eba402f3e6
Author: Osman Yasar <osmanyas05 at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/include/llvm/Target/GlobalISel/Combine.td
A llvm/test/CodeGen/AArch64/GlobalISel/combine-or-of-and.ll
A llvm/test/CodeGen/AArch64/GlobalISel/combine-or-of-and.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir
Log Message:
-----------
[GlobalISel] Add `combine_or_of_and` from SelectionDAG (#198754)
This PR adds the pattern `// fold or (and x, y), x --> x` from
SelectionDAG.
Commit: 4cfaaa679114c690edec268cb53d19d198c71bc2
https://github.com/llvm/llvm-project/commit/4cfaaa679114c690edec268cb53d19d198c71bc2
Author: Andrei Golubev <andrey.golubev at intel.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationDialect.cpp
Log Message:
-----------
[NFC][mlir][bufferization] Remove getMemRefType() helper (#199034)
Replace getMemRefType() helper with a direct usage of
options.unknownTypeConverterFn() hook. This does not change any
behaviour since all the existing call-sites would already implicitly
call the hook. The major difference could have been in the handling of
the memref layout but this does not seem to be properly handled anyhow.
As the `getMemRefType()` helper is removed, there are two cases to keep
in mind for downstream users that need to adjust the code accordingly:
1. For creating memrefs without layouts, call
`options.unknownTypeConverterFn` hook directly (the same way this patch
is doing for upstream)
2. For creating memrefs with layouts (assuming, custom ones), please
(re)implement the same helper. As only ranked memrefs can have a layout,
a call to `mlir::MemRefType::get(shape, elementType, /*your custom
layout=*/myLayout, memorySpace)` should be sufficient.
Commit: 3419e724ad5d1cf027da971581ae31c36a9dec51
https://github.com/llvm/llvm-project/commit/3419e724ad5d1cf027da971581ae31c36a9dec51
Author: Amina Chabane <amina.chabane at arm.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
A bolt/docs/BOLTAArch64OptimizationStatus.rst
Log Message:
-----------
[AArch64][BOLT] Document AArch64 optimization flag support (#198282)
BOLTAArch64OptimizationStatus.rst aims to document default-off,
user-enabled passes and their status (supported/unsupported) on AArch64.
``--simplify-rodata-loads`` has a patch in review, so I have documented
its current status.
Discussion on RST/MD:
https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/90840
Commit: 7496ee9be8d2d4467706615a975a4d61ccb3264d
https://github.com/llvm/llvm-project/commit/7496ee9be8d2d4467706615a975a4d61ccb3264d
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/sincos.ll
Log Message:
-----------
[SLP][NFC]Add a test with non-vectorized sincos, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/201312
Commit: c958962c157b728e153b6232b800cbf556812545
https://github.com/llvm/llvm-project/commit/c958962c157b728e153b6232b800cbf556812545
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
A llvm/test/Transforms/LoopInterchange/lcssa-incoming-value-is-not-instr.ll
Log Message:
-----------
[LoopInterchange] Assume LCSSA PHI incoming value may not be instruction (#201069)
This patch fixes one of the assertion failures reported in #200819. The
root cause in this case is that `moveLCSSAPhis` assumes the incoming
values of LCSSA PHIs are always instructions and unconditionally casts
them to `Instruction`.
This assumption does not always hold, especially when the incoming value
is a constant. For such LCSSA PHI nodes, it's enough to merely replace
all the uses with its incoming value.
Commit: 94c0e6fb2536cb2c0dbd205fadd4a8e929388b1a
https://github.com/llvm/llvm-project/commit/94c0e6fb2536cb2c0dbd205fadd4a8e929388b1a
Author: A. Jiang <de34 at live.cn>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M libcxx/include/__locale
M libcxx/include/__locale_dir/messages.h
M libcxx/include/__locale_dir/money.h
M libcxx/test/libcxx/localization/locales/use_facet.abort.pass.cpp
A libcxx/test/libcxx/localization/nodiscard.verify.cpp
Log Message:
-----------
[libc++][locale] Applied `[[nodiscard]]` (#200726)
`[[nodiscard]]` should be applied to functions where discarding the
return value is most likely a correctness issue.
- https://libcxx.llvm.org/CodingGuidelines.html
- https://wg21.link/localization
Remarks:
- Virtual functions are not marked `[[nodiscard]]` because they are not
expected to be directly called by users.
- `messages::open` is marked `[[nodiscard]]` because it is logically
similar to `operator new` and its friends.
Commit: e2efa2e958270e0f21d9db2aa9a393006c9d6d0b
https://github.com/llvm/llvm-project/commit/e2efa2e958270e0f21d9db2aa9a393006c9d6d0b
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/phi-vectorization-budget.ll
Log Message:
-----------
[SLP] Gather wide PHI bundles to avoid compile-time blow-up
Vectorizing a PHI bundle recurses into one operand bundle per incoming
value, so the analysis cost grows with bundle_size * num_incoming_values.
With revectorization, very wide PHIs from jump threading make
opt -O3 hang for minutes/hours. Such PHIs are not profitable to vectorize,
so gather the bundle once that product exceeds a budget (new hidden option
-slp-phi-vectorization-budget, default 1024).
Fixes #201181
Reviewers: hiraditya, bababuck, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/201227
Commit: c7ecad5c289c67829d8d43013c9ac46bc92ae4e6
https://github.com/llvm/llvm-project/commit/c7ecad5c289c67829d8d43013c9ac46bc92ae4e6
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M cross-project-tests/debuginfo-tests/dexter/dex/debugger/DebuggerControllers/DebuggerControllerBase.py
A cross-project-tests/debuginfo-tests/dexter/dex/debugger/DebuggerControllers/ScriptDebuggerController.py
M cross-project-tests/debuginfo-tests/dexter/dex/dextIR/DextIR.py
M cross-project-tests/debuginfo-tests/dexter/dex/dextIR/LocIR.py
M cross-project-tests/debuginfo-tests/dexter/dex/dextIR/StepIR.py
M cross-project-tests/debuginfo-tests/dexter/dex/tools/test/Tool.py
A cross-project-tests/debuginfo-tests/dexter/feature_tests/scripts/debugging/Inputs/header.h
A cross-project-tests/debuginfo-tests/dexter/feature_tests/scripts/debugging/simple_where_function.cpp
A cross-project-tests/debuginfo-tests/dexter/feature_tests/scripts/debugging/simple_where_line.cpp
A cross-project-tests/debuginfo-tests/dexter/feature_tests/scripts/debugging/where_file_paths.cpp
Log Message:
-----------
[Dexter] Add basic debugging support for structured scripts (#197418)
This patch adds a debugger controller for structured scripts. This
controller operates as follows:
- !where nodes at the root of the script (currently the only kind
allowed) have function or line breakpoints set to cover them.
- Whenever the debugger stops, the controller will examine the stack to
determine whether any !where nodes are in scope.
- While any !where is in scope, its associated !values will be evaluated
in the debugger and the results stored, and the debugger will
single-step.
- When no !where is in scope, the debugger will continue.
This is a simplified implementation compared to the final version, as it
is missing support for nested !where nodes, Scope evaluation, and
conditions/hit counts; these will be added in later commits.
Commit: 869be014cf9a02f26ad938cc40fa83dfb62e90f9
https://github.com/llvm/llvm-project/commit/869be014cf9a02f26ad938cc40fa83dfb62e90f9
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
Log Message:
-----------
[AMDGPU] Diagnose unsupported permlane16/mov.dpp8/tanh intrinsics (#200585)
Commit: 2fabed5f49d950b669b9f9a5a624d61aa8bdeda0
https://github.com/llvm/llvm-project/commit/2fabed5f49d950b669b9f9a5a624d61aa8bdeda0
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
A llvm/test/CodeGen/SPIRV/cloned-funcs-metadata-oob.ll
Log Message:
-----------
[SPIR-V] Diagnose out-of-bounds argument index in function type metadata (#200601)
The argument index in spv.cloned_funcs/spv.mutated_callsites metadata
was used to index the parameter list with only a lower bound assert
Add boundaries check it and report_fatal_error rather than silently
miscompiling
Commit: 66ceecd18b654a4e94c70d2a8d7239114e2705cf
https://github.com/llvm/llvm-project/commit/66ceecd18b654a4e94c70d2a8d7239114e2705cf
Author: Igor Wodiany <igor.wodiany at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/test/CodeGen/AMDGPU/asm-printer-check-vcc.mir
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
M llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
M llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir
M llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
M llvm/test/CodeGen/AMDGPU/sched-image-sample-post-RA.mir
M llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
M llvm/test/MC/AMDGPU/gfx11_asm_t16_err.s
M llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
Log Message:
-----------
Revert "[AMDGPU] Remove definition of hi16 for scalar registers" (#201309)
Reverts llvm/llvm-project#197467 as it causes a buildbot failure.
Commit: 90d907b54ca222271439467c5f42073625211fed
https://github.com/llvm/llvm-project/commit/90d907b54ca222271439467c5f42073625211fed
Author: Mirko Brkušanin <Mirko.Brkusanin at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SMInstructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[AMDGPU] Add llvm.amdgcn.s.prefetch.inst intrinsic (#192440)
- New intrinsic
- New SubtargetFeature for all s_prefetch_inst*/data*
- Support blockaddress
Commit: 8a81ecc4e7cfc3b63041cc28e620d339f1933cb6
https://github.com/llvm/llvm-project/commit/8a81ecc4e7cfc3b63041cc28e620d339f1933cb6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/test/CodeGen/X86/avx512-trunc.ll
Log Message:
-----------
[X86] avx512-trunc.ll - add basic masked trunc coverage for #200617 (#201318)
Commit: d515a6e5381d967f81f5d18d1b2a7a3255b48dc6
https://github.com/llvm/llvm-project/commit/d515a6e5381d967f81f5d18d1b2a7a3255b48dc6
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M libc/include/llvm-libc-types/CMakeLists.txt
Log Message:
-----------
[libc] Remove redundant file(COPY) for x86_64 types (#201317)
Removed the redundant file(COPY) command from the x86_64 architecture
check in libc/include/llvm-libc-types/CMakeLists.txt.
This command eagerly copies the x86_64 directory to the binary
directory, which is redundant because individual headers are already
copied by their respective add_header targets. It also preserved
read-only depot permissions from the source tree, making the build
directory read-only and causing rm -rf to fail.
Assisted-by: Automated tooling, human reviewed.
Commit: 7dc66bf2353d09a84dfa6aca70942b3902d94f6e
https://github.com/llvm/llvm-project/commit/7dc66bf2353d09a84dfa6aca70942b3902d94f6e
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/u_char.h
A libc/include/llvm-libc-types/u_int32_t.h
A libc/include/llvm-libc-types/uint.h
M libc/include/sys/types.yaml
Log Message:
-----------
[libc] Add BSD/SysV compatibility types to sys/types.h (#201314)
Added u_char, u_int32_t, and uint to sys/types.h. These types are
commonly used by legacy and compatibility-reliant libraries like libedit
and libcap.
Assisted-by: Automated tooling, human reviewed.
Commit: fb2233e688d089b1d7bf9a8032cd92a6de2ae213
https://github.com/llvm/llvm-project/commit/fb2233e688d089b1d7bf9a8032cd92a6de2ae213
Author: Luke Lau <luke at igalia.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Move mask intrinsics out of VP section (#201282)
Somehow llvm.get.active.lane.mask and
llvm.loop.dependence.{war,raw}.mask ended up in the VP intrinsics
section of the LangRef. This PR pulls them out into a new "Vector Mask
Intrinsics" section.
Commit: f86688b3a16be15f7a50132d0497fcef6110afd1
https://github.com/llvm/llvm-project/commit/f86688b3a16be15f7a50132d0497fcef6110afd1
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
A llvm/test/Transforms/LoopInterchange/function-attr.ll
R llvm/test/Transforms/LoopInterchange/memory-attr.ll
Log Message:
-----------
[LoopInterchange] Rename test to `function-attr.ll` (NFC) (#201330)
The new name is more appropriate if we want to add further test cases.
Commit: 2ba8bebb270d64a486096b6258f8ea6f764a630c
https://github.com/llvm/llvm-project/commit/2ba8bebb270d64a486096b6258f8ea6f764a630c
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M flang/include/flang/Semantics/openmp-utils.h
M flang/include/flang/Semantics/symbol.h
M flang/lib/Lower/OpenMP/Atomic.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/mod-file.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/symbol.cpp
M flang/test/Semantics/OpenMP/requires-modfile.f90
Log Message:
-----------
[flang][OpenMP] Refactor interface of WithOmpDeclarative (#200876)
The two major changes are that:
1. The clause sets are not optional anymore. In the absence of any
declarative directives (REQUIRES in this case), the set will simply be
empty.
2. The optional memory order member will serve as the value of the
argument to the ATOMIC_DEFAULT_MEM_ORDER clause, and will only be
meaningful (and required) when the clause is a member of the clause set.
Additionally,
- Rename the RequiredClauses type alias to OmpClauseSet, since it will
be reused for other purposes in the future.
- Remove the has_* functions since they are not necessary, and when more
members are added these functions will only add to the clutter.
- Add a version_ member for printing directive/clause names.
Commit: 23172e419c567115a7a00e48debae327c502fe03
https://github.com/llvm/llvm-project/commit/23172e419c567115a7a00e48debae327c502fe03
Author: Valery Pykhtin <valery.pykhtin at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/include/llvm/Support/AMDGPUAddrSpace.h
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
Log Message:
-----------
[NFC][AMDGPU] Introduce AMDGPU::FlatAddrSpace enum to replace uint64_t FLAT discriminant (#200431)
This is the reapply of https://github.com/llvm/llvm-project/pull/200396 with renamed AMDGPU::FlatVariant to AMDGPU::FlatAddrSpace to avoid name conflict with function arguments (build error on gcc)
Replace the uint64_t parameter used as a FLAT address-space segment discriminant in isLegalFLATOffset, splitFlatOffset, allowNegativeFlatOffset with a typed enum class to prevent usage of raw TSFlags.
Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
Commit: 8943bfbd08202aae1e85181082a1ec337e6a8b0b
https://github.com/llvm/llvm-project/commit/8943bfbd08202aae1e85181082a1ec337e6a8b0b
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
Log Message:
-----------
[AMDGPU] Do not scale private alloca size when using flat-scratch (#201142)
When using flat-scratch, the `scratch_load/scratch_store` instructions
scale the stack offset by the wavefront size on their own.
Scaling the alloca-size by the wave-front size lead to accesses outside
of the private-memory limit.
Commit: 0385a1b4e839ed35bf44bb5391999c3d48a8e2f7
https://github.com/llvm/llvm-project/commit/0385a1b4e839ed35bf44bb5391999c3d48a8e2f7
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avg-mask.ll
M llvm/test/CodeGen/X86/avx512-trunc.ll
Log Message:
-----------
[X86] combineSelect - fold select(c,trunc(x),y) -> X86ISD::MTRUNC(x,y,c) for non-BWI targets (#201339)
Fixes #200617
Commit: 27fd70f849f417db18ac581457f0419332a7a1fa
https://github.com/llvm/llvm-project/commit/27fd70f849f417db18ac581457f0419332a7a1fa
Author: Yanzuo Liu <zwuis at outlook.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/include/clang/Basic/LangOptions.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/RecordLayoutBuilder.cpp
M clang/lib/Basic/TargetInfo.cpp
M clang/lib/CodeGen/Targets/ARM.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
Log Message:
-----------
[clang][NFC] Introduce `LangOptions::isCompatibleWith(ClangABI)` (#201067)
This slightly improves readability and reduces the probability of
off-by-one errors.
Commit: 799af5d80d6335cd10de91506b6beb7c043278eb
https://github.com/llvm/llvm-project/commit/799af5d80d6335cd10de91506b6beb7c043278eb
Author: Joshua Rodriguez <josh.rodriguez at arm.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/arm64-vcnt.ll
Log Message:
-----------
[AArch64][GlobalISel] Add handling for cls intrinsic (#200440)
Neon intrinsic neon.cls wasn't linked to the generic node G_CTLS.
Add in this link in Legalisation (LegalizeIntrinsic), to allow the intrinsic to properly lower.
Commit: d67b41a20ca55b47f4d09bdba609fc305a9d2484
https://github.com/llvm/llvm-project/commit/d67b41a20ca55b47f4d09bdba609fc305a9d2484
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/test/CodeGen/X86/clmul-vector.ll
Log Message:
-----------
[X86] Add clmul vector allones baseline tests for #200592 (#201321)
Commit: 906968b379d2d591299b677868e4364e0ea1b5a0
https://github.com/llvm/llvm-project/commit/906968b379d2d591299b677868e4364e0ea1b5a0
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/test/Transforms/LoopInterchange/function-attr.ll
Log Message:
-----------
[LoopInterchange] Add tests for func attributes called in loops (NFC) (#201331)
LoopInterchange has special handling for call instructions. In general,
loops that contain call instructions are not legal to interchange, but
if a call satisfies certain conditions, we allow the interchange to
proceed. Currently, the legality checker only verifies whether the call
reads or writes memory. However, as pointed out in
https://github.com/llvm/llvm-project/pull/200828#issuecomment-4593914293,
we also need to ensure that the call does not diverge. Otherwise, an
illegal interchange may occur.
This patch adds test cases that demonstrate the issue, which will be
fixed in a follow-up patch.
Commit: b1d5d7e3237ac5be660f82c71ec7323d6db7b724
https://github.com/llvm/llvm-project/commit/b1d5d7e3237ac5be660f82c71ec7323d6db7b724
Author: John Brawn <john.brawn at arm.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/cmp_cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fully-unrolled-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-small-size.ll
Log Message:
-----------
[VPlan] Don't use the legacy cost model for loop conditions (#156864)
The current behaviour of using the legacy cost model for instructions
that compute the loop exit condition gets the wrong result when the loop
has been transformed to use a different exit condition, e.g. when have
tail-folded predicated vectorization the exit condition is based on the
predicate vector.
Fix this by adding cost computation for BranchOnCount and removing the
restriction on computing the cost for scalar ICmp/FCmp, and removing the
use of the legacy cost model for loop exit conditions.
This causes quite a lot of changes to expected output in tests. Some of
these are just changes to the -debug output, others are choosing a
different VF due to previously over or under-estimating the cost, and in
others the minimum trip count has changed as we now compute the cost for
compares in the middle block.
Commit: 0fd2402e94447ae9ae77e319cc8e312b97e5a30e
https://github.com/llvm/llvm-project/commit/0fd2402e94447ae9ae77e319cc8e312b97e5a30e
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M offload/ci/hip-tpl.py
Log Message:
-----------
[HIP] Remove explicit compiler-rt from bot recipe (#201329)
The same change was done to the AnnotatedBuilder script recently. Let's
keep them in sync.
https://github.com/llvm/llvm-zorg/pull/861
Commit: 52cf94a82eabfe70d417c17a3ab38736ded4938b
https://github.com/llvm/llvm-project/commit/52cf94a82eabfe70d417c17a3ab38736ded4938b
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
M llvm/test/CodeGen/AMDGPU/widen_extending_scalar_loads.ll
Log Message:
-----------
[AMDGPU] Drop !noundef when widening sub-DWORD constant loads (#201085)
The widened i32 load reads bytes outside the original sub-DWORD load, so
new op cannot claim !noundef
Commit: 70d62e1e10907e1bd6dd0e92968acbf6fe58af37
https://github.com/llvm/llvm-project/commit/70d62e1e10907e1bd6dd0e92968acbf6fe58af37
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/include/clang/Driver/Driver.h
M clang/include/clang/Driver/ToolChain.h
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/AIX.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/AVR.cpp
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Driver/ToolChains/Fuchsia.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/Haiku.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/Driver/ToolChains/OpenBSD.cpp
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/lib/Driver/ToolChains/SPIRV.cpp
M clang/lib/Driver/ToolChains/Serenity.cpp
M clang/lib/Driver/ToolChains/WebAssembly.cpp
Log Message:
-----------
[Clang] Rework LTO mode selection to be a Toolchain property (#201155)
Summary:
Currently, the LTO mode is a property of the Driver, which makes sense
because it is used to set up phases. However, we currently have `-flto`
and `-foffload-lto`, which is a split that doesn't fully work with the
full context of a heterogenous compilation as it is 'all-or-nothing'.
This PR seeks to be mostly NFC for now, just moving the queries to a
per-toolchain interface rather than the static driver mode setting we
have right now. The *single* use of this before ToolChains are created
is for the Webassembly toolchain to set an include path. This is now
just a direct check on the flag, which is consistent. In the future they
could shift to fat LTO objects as well.
The main goal for the PR is to allow the GPU / Offloading toolchains to
specify their "real" LTO behavior. Right now SPIR-V and AMDGCN both
default to LTO, but rather than re-use the LTO handling we hack through
the driver phases to override it. Allowing this split would let us
heavily simplify this logic.
Co-authored-by: Cursor <cursoragent at cursor.com>
---------
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: 911eddeed7ba2359c953396afce934fee269f50e
https://github.com/llvm/llvm-project/commit/911eddeed7ba2359c953396afce934fee269f50e
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/test/Driver/include-omp-header.f90
M flang/test/lit.cfg.py
M openmp/module/CMakeLists.txt
Log Message:
-----------
[Flang] Fix omp_lib.h location and search path (#201104)
Before this PR, omp_lib.h is emitted to `${PREFIX}/include` or
`${PREFIX}/lib/clang/<version>/include` (install prefix) and
`${PREFIX}/runtime/src/omp_lib.h` (builddir prefix). It is never found
there because the driver only adds `${PREFIX}/include/flang/OpenMP` to
the include path.
Fix the `omp_lib.h` include by using the same mechanism as the
omp_lib.mod; that is, move it to
`${PREFIX}/lib/clang/<version>/finclude/flang/<target-triple>`. The
search path is already added by the driver via
`-fintrinsics-modules-path` by the driver. Although omp_lib.h currently
does not contain anything target-specific, it could do so in the future
and I don't think it is worth the effort to add a mechanism without the
target triple. It should also me consistent with omp_lib.mod.
The changes in detail consist of:
1. Move the omp_lib.h output in the builddir to
`${RUNTIMES_OUTPUT_RESOURCE_MOD_DIR}`. This already takes care of
whether it is a bootstrapping build or not.
3. Move the omp_lib.h install dir to
`${RUNTIMES_INSTALL_RESOURCE_MOD_PATH}`.
4. Remove the implicit search path `include/flang/OpenMP` from the
frontend. There is nothing in there anyway.
5. Hardcoding the include search path for testing to the
`LLVM_RUNTIME_TARGETS=default` build becomes unnecessary. This was way
the `include-omp-header.f90` test was still passing, although it would
not work outside the regression tests. Essentially, it tested
lit.site.cfg, not the driver.
6. Replace the old `include-omp-header.f90` test. It created a temporary
`omp_lib.h` that interferes with any other test that use `include
omp_lib.h` (there currently isn't but I originally intended to add the
replacement as an additional omp_lib.h test which resulted in a flaky
test while the original test was there). Due to how the %flang(_fc1)
substitution works, lookup order may also vary.
Commit: e5332f3ea1766a0cfaa1a50a4db9f78c9d39cd3b
https://github.com/llvm/llvm-project/commit/e5332f3ea1766a0cfaa1a50a4db9f78c9d39cd3b
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/include/llvm/MC/MCGOFFObjectWriter.h
M llvm/lib/MC/GOFFObjectWriter.cpp
Log Message:
-----------
[SystemZ][GOFF] Implement reset() for GOFFObjectWriter (#201197)
The reset() methods is used to free memory before the object is
destructed or reused. This change adds this functionality to the GOFF
writer.
Commit: c689c165ba2723285258975a14cd562d41d059ab
https://github.com/llvm/llvm-project/commit/c689c165ba2723285258975a14cd562d41d059ab
Author: Zorojuro <sawantsukumar at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M libc/src/__support/FPUtil/bfloat16.h
M libc/test/src/__support/FPUtil/bfloat16_test.cpp
Log Message:
-----------
[libc] Add compound assignment operator overloads for BFloat16 (#201301)
The current Bfloat16 has normal operator overloads `+` , `-` , `=`,
`!=`, `*`, & `/`.
Later during a function failure `*=` was added in
https://github.com/llvm/llvm-project/pull/182882
For completeness the rest of the operators: `/=`, `+=`, `-=` are added
These are added along with some smoke test .
Commit: a2369b9743391351b1dd4a5c38fb61e295ff7088
https://github.com/llvm/llvm-project/commit/a2369b9743391351b1dd4a5c38fb61e295ff7088
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
Log Message:
-----------
[Clang] Fix leftover use of old LTO path (#201360)
Summary:
This was accidentally missed when I merged the refactor because it
showed up after I made the PR and didn't have any merge conflicts I
noticed.
Commit: ef4fb183a8d5c0d1910f7b5b6776ba669d6795ef
https://github.com/llvm/llvm-project/commit/ef4fb183a8d5c0d1910f7b5b6776ba669d6795ef
Author: khaki3 <47756807+khaki3 at users.noreply.github.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/test/HLFIR/opt-bufferization-eval_in_mem.fir
Log Message:
-----------
[flang][hlfir] Resolve shape_of users when bufferizing eval_in_mem (#201214)
A follow-up to #197814.
Example:
```fortran
bmat = matmul(mat, mat) ! bmat is allocatable
```
In this code, `SeparateAllocatableAssign` sizes the reallocation with an
`hlfir.shape_of` of the RHS. Once the `matmul` is lowered to
`hlfir.eval_in_mem`, that `shape_of` is an extra user, so
`EvaluateIntoMemoryAssignBufferization` erases the `eval_in_mem` while
it's still used, hitting a `use-after-erase` assertion at `-O2`.
Fix: in `OptimizedBufferization`, redirect a `shape_of` user to the
`eval_in_mem`'s shape operand before erasing it.
Commit: a7bfea843c73c9b48feb1b94c996924d2881f362
https://github.com/llvm/llvm-project/commit/a7bfea843c73c9b48feb1b94c996924d2881f362
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
R llvm/test/Transforms/InferAddressSpaces/AMDGPU/old-pass-regressions-inseltpoison.ll
R llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-inseltpoison.ll
Log Message:
-----------
[Transforms] Delete identical poison tests (NFC) (#201349)
These are now bit-identical to the original tests:
- llvm/test/Transforms/InferAddressSpaces/AMDGPU/old-pass-regressions.ll
- llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll
Commit: 9e01e0970c4cf810e99bdfde3a2329610df6d90c
https://github.com/llvm/llvm-project/commit/9e01e0970c4cf810e99bdfde3a2329610df6d90c
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M flang-rt/CMakeLists.txt
Log Message:
-----------
[Flang-RT] Disable tests by default without modules (#201311)
With #201297 flang-rt-mod is required for running tests. Disable tests
by default if module files are not built.
Commit: 7eff475c4998039878563b987121c7fcc002b7b3
https://github.com/llvm/llvm-project/commit/7eff475c4998039878563b987121c7fcc002b7b3
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/test/Driver/hip-toolchain-no-rdc.hip
Log Message:
-----------
[HIP] Fix test for --no-lto (#201367)
Commit: 3a9c6cdb5d99cbcbb98c8d3562c409ddc5822deb
https://github.com/llvm/llvm-project/commit/3a9c6cdb5d99cbcbb98c8d3562c409ddc5822deb
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
A clang/include/clang/AST/MatrixUtils.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/AST/TypePrinter.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CodeGenTypes.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/AST/HLSL/matrix_layout_attr.hlsl
A clang/test/CodeGenHLSL/matrix-layout-attr-overrides-default.hlsl
M clang/test/SemaHLSL/BuiltIns/logical-mat-operator-errors.hlsl
M clang/test/SemaHLSL/MatrixElementOverloadResolution.hlsl
M clang/test/SemaHLSL/Types/BuiltinMatrix/MatrixImplicitTruncCastWarnings.hlsl
Log Message:
-----------
[Matrix][HLSL] Add codegen support for Matrix Layout keywords (#198887)
fixes #192262
- Wrap Matrix Type in a row or column major layout attribute
- Add Helper to know which Matrix Layout to apply in codegen or check
for in Sema
- Remove the Decl Atribute and only store on the type.
Assisted by Claud Opus 4.7
Commit: 270a6a8f6742b6a0e86d1a6b3ca6b90b39a64e87
https://github.com/llvm/llvm-project/commit/270a6a8f6742b6a0e86d1a6b3ca6b90b39a64e87
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.cpp
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/symbol.h
M flang/include/flang/Support/Fortran.h
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/mod-file.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/symbol.cpp
M flang/test/Parser/OpenMP/declare_target-device_type.f90
M flang/test/Parser/OpenMP/groupprivate.f90
A flang/test/Semantics/OpenMP/declare-target-flags.f90
A flang/test/Semantics/OpenMP/declare-target-modfile.f90
M flang/test/Semantics/OpenMP/dump-requires-details.f90
Log Message:
-----------
[flang][OpenMP] Store DECLARE_TARGET information in WithOmpDeclarative (#201103)
This will be used to emit DECLARE_TARGET directives into module files.
When a symbol apperars in DECLARE_TARGET, the OmpDeclareTarget flag will
be set on it (this includes procedures containing a DECLARE_TARGET
without arguments or clauses). The set of accompanying clauses will be
stored in the associated details, in the WithOmpDeclarative mixin. The
mixin was added to ObjectEntityDetails, ProcEntityDetails, and
CommonBlockDetails.
The design goal was to be able to reconstruct the appropriate DECLARE_
TARGET directive for individual symbols for the purpose of emitting it
in a module file. Simply storing and then unparsing the AST node may
include symbols that should not be emitted.
Additionally, refactor the WithOmpDeclarative printing code for reuse in
symbol dumping for debugging, and for printing clause sets.
Commit: 9606c9ff18f0d90a639b132a7f69ebc8a8f61c99
https://github.com/llvm/llvm-project/commit/9606c9ff18f0d90a639b132a7f69ebc8a8f61c99
Author: Jameson Nash <vtjnash at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/lib/CodeGen/ABIInfoImpl.cpp
M clang/lib/CodeGen/CGAtomic.cpp
M clang/lib/CodeGen/CGBlocks.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDecl.cpp
M clang/lib/CodeGen/CGException.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprAgg.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/MicrosoftCXXABI.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/CodeGen/TargetBuiltins/X86.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/test/CodeGen/scoped-atomic-ops.c
M clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
M clang/test/CodeGenCUDA/atomic-options.hip
M clang/test/CodeGenCUDA/builtins-amdgcn.cu
M clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
M clang/test/CodeGenCUDA/record-layout.cu
M clang/test/CodeGenCXX/amdgcn-func-arg.cpp
M clang/test/CodeGenHIP/placement-new-addrspace.hip
M clang/test/CodeGenOpenCL/addr-space-struct-arg.cl
M clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl
M clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl
M clang/test/CodeGenOpenCL/atomic-ops.cl
M clang/test/CodeGenSYCL/kernel-caller-entry-point.cpp
M clang/test/OpenMP/amdgcn_target_device_vla.cpp
M clang/test/OpenMP/amdgpu_target_with_aligned_attribute.c
M clang/test/OpenMP/target_teams_generic_loop_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen_as_distribute.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp
Log Message:
-----------
Reapply "[clang] remove lots of "innocuous" addrspacecasts" (#200427)
Reapply #197745, with an additional commit to undo a small part of the
first commit, pending further analysis of alternatives to that part of it.
In particular, make the `agg.tmp` (CreateAggTemp) values keep using the
declared expression type of the RValue. This is indeed probably
sensible, since it lets Sema influence this via the expression type,
though it runs into some issues where some expression types (notably for
any load) haven't had one of the equivalent functions
getNonLValueExprType/DeduceAutoType/getUnqualifiedType called on them,
so they are bringing along additional annotation baggage which doesn't
apply the the rvalue when turned into a temporary (see comments in
getNonLValueExprType for relevant part of C++ standard). This in turn is
also rarely relevant, since inventing temporaries aren't often allowed
in this part of the pipeline (it'd require a move constructor) so the
LValue Dest already provides the type and the RValue type is ignored.
However, it does affect a single test (which loads a global but ignores
the result) and so this adds an extra `getUnqualifiedType` call to
`CodeGenFunction::EmitAnyExpr` so that load doesn't propagate the
qualifiers from source to temporary. This might be a common issue with
load-like expressions (for example, there's a `getUnqualifiedType` in
AtomicExpr code when computing the appropriate codegen for the result,
so it also didn't trust Sema to have created this correctly--and indeed
it seems that Sema expects CG to wait until after
DefaultLvalueConversion before it is does anything with the result type)
Commit: 90a172b53e77e4171b67e9fe4215707aed45cda4
https://github.com/llvm/llvm-project/commit/90a172b53e77e4171b67e9fe4215707aed45cda4
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size-error.ll
Log Message:
-----------
[AMDGPU] Reject named single register inline asm constraints for wider types (#200771)
A named single register constraint like `={v0}` was silently accepted
for i64 result, binding it to one 32-bit register
Reject scalars larger than 32 bits as well
Commit: 4a8c5d231227d7c6c61160e5be25f4626cdabbb8
https://github.com/llvm/llvm-project/commit/4a8c5d231227d7c6c61160e5be25f4626cdabbb8
Author: Yair Ben Avraham <yairba at protonmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-2velem.c
M clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
M clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c
M clang/test/CodeGen/AArch64/neon/fused-multiply.c
M clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
Log Message:
-----------
[CIR][AArch64] Lower vfmaq_lane_v and vfma_laneq_v (#197084)
Lower BI__builtin_neon_vfmaq_lane_v and BI__builtin_neon_vfma_laneq_v in
CIR.
This handles the covered vfmaq_lane_* and vfma_laneq_* ACLE wrappers by
bitcasting operands to the expected types, selecting the requested lane
from the lane source operand, and emitting fma through
emitCallMaybeConstrainedBuiltin.
For vfmaq_lane_v, the selected lane is splatted with emitNeonSplat.
For vfma_laneq_v, the lane is selected from the wider lane source; the
f64 case extracts the scalar lane before emitting scalar fma.
Neighboring scalar lane/laneq wrappers and other out-of-scope forms
remain explicit NYI cases.
Tests are moved into the existing CIR-enabled fused multiply files under
clang/test/CodeGen/AArch64/neon/, reusing upstream LLVM checks where
possible and adding CIR coverage for lane selection and fma lowering.
Part of #185382
Follow-up to #195602
Commit: f1b42dcc2326b80116430c9a60f41b0f86abbff7
https://github.com/llvm/llvm-project/commit/f1b42dcc2326b80116430c9a60f41b0f86abbff7
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
M llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll
M llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
M llvm/test/Transforms/LoopVectorize/early_exit_store_legality.ll
M llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
A llvm/test/Transforms/LoopVectorize/interleave_uncountable_exits.ll
A llvm/test/Transforms/LoopVectorize/scalarized_conditional_ops_uncountable_exits.ll
A llvm/test/Transforms/LoopVectorize/tail_fold_uncountable_exits.ll
M llvm/unittests/Transforms/Vectorize/VPlanUncountableExitTest.cpp
Log Message:
-----------
[LV] Vectorize early exit loops with stores using masking (#178454)
This is an alternative approach to vectorizing early exit loops with
stores that avoids needing to add an extra check block. This is a
fairly straightforward approach that should work on vector ISAs
supporting masked memory ops.
The basic approach is to create a mask covering all lanes _before_ any
exiting lane, using cttz.elts and active.lane.mask (which sets all lanes
to true if the uncountable exit wasn't taken). If the uncountable exit
was taken, then there will still be one scalar iteration left to perform
after the vector loop, which will also handle which exit block we should
branch to.
We no longer need to advance exit conditions in the vector body to the
next iteration (compared to the other PR), though we still need to move
the recipes needed to generate the exit condition (depending on which
memory operations are first in the loop).
The advantage this has over a full in-loop mask approach is that we
don't need to form intermediate masks for each uncountable exit; while I
haven't tried to mix this with the ongoing multiple-exit work yet, we
should be able to handle them without increasing the amount of generated
per-exit code. We also won't need to unpick which exit condition was met
first.
For a pseudo-C example of the transformation (with S1 and S2
representing statements with a side effect, like stores, or possibly a
load that may fault if continued past the early exit), given the
following scalar loop:
```c
for (i = 0; i < N; ++i) {
S1;
if (a[i] == threshold)
break;
S2;
}
```
we would have a vector loop and scalar tail like the following:
```c
int i = 0;
for (; i < vecN; i += VF) {
// Move load for uncountable exit condition before other
// operations in the loop.
vecA = a[i]...a[i+VF-1];
// Create mask for all lanes _before_ any uncountable exit.
vecCmp = vecA == splat(threshold);
mask = get.active.lane.mask(0, cttz.elts(vecCmp));
// Execute statements with side effects using the mask
vecS1(mask);
vecS2(mask);
// If there was an uncountable exit, increase IV by the number
// of elements in the mask, and bail out to the scalar tail.
if (any_of(vecCmp)) {
i += cttz.elts(vecCmp);
break;
}
}
// Scalar tail handles remaining iterations, plus any differences
// in exit block for different exits.
for (; i < N; ++i) {
S1;
if (a[i] == threshold)
break;
S2;
}
```
For the mask, given a comparison result of `<0, 0, 1, 0>`, we would
expect a mask of `<1, 1, 0, 0>`.
Commit: fdf8fb6c13deb88c2e179a4eed0c66900dcd92d8
https://github.com/llvm/llvm-project/commit/fdf8fb6c13deb88c2e179a4eed0c66900dcd92d8
Author: Andre Kuhlenschmidt <andre.kuhlenschmidt at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/include/clang/Options/FlangOptions.td
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/docs/OpenACC-extensions.md
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Parser/openacc-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Support/Fortran-features.cpp
A flang/test/Lower/OpenACC/acc-module-definition-multi-name.f90
A flang/test/Lower/OpenACC/acc-routine-multi-name.f90
A flang/test/Parser/acc-routine-empty-parens.f90
M flang/test/Parser/acc-unparse.f90
A flang/test/Semantics/OpenACC/acc-routine-multi-name-disabled.f90
A flang/test/Semantics/OpenACC/acc-routine-multi-name.f90
Log Message:
-----------
[flang][openacc] add extension which accepts multiple names in a OpenACC routine directive (#200296)
This PR adds an extension which allows one or more function names in a
single named routine directive. This is treated as multiple named
routine directives with the same clauses. The bind clause is forbidden.
The empty list of names isn't excepted. Routine clauses are stable under
unparsing.
This PR tests Parsing, Unparsing, Semantics, and Lowering.
Commit: d307ba096e49c4503b50191d6e0ab2879942ffdd
https://github.com/llvm/llvm-project/commit/d307ba096e49c4503b50191d6e0ab2879942ffdd
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
[DAGCombiner] Remove untested vp_fma combines. (#201239)
RISC-V no longer uses vp_fma in SelectionDAG leaving these combines
untested.
This effectively reverts 2fe2a6d4b8a4647e49d69a5ff7161946aeb7cee1.
Commit: 05e8d9f86a1d29e32d92a04ff9f0371f25057f33
https://github.com/llvm/llvm-project/commit/05e8d9f86a1d29e32d92a04ff9f0371f25057f33
Author: Harald van Dijk <hdijk at accesssoftek.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/include/llvm/IR/AssemblyAnnotationWriter.h
M llvm/lib/IR/AsmWriter.cpp
Log Message:
-----------
[AsmWriter] Add emitMDNodeAnnot (#198317)
Similarly to the other AAW::emit*Annot functions, this may be used to
emit a comment before a metadata node.
Commit: 5816ef1560d13b7fd27e623e7f88f2e44cd11e21
https://github.com/llvm/llvm-project/commit/5816ef1560d13b7fd27e623e7f88f2e44cd11e21
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M cross-project-tests/debuginfo-tests/dexter/dex/debugger/DebuggerControllers/ScriptDebuggerController.py
A cross-project-tests/debuginfo-tests/dexter/dex/evaluation/ExpectMatch.py
A cross-project-tests/debuginfo-tests/dexter/dex/evaluation/Metrics.py
A cross-project-tests/debuginfo-tests/dexter/dex/evaluation/RunMatch.py
A cross-project-tests/debuginfo-tests/dexter/dex/evaluation/StateMatch.py
A cross-project-tests/debuginfo-tests/dexter/dex/evaluation/__init__.py
M cross-project-tests/debuginfo-tests/dexter/dex/test_script/__init__.py
M cross-project-tests/debuginfo-tests/dexter/dex/tools/test/Tool.py
A cross-project-tests/debuginfo-tests/dexter/feature_tests/scripts/evaluation/basic_evaluate.cpp
A cross-project-tests/debuginfo-tests/dexter/feature_tests/scripts/evaluation/evaluate_nothing.cpp
Log Message:
-----------
[Dexter] Add basic result evaluation for structured scripts (#198803)
This patch adds evaluation for structured scripts, completing the
features required to run simple Dexter tests using structured scripts.
The basic output from these evaluations is a list of named metrics
aggregating the results of evaluating !value nodes. The verbose output
gives a per-step summary of the results for each expect node active at
that step.
Most of the new functionality is in the evaluation/ dir, which has also
absorbed some functionality previously stored in the
ScriptDebuggerController for matching !where nodes to a debugger StepIR,
as this is logic which is common to both managing a debugger session and
evaluating the end result.
Commit: aa8e38f4f87189a5952c8471fb6cb7464f2b9d94
https://github.com/llvm/llvm-project/commit/aa8e38f4f87189a5952c8471fb6cb7464f2b9d94
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M openmp/module/CMakeLists.txt
Log Message:
-----------
[OpenMP] FIx omp_lib.mod compilation for the GPU (#201377)
Commit: 582d2fd3901f2f3b5ea9373471d87c5995a26a80
https://github.com/llvm/llvm-project/commit/582d2fd3901f2f3b5ea9373471d87c5995a26a80
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/test/Transforms/LoopInterchange/call-instructions.ll
M llvm/test/Transforms/LoopInterchange/function-attr.ll
Log Message:
-----------
[LoopInterchange] Bail out if function that may diverge is called (#201348)
This patch fixes the issue pointed out in
https://github.com/llvm/llvm-project/pull/200828#issuecomment-4593914293.
As demonstrated by the test cases added in #201331, it is not legal to
interchange loops that contain call instructions which may diverge. This
patch adds an additional check and bails out early when we cannot prove
that a call instruction in the loops doesn't diverge.
Commit: 8ae895af32cc2f7c506e39f5736e1115a8afb4ce
https://github.com/llvm/llvm-project/commit/8ae895af32cc2f7c506e39f5736e1115a8afb4ce
Author: Justin Lebar <justin.lebar at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
A llvm/test/CodeGen/NVPTX/atomicrmw-allow-ftz-atomics.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
M llvm/test/CodeGen/NVPTX/atomicrmw.py
M llvm/test/CodeGen/NVPTX/atomics.ll
Log Message:
-----------
[NVPTX] Respect FTZ flag when lowering atomicrmw fadd. (#200732)
Previously we unconditionally lowered LLVM atomicrmw fadd to PTX
atom.add. This is incorrect, because it ignores the FTZ behavior of the
LLVM and PTX instructions.
Commit: e97e67681d0d7de9c6ab8b293852068ea5591066
https://github.com/llvm/llvm-project/commit/e97e67681d0d7de9c6ab8b293852068ea5591066
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M lldb/test/API/macosx/expedited-thread-pcs/TestExpeditedThreadPCs.py
Log Message:
-----------
[lldb/test] Fix TestExpeditedThreadPCs on remote-darwin targets (#201275)
Commit: 12f60d0684a96e3858296c49db4c4cd275ae672f
https://github.com/llvm/llvm-project/commit/12f60d0684a96e3858296c49db4c4cd275ae672f
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
Log Message:
-----------
[AMDGPU] Remove unneeded early outs in getDivNumBits. NFC. (#201366)
Commit: 2d249cd753ca8f6d291d4fccdcfba3af3bd9c778
https://github.com/llvm/llvm-project/commit/2d249cd753ca8f6d291d4fccdcfba3af3bd9c778
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/docs/GettingInvolved.rst
Log Message:
-----------
Remove incorrect gcal link from C/C++ language wg (#201374)
The C and C++ language working group meets on the first and third Wed of
the month, but Google Calendar does not support doing this via a single
event. Instead, we have one event for recurring on the 1st Wed and a
second event for recurring on the 3rd Wed. That means we cannot use a
single gcal link for the event. Instead of listing two links, this
removes the gcal link entirely because the meeting is also listed on the
community calendar itself. This reduces confusion for folks, but it
would be nice to get a replacement link at some point.
Commit: 0cea23a93700e1a454369f617525f628df84a064
https://github.com/llvm/llvm-project/commit/0cea23a93700e1a454369f617525f628df84a064
Author: Harald van Dijk <hdijk at accesssoftek.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/test/Driver/hipspv-toolchain.hip
Log Message:
-----------
[HIP] Fix another test for --no-lto (#201382)
Commit: 0f4b1e11e64fdaaf6258043e1a30014b00bd04d3
https://github.com/llvm/llvm-project/commit/0f4b1e11e64fdaaf6258043e1a30014b00bd04d3
Author: Sushant Gokhale <sgokhale at nvidia.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
Log Message:
-----------
[AArch64] Address issue reported in PR#196029 (#199122)
For certain types of truncating stores, the lowering action is set to
custom although no custom lowering exists for them.
This patch addresses issue reported in PR #196029 by removing the custom lowering entry.
Commit: c6c2ad52586c28e74a724570985a48dc0022d250
https://github.com/llvm/llvm-project/commit/c6c2ad52586c28e74a724570985a48dc0022d250
Author: Aayush Shrivastava <iamaayushrivastava at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/bitfield-insert.ll
M llvm/test/CodeGen/AArch64/bswap-known-bits.ll
M llvm/test/CodeGen/AArch64/sshl_sat.ll
M llvm/test/CodeGen/AArch64/ushl_sat.ll
A llvm/test/CodeGen/X86/aext-and-trunc-avx512.ll
A llvm/test/CodeGen/X86/aext-and-trunc.ll
M llvm/test/CodeGen/X86/and-with-overflow.ll
M llvm/test/CodeGen/X86/combine-srem.ll
M llvm/test/CodeGen/X86/llvm.frexp.ll
M llvm/test/CodeGen/X86/masked_load.ll
M llvm/test/CodeGen/X86/masked_store.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-innerouter.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbits.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-lowhigh.ll
Log Message:
-----------
[DAG] Fold any-extend(and(trunc(x), C)) -> and(x, C) (#200052)
Fixes #195575
Fix a missed optimization in `DAGCombiner::visitANY_EXTEND` where the
pattern `any-extend(and(trunc(x), C))` was not being folded into `and(x,
C)` on X86, causing a redundant `movzbl` instruction to be emitted after
a small-mask AND.
Commit: 91edd87a801fc5c9d12c7f5c6863edd50327cef8
https://github.com/llvm/llvm-project/commit/91edd87a801fc5c9d12c7f5c6863edd50327cef8
Author: mike-goutokuji <gfunni234 at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/ucmp.ll
Log Message:
-----------
[Legalizer] Add support for promoting integers for s/ucmp (#198554)
Instead of manually doing promotion in LowerUCMP of platforms like
PowerPC, we should have this logic in the legalizer.
Commit: 678a6c7dbbb90b5cf856d487820c63aafa6de25b
https://github.com/llvm/llvm-project/commit/678a6c7dbbb90b5cf856d487820c63aafa6de25b
Author: Deric C. <cheung.deric at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
A llvm/test/CodeGen/DirectX/SampleGrad.ll
Log Message:
-----------
[DirectX] Implement lowering of SampleGrad. Refactor sample lowering functions (#200871)
Fixes #192549
This PR builds atop #199745 by adding a helper `lowerSampleOp` function
to refactor `lowerSampleBias` and implement `lowerSampleGrad`.
The `lowerSampleGrad` implementation is very similar to
`lowerSampleBias`, just with ddx and ddy arguments instead of a bias.
Unlike SampleBias, SampleGrad is usable in all shader stages because it
has explicit gradient/derivative arguments.
Assisted-by: GitHub Copilot
Commit: 06ac45db1597049c0e4f04c334bf78cd362b75ee
https://github.com/llvm/llvm-project/commit/06ac45db1597049c0e4f04c334bf78cd362b75ee
Author: Ilpo Ruotsalainen <lonewolf at iki.fi>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
A llvm/test/CodeGen/X86/GlobalISel/calllowering-inalloca.ll
Log Message:
-----------
[GISel][CallLowering] Set byval flag for inalloca/preallocated args (#200600)
GlobalISel asserts when lowering a function with an `inalloca` or
`preallocated` argument:
> TargetCallingConv.h:183: void
llvm::ISD::ArgFlagsTy::setByValSize(unsigned): Assertion `isByVal() &&
!isByRef()' failed.
https://godbolt.org/z/jWr4enjaj
`addFlagsFromAttrSet()` sets the `InAlloca`/`Preallocated` flags but
never `ByVal`.
`setArgFlags()` then calls `Flags.setByValSize()` for any non-`ByRef`
indirect argument which asserts `isByVal()`.
`SelectionDAGISel::LowerArguments()` avoids this by deliberately also
setting the `ByVal` flag for `inalloca`/`preallocated`, this change
makes the GlobalISel side match that behavior.
Commit: 15375d84799ec260d101aa35670f61fa456b6a4e
https://github.com/llvm/llvm-project/commit/15375d84799ec260d101aa35670f61fa456b6a4e
Author: Andre Kuhlenschmidt <andre.kuhlenschmidt at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/include/clang/Options/FlangOptions.td
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/docs/OpenACC-extensions.md
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Support/Fortran-features.cpp
A flang/test/Semantics/OpenACC/acc-default-none-scalars-strict.f90
M flang/test/Semantics/OpenACC/acc-default-none-scalars.f90
Log Message:
-----------
[flang][openacc] change option feature flag names to address comments. (#200037)
- Fixes FeatureFlags and CLI flags to use OpenACC instead of ACC.
- Offline comments further refined the name to be
OpenACCDefaultNoneScalarsStrict
- Which changes the semantics requiring the user to opt out of the
default behavior, instead of opt-in to an extension.
- Also makes the CLI flag OptOut instead of OptIn to match the cli
behavior.
- Gets rid of the unneeded warning flag since FeatureFlags have both a
disabled bit and a warning bit.
- Updates old test for these changes and adds a new test to document all
the different cli configurations.
Commit: cd75a7db92289d9784b471b27cd72cb50a2352fd
https://github.com/llvm/llvm-project/commit/cd75a7db92289d9784b471b27cd72cb50a2352fd
Author: Jan Schultke <me at eisenwave.net>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/clmul.ll
Log Message:
-----------
[SelectionDAG] Fix missed optimization for CLMUL where one operand is all ones (#200592)
Fixes #200556
This special case is equivalent to a "parallel prefix XOR" or "bitwise
parity" operation, which can be expanded to a logarithmic amount of
bitwise operations instead of a linear amount (relative to the bit
width). When other bitwise operations such as BDEP and BEXT are
expanded, they rely on that operation being lowered to a CLMUL directly
or expanded to this efficient form.
See also
- #200570 (this PR needs this fix to have good codegen)
Commit: cf9bf34e29e67fae3562705cfaffb71c7846e8c8
https://github.com/llvm/llvm-project/commit/cf9bf34e29e67fae3562705cfaffb71c7846e8c8
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.cpp
M llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
M llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll
Log Message:
-----------
[AMDGPU] Fix backward compatibility kernarg preload prolog base offset (#201355)
Backward compatibility preload prolog loaded args from kernarg-segment
byte 0, but on non-AMDHSA triples the explicit args start at
`getExplicitKernelArgOffset()` (value: 36), so preloaded SGPRs held the
runtime header instead of the arguments
Commit: ee10231219016efcc51a23bb74dc541dcba3aaf6
https://github.com/llvm/llvm-project/commit/ee10231219016efcc51a23bb74dc541dcba3aaf6
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M libc/include/llvm-libc-macros/_LIBC_MODULAR_FORMAT_PRINTF-disable.h
M libc/include/llvm-libc-macros/_LIBC_MODULAR_FORMAT_PRINTF.h
M libc/include/stdio.yaml
Log Message:
-----------
[libc] Add explicit format attributes for modular printf (#201212)
We had been relying on compiler-generated format attributes when using
the modular_format attribute for printf-family functions, but this is
not applied in -ffreestanding mode. When modular format is enabled, libc
is explicitly asserting the semantics of these functions, so it should
be explicit about the format attributes as well to keep them from
breaking in -ffreestanding.
Generated by Gemini, reviewed and edited by hand.
Commit: 3a1420effe06748cb9bd1b2ef746bd5be25fad52
https://github.com/llvm/llvm-project/commit/3a1420effe06748cb9bd1b2ef746bd5be25fad52
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
A clang/cmake/caches/generic-allow-shared-imports.cmake
A clang/cmake/caches/hexagon-unknown-linux-musl-clang-cross-dist.cmake
A clang/cmake/caches/hexagon-unknown-linux-musl-clang-defaults-dist.cmake
A clang/cmake/caches/hexagon-unknown-linux-musl-clang-dist.cmake
A clang/cmake/caches/hexagon-unknown-linux-musl-clang-dylib-dist.cmake
Log Message:
-----------
[Hexagon] Add cmake caches for cross-toolchain distribution build (#201207)
Adds and extends the
clang/cmake/caches/hexagon-unknown-linux-musl-clang* files to drive a
full install-distribution build: host tools, per-target builtins (Linux
and baremetal), and runtimes for hexagon-unknown-linux-musl.
Commit: f080619e96dfc661fd0f4c0f51a7cc2457d298b9
https://github.com/llvm/llvm-project/commit/f080619e96dfc661fd0f4c0f51a7cc2457d298b9
Author: Martin Erhart <martin.erhart at sifive.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M mlir/include/mlir/Bindings/Python/IRCore.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/test/python/ir/location.py
Log Message:
-----------
[mlir][Python] Downcast location returned from diagnostic (#201337)
Essentially a follow up to
https://github.com/llvm/llvm-project/pull/192630
Commit: 0b109532693fec0dce3a8d275b716f5a5fb6e45c
https://github.com/llvm/llvm-project/commit/0b109532693fec0dce3a8d275b716f5a5fb6e45c
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M lldb/CMakeLists.txt
M lldb/source/Host/common/PythonRuntimeLoader.cpp
Log Message:
-----------
[lldb][windows] explicitly load python3.dll in PythonRuntimeLoader (#201399)
When building with the Python stable API, `liblldb.dll`'s delay-load
crashes because it needs `python3.dll` and it can't find it
Loading `python310.dll` via `LoadLibrary` with a full path doesn't add
Python's directory to the DLL search path for subsequent loads.
This patch also explicitly loads `python3.dll` from the same directory
in `PythonRuntimeLoader` to fix the issue.
This is needed for https://github.com/llvm/llvm-project/pull/200533.
Commit: 7954dcc70ef251581f95582beb7929e286ec9fe9
https://github.com/llvm/llvm-project/commit/7954dcc70ef251581f95582beb7929e286ec9fe9
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Transforms/IPO/HotColdSplitting.cpp
M llvm/test/Transforms/CodeExtractor/input-value-debug.ll
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs.ll.generated.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs.ll.nogenerated.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs_prefix_reuse.ll.generated.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs_prefix_reuse.ll.nogenerated.globals.expected
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[HotColdSplit] Unconditionally mark new functions as cold (#200947)
Previously, HotColdSplit would only mark functions as cold if there was
a profile summary available in the module metadata. This was causing
profcheck failures and is inconsistent with how we handle profile
metadata in other parts of the compiler.
This behavior has been around since
c36c10ddfb3dc07129b9f3973029d17940f6a45f when the profile annotation was
first introduced.
Commit: 7e45473cc229baff6c2a8d2130b58035f4f70e41
https://github.com/llvm/llvm-project/commit/7e45473cc229baff6c2a8d2130b58035f4f70e41
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/lldb/include/lldb/Host/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Host/BUILD.gn
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/DTLTO/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port commits (#201400)
142ad481b625
87d6941017aa
c264e07c2f3d
f91f589aaa82
Commit: 28b12c6317568c8d31a701a35d1c59366030e054
https://github.com/llvm/llvm-project/commit/28b12c6317568c8d31a701a35d1c59366030e054
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/tools/llvm-lto2/BUILD.gn
Log Message:
-----------
[gn build] Add missing dep (#201414)
Commit: 102d8583355c316618648de7d8537299f4357f95
https://github.com/llvm/llvm-project/commit/102d8583355c316618648de7d8537299f4357f95
Author: Jan Schultke <me at eisenwave.net>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/test/CodeGen/X86/clmul.ll
Log Message:
-----------
Regenerate X86/clmul.ll expectations (#201405)
Fixes a build failure on trunk after merging:
- #200592
See
https://github.com/llvm/llvm-project/pull/200592#issuecomment-4614719422
Commit: 3f67f166d6580970a9f4d50bdf7827c510d884d3
https://github.com/llvm/llvm-project/commit/3f67f166d6580970a9f4d50bdf7827c510d884d3
Author: Philipp Rados <philipp.rados at openchip.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
A llvm/test/CodeGen/RISCV/stack-offset-large.ll
Log Message:
-----------
[RISCV] Allow 64-bit fixed frame-offsets on RV64 (#201338)
Some HPC code requires a _very_ large stack. GCC also allows 64-bit
frame-offsets on 64-bit systems.
Since RISCVInstrInfo::movImm() supports materializing 64-bit immediates
the existing framework already handles the lowering correctly.
This patch only enables support for 64-bit _fixed_ frame offsets.
Scalable offsets call RISCVInstrInfo::mulImm() which doesn't seem to
support 64-bit calculations yet. This should be fine since there'd have
to be more than 2^31 RVV spills for this case to happen.
Commit: 1c88bd716167a0650513319176c30dd715101a70
https://github.com/llvm/llvm-project/commit/1c88bd716167a0650513319176c30dd715101a70
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M lldb/include/lldb/Host/MainLoopBase.h
M lldb/source/Host/common/MainLoopBase.cpp
Log Message:
-----------
[lldb] Preserve FIFO order for equal time MainLoop callbacks (#199056)
Co-authored-by: Adrian Prantl <adrian.prantl at gmail.com>
Commit: 6cfa1a01a0f737ed1d54963810057fb1bd67a274
https://github.com/llvm/llvm-project/commit/6cfa1a01a0f737ed1d54963810057fb1bd67a274
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/lib/CodeGen/CGCUDANV.cpp
R clang/test/CodeGenHIP/offload-pgo-sections.hip
M compiler-rt/CMakeLists.txt
M compiler-rt/lib/profile/CMakeLists.txt
M compiler-rt/lib/profile/InstrProfilingFile.c
R compiler-rt/lib/profile/InstrProfilingPlatformROCm.cpp
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
R llvm/test/Instrumentation/InstrProfiling/amdgpu-instrumentation.ll
R llvm/test/Instrumentation/InstrProfiling/amdgpu-profc-arrays.ll
R llvm/test/Instrumentation/InstrProfiling/gpu-weak.ll
R llvm/test/Transforms/PGOProfile/amdgpu-disable-value-profiling.ll
Log Message:
-----------
Revert "[PGO][AMDGPU] Add basic HIP offload PGO support (#177665)" (#201416)
This broke profiling builds on Windows by switching the profile library
to link against the dynamic CRT; see discussion on the PR.
There were already a number of issues reported and fixed after this PR.
Rather than piling on the fixes (and this one may need some work),
revert back to green for now to let the project recover.
This reverts commit 5db13643f4b7038db0ca304d9f8900122502935c.
Additionally, this reverts the followup PRs in
635e120fb87304924508a7a204574727e3c37363,
2766733764f4bdf8399d48c0225e9c64bdfa95f7,
4c33844b4b560f24b2a3a0cc689d73510cb01ad5, and
5eca8b67ff3c5f371141d54b6e4544a0ebe77fdb:
"[PGO][HIP] Stop pulling ROCm.o into every PGO host link (#200101)"
"[compiler-rt][profile] Add COMPILER_RT_BUILD_PROFILE_ROCM option
(#200127)"
"[PGO][HIP] Skip ROCm interceptor in profile-only compiler-rt builds
(#200111)"
"[PGO][HIP] Fix profile-only Windows link by gating ROCm interceptor
macro (#200859)"
Commit: 09020f9d68e4a0a8f93d2e7f4875ef58f451f948
https://github.com/llvm/llvm-project/commit/09020f9d68e4a0a8f93d2e7f4875ef58f451f948
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for llvm.amdgcn.frexp.exp (#201178)
Commit: e43adaea1fb557e860fbb34568ac024fd649cf5c
https://github.com/llvm/llvm-project/commit/e43adaea1fb557e860fbb34568ac024fd649cf5c
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
A lldb/docs/python_api.md
R lldb/docs/python_api.rst
A lldb/docs/python_extensions.md
R lldb/docs/python_extensions.rst
A lldb/docs/resources/caveats.md
R lldb/docs/resources/caveats.rst
A lldb/docs/resources/contributing.md
R lldb/docs/resources/contributing.rst
A lldb/docs/resources/fuzzing.md
R lldb/docs/resources/fuzzing.rst
A lldb/docs/use/links.md
R lldb/docs/use/links.rst
A lldb/docs/use/ondemand.md
R lldb/docs/use/ondemand.rst
A lldb/docs/use/python-reference.md
R lldb/docs/use/python-reference.rst
A lldb/docs/use/repeat-commands.md
R lldb/docs/use/repeat-commands.rst
Log Message:
-----------
[lldb][docs] Convert simple RST pages to Markdown (NFC) (#201256)
Convert nine short, low-risk RST docs to MyST Markdown as the first
batch of an incremental RST -> Markdown migration. Subsequent batches
will cover the rest.
Verified by building the docs on origin/main and on this branch with
identical sphinx flags and diffing the rendered HTML. Seven of nine
pages are byte-identical.
contributing.html differs in 42 lines, all attributable to `{doc}` xrefs
replacing RST hyperlinks to sibling pages (`reference external` ->
`reference internal`) and CommonMark collapsing two-spaces-after- period
to one.
ondemand.html differs in 26 lines because two bulleted lists that
followed a paragraph with no blank-line separator originally rendered as
literal `- ...` text in both RST and Markdown. The conversion tool
preserved that by emitting `\-`; this patch instead inserts a blank line
so they render as proper `<ul>` lists, fixing a latent doc bug.
Context:
https://discourse.llvm.org/t/rfc-make-myst-markdown-the-llvm-docs-format-rip-rest/
Assisted-by: Claude
Commit: 47209321457b4302ac0d2cb668cdd3f3caff9134
https://github.com/llvm/llvm-project/commit/47209321457b4302ac0d2cb668cdd3f3caff9134
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCComputeLowering.cpp
A mlir/test/Dialect/OpenACC/acc-compute-lowering-compute-device-type.mlir
A mlir/test/Dialect/OpenACC/acc-compute-lowering-loop-device-type.mlir
Log Message:
-----------
[mlir][acc] ACCComputeLowering needs to account for device_type par (#201267)
When assigning parallelism for compute constructs or loops, device_type
parallelism must be first considered as a group for all available (gang,
worker, vector) - if any of these have device_type setting, then those
are the only ones that should be considered. Only if the loop has no
device_type specific parallelism then default parallelism should be
assigned.
Commit: 91b00526a599fa21e43da82438f1e9c8a8e1b7b3
https://github.com/llvm/llvm-project/commit/91b00526a599fa21e43da82438f1e9c8a8e1b7b3
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/IR/BasicBlock.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
A llvm/test/Bitcode/musttail-bitcast-upgrade.ll
A llvm/test/Bitcode/musttail-bitcast-upgrade.ll.bc
M llvm/test/Instrumentation/AddressSanitizer/musttail.ll
M llvm/test/Instrumentation/ThreadSanitizer/tsan_musttail.ll
M llvm/test/Transforms/CallSiteSplitting/musttail.ll
M llvm/test/Transforms/SafeStack/X86/musttail.ll
M llvm/test/Verifier/musttail-invalid.ll
Log Message:
-----------
Remove the optional bitcast between a musttail call and its ret (#201280)
Under opaque pointers the only bitcast the verifier could accept in this
position is a no-op ptr->ptr cast
Drop it and reduce isTypeCongruent to a plain type equality check
Commit: 420b8b3cede41894dc5dac29f8e64bcff13e3620
https://github.com/llvm/llvm-project/commit/420b8b3cede41894dc5dac29f8e64bcff13e3620
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M llvm/tools/llvm-exegesis/lib/LlvmState.cpp
M llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
M llvm/tools/llvm-exegesis/lib/MCInstrDescView.h
M llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp
Log Message:
-----------
[llvm-exegesis] Support LookupRegClassByHwMode in exegesis Instruction::create
This resolves the TODO for LookupRegClassByHwMode support in llvm-exegesis by
passing the MCSubtargetInfo to Instruction::create and calling
getOpRegClassID with the active HwMode.
This also updates MemoryUse test expectations for Mips, as the target now
correctly resolve HwMode-dependent memory register operands (MSA128F16 in
Mips and post-#177073 BasePtrRegClass for RISC-V).
Pull Request: https://github.com/llvm/llvm-project/pull/200525
Commit: 4169b17acfe53c79e0e170ebb8249ef749e061a2
https://github.com/llvm/llvm-project/commit/4169b17acfe53c79e0e170ebb8249ef749e061a2
Author: adams381 <adams at nvidia.com>
Date: 2026-06-03 (Wed, 03 Jun 2026)
Changed paths:
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
Log Message:
-----------
[CIR][NFC] Remove unused DataLayout in array lowering (#201408)
The per-element loop in CIRAttrToValue::visitCirAttr(ConstArrayAttr) constructed an mlir::DataLayout for every element of an ArrayAttr-backed constant array and never used it. Constructing a DataLayout walks the parent ops to gather the layout spec, so for an N-element array this was N redundant constructions on the lowering path. Removing the dead local is NFC -- the generated IR is unchanged.
Split out of #198427, where it was flagged as an unrelated drive-by.
Commit: 5c4e85a35bdad0c41eb3802ed3fd9e636ba7c935
https://github.com/llvm/llvm-project/commit/5c4e85a35bdad0c41eb3802ed3fd9e636ba7c935
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-06-04 (Thu, 04 Jun 2026)
Changed paths:
M .ci/green-dragon/lldb-windows.groovy
A bolt/docs/BOLTAArch64OptimizationStatus.rst
M bolt/include/bolt/Core/BinaryContext.h
M bolt/include/bolt/Core/DIEBuilder.h
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Core/DIEBuilder.cpp
M bolt/lib/Passes/VeneerElimination.cpp
M bolt/lib/Rewrite/DWARFRewriter.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
A bolt/test/AArch64/veneer-erratum-843419.s
M bolt/test/X86/dwarf5-df-types-dup-dwp-input.test
A bolt/test/X86/dwarf5-dwp-tsan-data-race.test
M clang-tools-extra/clang-tidy/fuchsia/StaticallyConstructedObjectsCheck.cpp
M clang-tools-extra/clang-tidy/misc/CMakeLists.txt
M clang-tools-extra/clang-tidy/misc/ConfusableTable/CMakeLists.txt
M clang-tools-extra/clang-tidy/misc/DefinitionsInHeadersCheck.cpp
M clang-tools-extra/clang-tidy/readability/NonConstParameterCheck.cpp
M clang-tools-extra/clangd/InlayHints.cpp
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/index/StdLib.cpp
M clang-tools-extra/clangd/index/SymbolCollector.cpp
M clang-tools-extra/clangd/refactor/tweaks/DefineInline.cpp
M clang-tools-extra/clangd/unittests/CMakeLists.txt
M clang-tools-extra/clangd/unittests/InlayHintTests.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/conf.py
M clang-tools-extra/test/clang-tidy/checkers/fuchsia/statically-constructed-objects.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/non-const-parameter.cpp
M clang/CMakeLists.txt
A clang/cmake/caches/generic-allow-shared-imports.cmake
A clang/cmake/caches/hexagon-unknown-linux-musl-clang-cross-dist.cmake
A clang/cmake/caches/hexagon-unknown-linux-musl-clang-defaults-dist.cmake
A clang/cmake/caches/hexagon-unknown-linux-musl-clang-dist.cmake
A clang/cmake/caches/hexagon-unknown-linux-musl-clang-dylib-dist.cmake
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/JSONNodeDumper.h
A clang/include/clang/AST/MatrixUtils.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/ASTMatchers/ASTMatchersInternal.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/DarwinSDKInfo.h
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/include/clang/Basic/DiagnosticIDs.h
M clang/include/clang/Basic/FileManager.h
R clang/include/clang/Basic/FileSystemStatCache.h
M clang/include/clang/Basic/LangOptions.h
M clang/include/clang/Basic/Specifiers.h
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/clang/Basic/arm_neon.td
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Basic/arm_sve_sme_incl.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Driver/CommonArgs.h
M clang/include/clang/Driver/Driver.h
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Options/FlangOptions.td
M clang/include/clang/Options/Options.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTDumper.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/Comment.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/RecordLayoutBuilder.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/ASTMatchers/Dynamic/Registry.cpp
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
M clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp
M clang/lib/Basic/CMakeLists.txt
M clang/lib/Basic/DarwinSDKInfo.cpp
M clang/lib/Basic/FileManager.cpp
R clang/lib/Basic/FileSystemStatCache.cpp
M clang/lib/Basic/TargetInfo.cpp
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/OSTargets.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenCleanup.cpp
M clang/lib/CIR/CodeGen/CIRGenConstantEmitter.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/ABIInfoImpl.cpp
M clang/lib/CodeGen/CGAtomic.cpp
M clang/lib/CodeGen/CGBlocks.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCUDANV.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGClass.cpp
M clang/lib/CodeGen/CGDecl.cpp
M clang/lib/CodeGen/CGException.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprAgg.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenTypes.cpp
M clang/lib/CodeGen/MicrosoftCXXABI.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/CodeGen/TargetBuiltins/X86.cpp
M clang/lib/CodeGen/TargetInfo.h
M clang/lib/CodeGen/Targets/ARM.cpp
M clang/lib/CodeGen/Targets/SystemZ.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/AIX.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/AVR.cpp
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Darwin.h
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Driver/ToolChains/Fuchsia.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Driver/ToolChains/Haiku.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/Driver/ToolChains/OpenBSD.cpp
M clang/lib/Driver/ToolChains/PS4CPU.cpp
M clang/lib/Driver/ToolChains/SPIRV.cpp
M clang/lib/Driver/ToolChains/Serenity.cpp
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/lib/Index/IndexingContext.cpp
M clang/lib/InstallAPI/Visitor.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp
M clang/lib/Tooling/Syntax/BuildTree.cpp
M clang/lib/Tooling/Tooling.cpp
M clang/test/AST/ByteCode/records.cpp
M clang/test/AST/HLSL/matrix_layout_attr.hlsl
M clang/test/AST/ast-dump-templates-pattern.cpp
A clang/test/CIR/CodeGen/compound_literal.c
A clang/test/CIR/CodeGen/func-linkage-weak-import.c
A clang/test/CIR/CodeGen/global-temp-dtor.cpp
A clang/test/CIR/CodeGen/inline-forward-decl.c
M clang/test/CIR/CodeGen/self-ref-temporaries.cpp
A clang/test/CIR/CodeGen/switch-cleanup.cpp
M clang/test/CIR/CodeGenCXX/global-refs.cpp
M clang/test/CIR/IR/invalid-cast.cir
M clang/test/CIR/Lowering/cast.cir
A clang/test/CIR/Transforms/abi-lowering/coerce-int-to-record.cir
A clang/test/CIR/Transforms/abi-lowering/coerce-record-return-larger.cir
A clang/test/CIR/Transforms/abi-lowering/coerce-record-to-int.cir
A clang/test/CIR/Transforms/abi-lowering/coerce-record-to-record-via-memory.cir
A clang/test/CIR/Transforms/abi-lowering/coerce-vector-to-complex.cir
M clang/test/CXX/basic/basic.link/p11.cpp
M clang/test/CXX/temp/temp.arg/temp.arg.template/p3-2a.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.decl/p4.cpp
M clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp
M clang/test/CXX/temp/temp.spec/temp.expl.spec/p7.cpp
A clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c
M clang/test/CodeGen/AArch64/neon-2velem.c
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c
M clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c
M clang/test/CodeGen/AArch64/neon/fused-multiply.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2_fp_int_cvtn_x2.c
A clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2_int_fp_cvt.c
M clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c
M clang/test/CodeGen/RISCV/riscv-cf-protection.c
A clang/test/CodeGen/SystemZ/zos-abi.c
A clang/test/CodeGen/SystemZ/zos-abi.cpp
M clang/test/CodeGen/cfi-icall-trap-recover-runtime.c
M clang/test/CodeGen/lto-newpm-pipeline.c
M clang/test/CodeGen/scoped-atomic-ops.c
M clang/test/CodeGen/target-data.c
M clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
M clang/test/CodeGenCUDA/atomic-options.hip
M clang/test/CodeGenCUDA/builtins-amdgcn.cu
M clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
M clang/test/CodeGenCUDA/record-layout.cu
M clang/test/CodeGenCXX/amdgcn-func-arg.cpp
M clang/test/CodeGenCXX/cfi-vcall-trap-recover-runtime.cpp
R clang/test/CodeGenHIP/offload-pgo-sections.hip
M clang/test/CodeGenHIP/placement-new-addrspace.hip
A clang/test/CodeGenHLSL/matrix-layout-attr-overrides-default.hlsl
M clang/test/CodeGenOpenCL/addr-space-struct-arg.cl
M clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl
M clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl
M clang/test/CodeGenOpenCL/atomic-ops.cl
M clang/test/CodeGenSYCL/kernel-caller-entry-point.cpp
M clang/test/Driver/hip-toolchain-no-rdc.hip
M clang/test/Driver/hipspv-toolchain.hip
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Frontend/spirv-target-validation.c
A clang/test/Modules/pr195905.cppm
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper-hip-no-rdc.c
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper-image.c
M clang/test/OffloadTools/clang-sycl-linker/basic.ll
M clang/test/OffloadTools/clang-sycl-linker/split-mode.ll
M clang/test/OffloadTools/clang-sycl-linker/triple.ll
M clang/test/OpenMP/amdgcn_target_device_vla.cpp
M clang/test/OpenMP/amdgpu_target_with_aligned_attribute.c
M clang/test/OpenMP/target_teams_generic_loop_codegen.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen_as_distribute.cpp
M clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp
M clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_LP_sve2p3_OR_sme2p3_RP___sme_AND_LP_sve2p3_OR_sme2p3_RP.c
M clang/test/Sema/aarch64-neon-immediate-ranges/dotprod.c
M clang/test/Sema/constexpr.c
M clang/test/SemaCUDA/addr-of-overloaded-fn.cu
A clang/test/SemaCUDA/addr-of-overloaded-template-fn.cu
M clang/test/SemaHLSL/BuiltIns/logical-mat-operator-errors.hlsl
M clang/test/SemaHLSL/MatrixElementOverloadResolution.hlsl
M clang/test/SemaHLSL/Types/BuiltinMatrix/MatrixImplicitTruncCastWarnings.hlsl
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/test/SemaTemplate/friend-template.cpp
M clang/test/SemaTemplate/instantiate-scope.cpp
M clang/test/Templight/templight-default-func-arg.cpp
M clang/test/Templight/templight-empty-entries-fix.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
M clang/tools/libclang/CIndex.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
M clang/unittests/Analysis/LifetimeSafetyTest.cpp
M clang/unittests/Basic/DarwinSDKInfoTest.cpp
M clang/unittests/Basic/FileManagerTest.cpp
M clang/utils/TableGen/SveEmitter.cpp
M clang/utils/perf-training/lit.site.cfg.in
M compiler-rt/CMakeLists.txt
M compiler-rt/lib/asan/asan_interceptors.cpp
M compiler-rt/lib/profile/CMakeLists.txt
M compiler-rt/lib/profile/InstrProfilingFile.c
R compiler-rt/lib/profile/InstrProfilingPlatformROCm.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_common.h
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_mac.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_win.cpp
M compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
M cross-project-tests/debuginfo-tests/dexter/dex/debugger/DebuggerControllers/DebuggerControllerBase.py
A cross-project-tests/debuginfo-tests/dexter/dex/debugger/DebuggerControllers/ScriptDebuggerController.py
M cross-project-tests/debuginfo-tests/dexter/dex/dextIR/DextIR.py
M cross-project-tests/debuginfo-tests/dexter/dex/dextIR/LocIR.py
M cross-project-tests/debuginfo-tests/dexter/dex/dextIR/StepIR.py
A cross-project-tests/debuginfo-tests/dexter/dex/evaluation/ExpectMatch.py
A cross-project-tests/debuginfo-tests/dexter/dex/evaluation/Metrics.py
A cross-project-tests/debuginfo-tests/dexter/dex/evaluation/RunMatch.py
A cross-project-tests/debuginfo-tests/dexter/dex/evaluation/StateMatch.py
A cross-project-tests/debuginfo-tests/dexter/dex/evaluation/__init__.py
M cross-project-tests/debuginfo-tests/dexter/dex/test_script/__init__.py
M cross-project-tests/debuginfo-tests/dexter/dex/tools/test/Tool.py
A cross-project-tests/debuginfo-tests/dexter/feature_tests/scripts/debugging/Inputs/header.h
A cross-project-tests/debuginfo-tests/dexter/feature_tests/scripts/debugging/simple_where_function.cpp
A cross-project-tests/debuginfo-tests/dexter/feature_tests/scripts/debugging/simple_where_line.cpp
A cross-project-tests/debuginfo-tests/dexter/feature_tests/scripts/debugging/where_file_paths.cpp
A cross-project-tests/debuginfo-tests/dexter/feature_tests/scripts/evaluation/basic_evaluate.cpp
A cross-project-tests/debuginfo-tests/dexter/feature_tests/scripts/evaluation/evaluate_nothing.cpp
M cross-project-tests/dtlto/dtlto-cache.test
M cross-project-tests/dtlto/savetemps-lock.test
M flang-rt/CMakeLists.txt
M flang-rt/lib/runtime/io-api-server.cpp
M flang-rt/test/CMakeLists.txt
M flang/docs/OpenACC-extensions.md
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.cpp
M flang/include/flang/Frontend/CodeGenOptions.def
M flang/include/flang/Optimizer/HLFIR/Passes.td
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/openmp-utils.h
M flang/include/flang/Semantics/symbol.h
M flang/include/flang/Support/Fortran-features.h
M flang/include/flang/Support/Fortran.h
M flang/lib/Frontend/CompilerInstance.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenMP/Atomic.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/lib/Optimizer/HLFIR/Transforms/CMakeLists.txt
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
A flang/lib/Optimizer/HLFIR/Transforms/SeparateAllocatableAssign.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Parser/openacc-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/CMakeLists.txt
M flang/lib/Semantics/check-acc-structure.cpp
R flang/lib/Semantics/check-omp-metadirective.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
A flang/lib/Semantics/check-omp-variant.cpp
M flang/lib/Semantics/mod-file.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/symbol.cpp
M flang/lib/Support/Fortran-features.cpp
A flang/test/Driver/function-sections.f90
M flang/test/Driver/include-omp-header.f90
M flang/test/Driver/mlir-debug-pass-pipeline.f90
M flang/test/Driver/mlir-pass-pipeline.f90
M flang/test/Fir/basic-program.fir
A flang/test/HLFIR/opt-bufferization-dealloc-conflict.fir
M flang/test/HLFIR/opt-bufferization-eval_in_mem.fir
A flang/test/HLFIR/separate-allocatable-assign.fir
M flang/test/Integration/OpenMP/workshare-axpy.f90
A flang/test/Integration/function-sections.f90
A flang/test/Lower/OpenACC/acc-module-definition-multi-name.f90
A flang/test/Lower/OpenACC/acc-routine-multi-name.f90
R flang/test/Lower/OpenMP/Todo/begin-metadirective.f90
A flang/test/Lower/OpenMP/Todo/metadirective-declarative.f90
A flang/test/Lower/OpenMP/Todo/metadirective-dynamic.f90
R flang/test/Lower/OpenMP/Todo/metadirective-exec.f90
A flang/test/Lower/OpenMP/Todo/metadirective-loop.f90
R flang/test/Lower/OpenMP/Todo/metadirective-spec.f90
A flang/test/Lower/OpenMP/Todo/metadirective-structured-trait-property.f90
A flang/test/Lower/OpenMP/Todo/metadirective-target-device.f90
A flang/test/Lower/OpenMP/metadirective-construct.f90
A flang/test/Lower/OpenMP/metadirective-device-arch.f90
A flang/test/Lower/OpenMP/metadirective-device-isa.f90
A flang/test/Lower/OpenMP/metadirective-device-kind.f90
A flang/test/Lower/OpenMP/metadirective-implementation.f90
A flang/test/Lower/OpenMP/metadirective-nothing.f90
A flang/test/Lower/OpenMP/metadirective-user.f90
A flang/test/Lower/intrinsic-module-array-constant.f90
M flang/test/Parser/OpenMP/declare_target-device_type.f90
M flang/test/Parser/OpenMP/groupprivate.f90
A flang/test/Parser/acc-routine-empty-parens.f90
M flang/test/Parser/acc-unparse.f90
A flang/test/Semantics/OpenACC/acc-default-none-scalars-strict.f90
M flang/test/Semantics/OpenACC/acc-default-none-scalars.f90
A flang/test/Semantics/OpenACC/acc-routine-multi-name-disabled.f90
A flang/test/Semantics/OpenACC/acc-routine-multi-name.f90
A flang/test/Semantics/OpenMP/declare-target-flags.f90
A flang/test/Semantics/OpenMP/declare-target-modfile.f90
A flang/test/Semantics/OpenMP/declare-variant-match.f90
M flang/test/Semantics/OpenMP/declare-variant.f90
M flang/test/Semantics/OpenMP/dump-requires-details.f90
M flang/test/Semantics/OpenMP/metadirective-common.f90
M flang/test/Semantics/OpenMP/requires-modfile.f90
M flang/test/lit.cfg.py
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/riscv/headers.txt
M libc/config/linux/x86_64/headers.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/struct_in6_addr.h
M libc/include/CMakeLists.txt
M libc/include/arpa/inet.yaml
M libc/include/limits.yaml
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/_LIBC_MODULAR_FORMAT_PRINTF-disable.h
M libc/include/llvm-libc-macros/_LIBC_MODULAR_FORMAT_PRINTF.h
A libc/include/llvm-libc-macros/inet-address-macros.h
M libc/include/llvm-libc-macros/limits-macros.h
M libc/include/llvm-libc-macros/linux/unistd-macros.h
M libc/include/llvm-libc-macros/netinet-in-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/struct_in6_addr.h
A libc/include/llvm-libc-types/u_char.h
A libc/include/llvm-libc-types/u_int32_t.h
A libc/include/llvm-libc-types/uint.h
M libc/include/netinet/in.yaml
M libc/include/stdio.yaml
M libc/include/sys/types.yaml
M libc/include/unistd.yaml
M libc/src/__support/FPUtil/bfloat16.h
M libc/src/__support/File/linux/CMakeLists.txt
M libc/src/__support/File/linux/dir.cpp
M libc/src/__support/File/linux/file.cpp
M libc/src/__support/OSUtil/linux/CMakeLists.txt
M libc/src/__support/OSUtil/linux/auxv.h
M libc/src/__support/block.h
M libc/src/__support/freelist_heap.h
M libc/src/__support/freestore.h
M libc/src/__support/threads/linux/CMakeLists.txt
M libc/src/__support/threads/linux/thread.cpp
M libc/src/fcntl/linux/CMakeLists.txt
M libc/src/fcntl/linux/creat.cpp
M libc/src/spawn/linux/CMakeLists.txt
M libc/src/spawn/linux/posix_spawn.cpp
M libc/src/unistd/linux/alarm.cpp
M libc/src/unistd/linux/sysconf.cpp
M libc/test/include/CMakeLists.txt
A libc/test/include/unistd_macros_test.cpp
M libc/test/src/__support/CMakeLists.txt
M libc/test/src/__support/CPP/limits_test.cpp
M libc/test/src/__support/FPUtil/bfloat16_test.cpp
M libc/test/src/__support/block_test.cpp
M libc/test/src/__support/freelist_heap_test.cpp
M libc/test/src/netinet/CMakeLists.txt
A libc/test/src/netinet/in_test.cpp
M libc/test/src/unistd/sysconf_test.cpp
M libc/utils/docgen/arpa/inet.yaml
M libclc/CMakeLists.txt
M libclc/README.md
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/__iterator/erase_if_container.h
M libcxx/include/__locale
M libcxx/include/__locale_dir/messages.h
M libcxx/include/__locale_dir/money.h
M libcxx/include/__mutex/unique_lock.h
M libcxx/include/__node_handle
M libcxx/include/__tree
M libcxx/include/__type_traits/integer_traits.h
M libcxx/include/__type_traits/make_transparent.h
M libcxx/include/__utility/default_three_way_comparator.h
M libcxx/include/__utility/lazy_synth_three_way_comparator.h
M libcxx/include/__utility/try_key_extraction.h
M libcxx/include/map
M libcxx/include/shared_mutex
M libcxx/include/span
M libcxx/include/version
M libcxx/test/libcxx/atomics/builtin_clear_padding.pass.cpp
M libcxx/test/libcxx/concepts/concepts.arithmetic/__libcpp_signed_integer.compile.pass.cpp
M libcxx/test/libcxx/concepts/concepts.arithmetic/__libcpp_unsigned_integer.compile.pass.cpp
M libcxx/test/libcxx/localization/locales/use_facet.abort.pass.cpp
A libcxx/test/libcxx/localization/nodiscard.verify.cpp
M libcxx/test/libcxx/thread/nodiscard.verify.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/for_each.associative.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/ranges.for_each.associative.pass.cpp
M libcxx/test/std/containers/associative/from_range_associative_containers.h
M libcxx/test/std/containers/associative/map/compare.pass.cpp
M libcxx/test/std/containers/associative/map/get_allocator.pass.cpp
M libcxx/test/std/containers/associative/map/incomplete_type.pass.cpp
M libcxx/test/std/containers/associative/map/map.access/at.pass.cpp
M libcxx/test/std/containers/associative/map/map.access/empty.pass.cpp
M libcxx/test/std/containers/associative/map/map.access/index_key.pass.cpp
M libcxx/test/std/containers/associative/map/map.access/index_rv_key.pass.cpp
M libcxx/test/std/containers/associative/map/map.access/index_tuple.pass.cpp
M libcxx/test/std/containers/associative/map/map.access/iterator.pass.cpp
M libcxx/test/std/containers/associative/map/map.access/max_size.pass.cpp
M libcxx/test/std/containers/associative/map/map.access/size.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/alloc.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/assign_initializer_list.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/compare.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/compare_alloc.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/copy.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/copy_alloc.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/copy_assign.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/deduct.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/deduct_const.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/default.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/default_noexcept.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/dtor_noexcept.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/from_range.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/initializer_list.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/initializer_list_compare.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/initializer_list_compare_alloc.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/iter_iter.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/iter_iter_comp.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/iter_iter_comp_alloc.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/move.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/move_alloc.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/move_assign.pass.cpp
M libcxx/test/std/containers/associative/map/map.cons/move_noexcept.pass.cpp
M libcxx/test/std/containers/associative/map/map.erasure/erase_if.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/clear.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/emplace.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/emplace_hint.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/erase_iter.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/erase_iter_iter.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/erase_key.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/extract_iterator.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/extract_key.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_cv.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_initializer_list.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_iter_cv.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_iter_iter.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_iter_rv.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_node_type.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_node_type_hint.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_or_assign.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_range.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_rv.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/merge.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/try.emplace.pass.cpp
M libcxx/test/std/containers/associative/map/map.nonmember/compare.three_way.pass.cpp
M libcxx/test/std/containers/associative/map/map.nonmember/op_compare.pass.cpp
M libcxx/test/std/containers/associative/map/map.observers/key_comp.pass.cpp
M libcxx/test/std/containers/associative/map/map.observers/value_comp.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/contains.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/contains_transparent.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/count.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/count0.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/count_transparent.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/equal_range.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/equal_range0.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/equal_range_transparent.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/find.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/find0.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/lower_bound.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/lower_bound0.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/upper_bound.pass.cpp
M libcxx/test/std/containers/associative/map/map.ops/upper_bound0.pass.cpp
M libcxx/test/std/containers/associative/map/map.special/member_swap.pass.cpp
M libcxx/test/std/containers/associative/map/map.special/non_member_swap.pass.cpp
M libcxx/test/std/containers/associative/map/map.special/swap_noexcept.pass.cpp
M libcxx/test/std/containers/associative/map/map.value_compare/invoke.pass.cpp
M libcxx/test/std/containers/associative/map/types.pass.cpp
M libcxx/test/std/containers/container.node/node_handle.pass.cpp
M libcxx/test/std/containers/insert_range_maps_sets.h
M libcxx/test/std/containers/views/mdspan/extents/index_type.verify.cpp
M libcxx/test/std/containers/views/views.span/span.objectrep/as_bytes.pass.cpp
M libcxx/test/std/containers/views/views.span/span.objectrep/as_writable_bytes.pass.cpp
R libcxx/test/std/containers/views/views.span/span.objectrep/as_writable_bytes.verify.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/map.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/test/std/numerics/numeric.ops/numeric.ops.sat/saturating_cast.compile.pass.cpp
M libcxx/test/std/utilities/utility/utility.intcmp/intcmp.verify.cpp
A libcxx/test/support/CopyConstructible.h
M libcxx/test/support/is_transparent.h
M libcxx/test/support/nasty_string.h
M libcxx/test/support/private_constructor.h
M libcxx/utils/generate_feature_test_macro_components.py
M lld/COFF/LTO.cpp
M lld/ELF/LTO.cpp
M lld/test/ELF/dtlto/timetrace.test
M lld/test/ELF/lto/devirt_vcall_vis_export_dynamic.ll
M lld/test/ELF/lto/devirt_vcall_vis_public.ll
M lld/test/ELF/lto/devirt_vcall_vis_shared_def.ll
M lldb/CMakeLists.txt
M lldb/bindings/python/CMakeLists.txt
M lldb/cmake/caches/Apple-lldb-macOS.cmake
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/docs/conf.py
M lldb/docs/dil-expr-lang.ebnf
A lldb/docs/python_api.md
R lldb/docs/python_api.rst
A lldb/docs/python_extensions.md
R lldb/docs/python_extensions.rst
A lldb/docs/resources/caveats.md
R lldb/docs/resources/caveats.rst
A lldb/docs/resources/contributing.md
R lldb/docs/resources/contributing.rst
A lldb/docs/resources/fuzzing.md
R lldb/docs/resources/fuzzing.rst
A lldb/docs/use/links.md
R lldb/docs/use/links.rst
A lldb/docs/use/ondemand.md
R lldb/docs/use/ondemand.rst
A lldb/docs/use/python-reference.md
R lldb/docs/use/python-reference.rst
A lldb/docs/use/repeat-commands.md
R lldb/docs/use/repeat-commands.rst
M lldb/include/lldb/Host/Config.h.cmake
M lldb/include/lldb/Host/MainLoopBase.h
A lldb/include/lldb/Host/ScriptInterpreterRuntimeLoader.h
M lldb/include/lldb/Symbol/Symbol.h
M lldb/include/lldb/Target/Memory.h
M lldb/include/lldb/ValueObject/DILAST.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/include/lldb/ValueObject/DILLexer.h
M lldb/include/lldb/ValueObject/DILParser.h
M lldb/include/module.modulemap
M lldb/packages/Python/lldbsuite/test/decorators.py
M lldb/packages/Python/lldbsuite/test/lldbpexpect.py
M lldb/source/API/SystemInitializerFull.cpp
M lldb/source/Commands/CommandObjectSettings.cpp
M lldb/source/Host/CMakeLists.txt
M lldb/source/Host/common/MainLoopBase.cpp
A lldb/source/Host/common/PythonRuntimeLoader.cpp
A lldb/source/Host/common/PythonRuntimeLoaderInternal.h
A lldb/source/Host/common/ScriptInterpreterRuntimeLoader.cpp
A lldb/source/Host/linux/PythonRuntimeLoaderLinux.cpp
A lldb/source/Host/macosx/PythonRuntimeLoaderDarwin.cpp
M lldb/source/Host/windows/PipeWindows.cpp
M lldb/source/Host/windows/PseudoConsole.cpp
A lldb/source/Host/windows/PythonRuntimeLoaderWindows.cpp
M lldb/source/Plugins/DynamicLoader/Windows-DYLD/CMakeLists.txt
M lldb/source/Plugins/DynamicLoader/Windows-DYLD/DynamicLoaderWindowsDYLD.cpp
A lldb/source/Plugins/DynamicLoader/Windows-DYLD/MSVCRTCFrameRecognizer.cpp
A lldb/source/Plugins/DynamicLoader/Windows-DYLD/MSVCRTCFrameRecognizer.h
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Process/Windows/Common/CMakeLists.txt
M lldb/source/Plugins/Process/Windows/Common/DebuggerThread.cpp
M lldb/source/Plugins/Process/Windows/Common/IDebugDelegate.h
M lldb/source/Plugins/Process/Windows/Common/LocalDebugDelegate.cpp
M lldb/source/Plugins/Process/Windows/Common/LocalDebugDelegate.h
R lldb/source/Plugins/Process/Windows/Common/MSVCRTCFrameRecognizer.cpp
R lldb/source/Plugins/Process/Windows/Common/MSVCRTCFrameRecognizer.h
M lldb/source/Plugins/Process/Windows/Common/NativeProcessWindows.h
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.h
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h
M lldb/source/Plugins/Process/Windows/Common/arm/RegisterContextWindows_arm.cpp
M lldb/source/Plugins/Process/Windows/Common/x64/RegisterContextWindows_x64.cpp
M lldb/source/Plugins/Process/Windows/Common/x86/RegisterContextWindows_x86.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/CMakeLists.txt
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Target/Memory.cpp
M lldb/source/ValueObject/DILAST.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILLexer.cpp
M lldb/source/ValueObject/DILParser.cpp
M lldb/test/API/commands/apropos/formatting/TestAproposFormatting.py
M lldb/test/API/commands/expression/multiline-completion/TestMultilineCompletion.py
M lldb/test/API/commands/expression/multiline-navigation/TestMultilineNavigation.py
A lldb/test/API/commands/frame/var-dil/expr/Bitwise/Makefile
A lldb/test/API/commands/frame/var-dil/expr/Bitwise/TestFrameVarDILBitwise.py
A lldb/test/API/commands/frame/var-dil/expr/Bitwise/main.cpp
M lldb/test/API/commands/gui/basic/TestGuiBasic.py
M lldb/test/API/commands/gui/basicdebug/TestGuiBasicDebug.py
M lldb/test/API/commands/gui/breakpoints/TestGuiBreakpoints.py
M lldb/test/API/commands/gui/expand-threads-tree/TestGuiExpandThreadsTree.py
M lldb/test/API/commands/gui/spawn-threads/TestGuiSpawnThreads.py
M lldb/test/API/commands/gui/viewlarge/TestGuiViewLarge.py
M lldb/test/API/commands/register/aarch64_dynamic_regset/main.c
M lldb/test/API/commands/register/aarch64_sve_registers/rw_access_static_config/main.c
M lldb/test/API/functionalities/thread/jump/TestThreadJump.py
M lldb/test/API/iohandler/autosuggestion/TestAutosuggestion.py
M lldb/test/API/iohandler/completion/TestIOHandlerCompletion.py
M lldb/test/API/iohandler/resize/TestIOHandlerResize.py
M lldb/test/API/iohandler/sigint/TestIOHandlerPythonREPLSigint.py
M lldb/test/API/iohandler/sigint/TestProcessIOHandlerInterrupt.py
M lldb/test/API/iohandler/stdio/TestIOHandlerProcessSTDIO.py
M lldb/test/API/iohandler/unicode/TestUnicode.py
M lldb/test/API/macosx/expedited-thread-pcs/TestExpeditedThreadPCs.py
M lldb/test/API/python_api/run_locker/TestRunLocker.py
M lldb/test/API/qemu/TestQemuLaunch.py
M lldb/test/API/repl/clang/TestClangREPL.py
M lldb/test/API/terminal/TestDisabledBreakpoints.py
M lldb/test/API/terminal/TestEditline.py
M lldb/test/CMakeLists.txt
A lldb/test/Shell/Process/Windows/output_debug_string.cpp
M lldb/test/Shell/SymbolFile/DWARF/delayed-definition-die-searching.test
M lldb/tools/debugserver/source/DNB.cpp
M lldb/unittests/Host/CMakeLists.txt
A lldb/unittests/Host/PythonRuntimeLoaderTest.cpp
M llvm/cmake/modules/AddLLVM.cmake
M llvm/docs/AMDGPU/AMDGPUAsmGFX12.rst
R llvm/docs/AMDGPU/gfx12_addr.rst
R llvm/docs/AMDGPU/gfx12_attr.rst
R llvm/docs/AMDGPU/gfx12_clause.rst
R llvm/docs/AMDGPU/gfx12_data0_56f215.rst
R llvm/docs/AMDGPU/gfx12_data0_6802ce.rst
R llvm/docs/AMDGPU/gfx12_data0_e016a1.rst
R llvm/docs/AMDGPU/gfx12_data0_fd235e.rst
R llvm/docs/AMDGPU/gfx12_data1_6802ce.rst
R llvm/docs/AMDGPU/gfx12_data1_731030.rst
R llvm/docs/AMDGPU/gfx12_data1_e016a1.rst
R llvm/docs/AMDGPU/gfx12_data1_fd235e.rst
R llvm/docs/AMDGPU/gfx12_delay.rst
R llvm/docs/AMDGPU/gfx12_hwreg.rst
R llvm/docs/AMDGPU/gfx12_imm16.rst
R llvm/docs/AMDGPU/gfx12_ioffset.rst
R llvm/docs/AMDGPU/gfx12_label.rst
R llvm/docs/AMDGPU/gfx12_literal_1f74c7.rst
R llvm/docs/AMDGPU/gfx12_literal_81e671.rst
R llvm/docs/AMDGPU/gfx12_m.rst
A llvm/docs/AMDGPU/gfx12_operands.rst
R llvm/docs/AMDGPU/gfx12_rsrc_5fe6d8.rst
R llvm/docs/AMDGPU/gfx12_rsrc_c9f929.rst
R llvm/docs/AMDGPU/gfx12_saddr_cdc95c.rst
R llvm/docs/AMDGPU/gfx12_saddr_d42b64.rst
R llvm/docs/AMDGPU/gfx12_samp.rst
R llvm/docs/AMDGPU/gfx12_sbase_453b95.rst
R llvm/docs/AMDGPU/gfx12_sbase_47adb7.rst
R llvm/docs/AMDGPU/gfx12_sdata_0974a4.rst
R llvm/docs/AMDGPU/gfx12_sdata_354189.rst
R llvm/docs/AMDGPU/gfx12_sdata_4585b8.rst
R llvm/docs/AMDGPU/gfx12_sdata_5c7b50.rst
R llvm/docs/AMDGPU/gfx12_sdata_6c003b.rst
R llvm/docs/AMDGPU/gfx12_sdata_836716.rst
R llvm/docs/AMDGPU/gfx12_sdata_d725ab.rst
R llvm/docs/AMDGPU/gfx12_sdata_dd9dd8.rst
R llvm/docs/AMDGPU/gfx12_sdst_006c40.rst
R llvm/docs/AMDGPU/gfx12_sdst_20064d.rst
R llvm/docs/AMDGPU/gfx12_sdst_354189.rst
R llvm/docs/AMDGPU/gfx12_sdst_836716.rst
R llvm/docs/AMDGPU/gfx12_sdst_ced58d.rst
R llvm/docs/AMDGPU/gfx12_sdst_e701cc.rst
R llvm/docs/AMDGPU/gfx12_sendmsg.rst
R llvm/docs/AMDGPU/gfx12_sendmsg_rtn.rst
R llvm/docs/AMDGPU/gfx12_simm16_15ccdd.rst
R llvm/docs/AMDGPU/gfx12_simm16_218bea.rst
R llvm/docs/AMDGPU/gfx12_simm16_39b593.rst
R llvm/docs/AMDGPU/gfx12_simm16_3d2a4f.rst
R llvm/docs/AMDGPU/gfx12_simm16_730a13.rst
R llvm/docs/AMDGPU/gfx12_simm16_7ed651.rst
R llvm/docs/AMDGPU/gfx12_simm16_81e671.rst
R llvm/docs/AMDGPU/gfx12_simm16_c98889.rst
R llvm/docs/AMDGPU/gfx12_simm16_cc1716.rst
R llvm/docs/AMDGPU/gfx12_simm16_ee8b30.rst
R llvm/docs/AMDGPU/gfx12_soffset_8ec073.rst
R llvm/docs/AMDGPU/gfx12_soffset_c5b88c.rst
R llvm/docs/AMDGPU/gfx12_soffset_ec005a.rst
R llvm/docs/AMDGPU/gfx12_src0_5727cf.rst
R llvm/docs/AMDGPU/gfx12_src0_5cae62.rst
R llvm/docs/AMDGPU/gfx12_src0_6802ce.rst
R llvm/docs/AMDGPU/gfx12_src0_85aab6.rst
R llvm/docs/AMDGPU/gfx12_src0_c4593f.rst
R llvm/docs/AMDGPU/gfx12_src0_e016a1.rst
R llvm/docs/AMDGPU/gfx12_src0_fd235e.rst
R llvm/docs/AMDGPU/gfx12_src1_5727cf.rst
R llvm/docs/AMDGPU/gfx12_src1_5cae62.rst
R llvm/docs/AMDGPU/gfx12_src1_6802ce.rst
R llvm/docs/AMDGPU/gfx12_src1_731030.rst
R llvm/docs/AMDGPU/gfx12_src1_977794.rst
R llvm/docs/AMDGPU/gfx12_src1_c4593f.rst
R llvm/docs/AMDGPU/gfx12_src1_e016a1.rst
R llvm/docs/AMDGPU/gfx12_src1_fd235e.rst
R llvm/docs/AMDGPU/gfx12_src2_2797bc.rst
R llvm/docs/AMDGPU/gfx12_src2_5727cf.rst
R llvm/docs/AMDGPU/gfx12_src2_5cae62.rst
R llvm/docs/AMDGPU/gfx12_src2_6802ce.rst
R llvm/docs/AMDGPU/gfx12_src2_7b936a.rst
R llvm/docs/AMDGPU/gfx12_src2_96fbd3.rst
R llvm/docs/AMDGPU/gfx12_src2_c4593f.rst
R llvm/docs/AMDGPU/gfx12_src2_e016a1.rst
R llvm/docs/AMDGPU/gfx12_srcx0.rst
R llvm/docs/AMDGPU/gfx12_srcy0.rst
R llvm/docs/AMDGPU/gfx12_ssrc0_007f9c.rst
R llvm/docs/AMDGPU/gfx12_ssrc0_1a9ca5.rst
R llvm/docs/AMDGPU/gfx12_ssrc0_245536.rst
R llvm/docs/AMDGPU/gfx12_ssrc0_2797bc.rst
R llvm/docs/AMDGPU/gfx12_ssrc0_bbb4c6.rst
R llvm/docs/AMDGPU/gfx12_ssrc0_c4593f.rst
R llvm/docs/AMDGPU/gfx12_ssrc1_bbb4c6.rst
R llvm/docs/AMDGPU/gfx12_ssrc1_c4593f.rst
R llvm/docs/AMDGPU/gfx12_tgt.rst
R llvm/docs/AMDGPU/gfx12_vaddr_a972b9.rst
R llvm/docs/AMDGPU/gfx12_vaddr_c12f43.rst
R llvm/docs/AMDGPU/gfx12_vaddr_c8b8d4.rst
R llvm/docs/AMDGPU/gfx12_vaddr_d82160.rst
R llvm/docs/AMDGPU/gfx12_vaddr_f2b449.rst
R llvm/docs/AMDGPU/gfx12_vcc.rst
R llvm/docs/AMDGPU/gfx12_vdata_2eda77.rst
R llvm/docs/AMDGPU/gfx12_vdata_48e42f.rst
R llvm/docs/AMDGPU/gfx12_vdata_69a144.rst
R llvm/docs/AMDGPU/gfx12_vdata_89680f.rst
R llvm/docs/AMDGPU/gfx12_vdata_aac3e8.rst
R llvm/docs/AMDGPU/gfx12_vdata_bdb32f.rst
R llvm/docs/AMDGPU/gfx12_vdst_006c40.rst
R llvm/docs/AMDGPU/gfx12_vdst_227281.rst
R llvm/docs/AMDGPU/gfx12_vdst_2eda77.rst
R llvm/docs/AMDGPU/gfx12_vdst_47d3bc.rst
R llvm/docs/AMDGPU/gfx12_vdst_48e42f.rst
R llvm/docs/AMDGPU/gfx12_vdst_69a144.rst
R llvm/docs/AMDGPU/gfx12_vdst_7de8e7.rst
R llvm/docs/AMDGPU/gfx12_vdst_836716.rst
R llvm/docs/AMDGPU/gfx12_vdst_89680f.rst
R llvm/docs/AMDGPU/gfx12_vdst_bdb32f.rst
R llvm/docs/AMDGPU/gfx12_vdstx.rst
R llvm/docs/AMDGPU/gfx12_vdsty.rst
R llvm/docs/AMDGPU/gfx12_version.rst
R llvm/docs/AMDGPU/gfx12_vsrc0.rst
R llvm/docs/AMDGPU/gfx12_vsrc1_6802ce.rst
R llvm/docs/AMDGPU/gfx12_vsrc1_fd235e.rst
R llvm/docs/AMDGPU/gfx12_vsrc2.rst
R llvm/docs/AMDGPU/gfx12_vsrc3.rst
R llvm/docs/AMDGPU/gfx12_vsrc_56f215.rst
R llvm/docs/AMDGPU/gfx12_vsrc_6802ce.rst
R llvm/docs/AMDGPU/gfx12_vsrc_89fd7b.rst
R llvm/docs/AMDGPU/gfx12_vsrc_e016a1.rst
R llvm/docs/AMDGPU/gfx12_vsrc_fd235e.rst
R llvm/docs/AMDGPU/gfx12_vsrcx1.rst
R llvm/docs/AMDGPU/gfx12_vsrcy1.rst
R llvm/docs/AMDGPU/gfx12_waitcnt.rst
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CommandGuide/llvm-objcopy.rst
M llvm/docs/CommandGuide/llvm-strip.rst
M llvm/docs/GettingInvolved.rst
M llvm/docs/GitHub.rst
M llvm/docs/LangRef.rst
M llvm/docs/MarkdownQuickstartTemplate.md
M llvm/docs/README.txt
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
A llvm/docs/SphinxQuickstartTemplate.md
R llvm/docs/SphinxQuickstartTemplate.rst
M llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl04.rst
M llvm/include/llvm/ADT/APFixedPoint.h
M llvm/include/llvm/ADT/APInt.h
M llvm/include/llvm/ADT/APSInt.h
M llvm/include/llvm/ADT/ArrayRef.h
M llvm/include/llvm/ADT/BitVector.h
M llvm/include/llvm/ADT/CachedHashString.h
M llvm/include/llvm/ADT/DenseMapInfo.h
M llvm/include/llvm/ADT/DenseMapInfoVariant.h
M llvm/include/llvm/ADT/Hashing.h
M llvm/include/llvm/ADT/ImmutableList.h
M llvm/include/llvm/ADT/PointerEmbeddedInt.h
M llvm/include/llvm/ADT/PointerIntPair.h
M llvm/include/llvm/ADT/PointerSumType.h
M llvm/include/llvm/ADT/PointerUnion.h
M llvm/include/llvm/ADT/SmallBitVector.h
M llvm/include/llvm/ADT/SmallVector.h
M llvm/include/llvm/ADT/StringRef.h
M llvm/include/llvm/Analysis/AliasAnalysis.h
M llvm/include/llvm/Analysis/AssumeBundleQueries.h
M llvm/include/llvm/Analysis/CtxProfAnalysis.h
M llvm/include/llvm/Analysis/IRSimilarityIdentifier.h
M llvm/include/llvm/Analysis/MemoryLocation.h
M llvm/include/llvm/Analysis/MemorySSA.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/BinaryFormat/Minidump.h
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/BinaryFormat/WasmTraits.h
M llvm/include/llvm/Bitcode/BitcodeReader.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/CAS/CASID.h
M llvm/include/llvm/CAS/CASReference.h
M llvm/include/llvm/CodeGen/AccelTable.h
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/CodeGen/MachineOperand.h
M llvm/include/llvm/CodeGen/PBQP/CostAllocator.h
M llvm/include/llvm/CodeGen/Register.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGenTypes/LowLevelType.h
M llvm/include/llvm/DTLTO/DTLTO.h
M llvm/include/llvm/DWARFLinker/Classic/DWARFLinkerDeclContext.h
M llvm/include/llvm/DebugInfo/CodeView/TypeHashing.h
M llvm/include/llvm/DebugInfo/CodeView/TypeIndex.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h
M llvm/include/llvm/DebugInfo/GSYM/FileEntry.h
M llvm/include/llvm/DebugInfo/PDB/Native/PDBFile.h
M llvm/include/llvm/DebugInfo/PDB/Native/PDBFileBuilder.h
M llvm/include/llvm/DebugInfo/PDB/Native/PDBStringTableBuilder.h
M llvm/include/llvm/DebugInfo/PDB/Native/RawConstants.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/ExecutorAddress.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/MemoryFlags.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
M llvm/include/llvm/ExecutionEngine/Orc/SymbolStringPool.h
M llvm/include/llvm/ExecutionEngine/Orc/TargetProcess/SimpleExecutorDylibManager.h
M llvm/include/llvm/Frontend/OpenMP/OMPContext.h
M llvm/include/llvm/IR/AssemblyAnnotationWriter.h
M llvm/include/llvm/IR/Attributes.h
M llvm/include/llvm/IR/BasicBlock.h
M llvm/include/llvm/IR/DebugInfo.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/Dominators.h
M llvm/include/llvm/IR/GlobalObject.h
M llvm/include/llvm/IR/GlobalValue.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/Metadata.h
M llvm/include/llvm/IR/Module.h
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/IR/ValueHandle.h
M llvm/include/llvm/IR/ValueMap.h
M llvm/include/llvm/LTO/Config.h
M llvm/include/llvm/LTO/LTO.h
M llvm/include/llvm/Linker/IRMover.h
M llvm/include/llvm/MC/MCGOFFObjectWriter.h
M llvm/include/llvm/MC/MCRegister.h
M llvm/include/llvm/ObjCopy/CommonConfig.h
M llvm/include/llvm/ObjCopy/ObjCopy.h
M llvm/include/llvm/Object/ObjectFile.h
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
M llvm/include/llvm/ProfileData/FunctionId.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/include/llvm/ProfileData/SampleProf.h
M llvm/include/llvm/SandboxIR/Context.h
M llvm/include/llvm/Support/AMDGPUAddrSpace.h
M llvm/include/llvm/Support/FileSystem/UniqueID.h
M llvm/include/llvm/Support/TypeSize.h
M llvm/include/llvm/Support/UniqueBBID.h
M llvm/include/llvm/Support/VersionTuple.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/TextAPI/SymbolSet.h
M llvm/include/llvm/Transforms/IPO/Attributor.h
M llvm/include/llvm/Transforms/IPO/FunctionSpecialization.h
M llvm/include/llvm/Transforms/IPO/IROutliner.h
M llvm/include/llvm/Transforms/Scalar/GVNExpression.h
R llvm/include/llvm/Transforms/Utils/AssignGUID.h
M llvm/include/llvm/Transforms/Utils/BypassSlowDivision.h
A llvm/include/llvm/Transforms/Utils/TriggerCrashPass.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/CaptureTracking.cpp
M llvm/lib/Analysis/CtxProfAnalysis.cpp
M llvm/lib/Analysis/IRSimilarityIdentifier.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/MemorySSA.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeAnalyzer.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.h
M llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
M llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
M llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalMerge.cpp
M llvm/lib/CodeGen/InlineSpiller.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h
M llvm/lib/CodeGen/MachineOutliner.cpp
M llvm/lib/CodeGen/PseudoProbeInserter.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/lib/CodeGen/StackMaps.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/DTLTO/CMakeLists.txt
M llvm/lib/DTLTO/DTLTO.cpp
A llvm/lib/DTLTO/DTLTODistributionDriver.cpp
A llvm/lib/DTLTO/DTLTOInputFiles.cpp
M llvm/lib/DWARFLinker/Parallel/DependencyTracker.cpp
M llvm/lib/DebugInfo/CodeView/TypeHashing.cpp
M llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp
M llvm/lib/DebugInfo/PDB/Native/GSIStreamBuilder.cpp
M llvm/lib/DebugInfo/PDB/Native/PDBFile.cpp
M llvm/lib/DebugInfo/PDB/Native/PDBFileBuilder.cpp
M llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleExecutorDylibManager.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/BasicBlock.cpp
M llvm/lib/IR/ConstantsContext.h
M llvm/lib/IR/Globals.cpp
M llvm/lib/IR/LLVMContextImpl.h
M llvm/lib/IR/Verifier.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/lib/LTO/LTOBackend.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/MC/GOFFObjectWriter.cpp
M llvm/lib/ObjCopy/Archive.cpp
M llvm/lib/ObjCopy/DXContainer/DXContainerObjcopy.cpp
M llvm/lib/ObjCopy/ObjCopy.cpp
M llvm/lib/Object/Minidump.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Support/StringRef.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMemoryUtils.h
M llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/lib/Target/AMDGPU/SMInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetStreamer.h
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/M68k/AsmParser/CMakeLists.txt
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp
M llvm/lib/Target/NVPTX/NVVMIntrRange.cpp
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
R llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVTypeInst.h
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrFragments.td
M llvm/lib/Target/X86/X86OptimizeLEAs.cpp
M llvm/lib/Target/X86/X86PartialReduction.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/ConstantMerge.cpp
M llvm/lib/Transforms/IPO/FunctionImport.cpp
M llvm/lib/Transforms/IPO/FunctionSpecialization.cpp
M llvm/lib/Transforms/IPO/HotColdSplitting.cpp
M llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/PGOCtxProfFlattening.cpp
M llvm/lib/Transforms/Instrumentation/PGOCtxProfLowering.cpp
M llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
M llvm/lib/Transforms/Scalar/EarlyCSE.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/GVNSink.cpp
M llvm/lib/Transforms/Scalar/JumpTableToSwitch.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
R llvm/lib/Transforms/Utils/AssignGUID.cpp
M llvm/lib/Transforms/Utils/CMakeLists.txt
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
M llvm/lib/Transforms/Utils/CanonicalizeFreezeInLoops.cpp
M llvm/lib/Transforms/Utils/CloneModule.cpp
M llvm/lib/Transforms/Utils/FunctionImportUtils.cpp
M llvm/lib/Transforms/Utils/InlineFunction.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
A llvm/lib/Transforms/Utils/TriggerCrashPass.cpp
M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/runtimes/CMakeLists.txt
M llvm/test/Assembler/index-value-order.ll
A llvm/test/Bitcode/musttail-bitcast-upgrade.ll
A llvm/test/Bitcode/musttail-bitcast-upgrade.ll.bc
M llvm/test/Bitcode/thinlto-alias.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph-partial-sample-profile-summary.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph-pgo.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph-profile-summary.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph-sample-profile-summary.ll
M llvm/test/Bitcode/thinlto-function-summary-callgraph.ll
M llvm/test/Bitcode/thinlto-function-summary-refgraph.ll
M llvm/test/Bitcode/thinlto-function-summary.ll
A llvm/test/CodeGen/AArch64/GlobalISel/combine-or-of-and.ll
A llvm/test/CodeGen/AArch64/GlobalISel/combine-or-of-and.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll
A llvm/test/CodeGen/AArch64/aarch64-f16f32dot-intrinsics.ll
A llvm/test/CodeGen/AArch64/aarch64-pseudo-probe-tail-call.ll
M llvm/test/CodeGen/AArch64/aarch64-sme-za-call-lowering.ll
M llvm/test/CodeGen/AArch64/aarch64-sysreg128.ll
M llvm/test/CodeGen/AArch64/arm64-int-neon.ll
R llvm/test/CodeGen/AArch64/arm64-invalid-sys-reg.ll
A llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
M llvm/test/CodeGen/AArch64/arm64-vcnt.ll
M llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-fpr.ll
M llvm/test/CodeGen/AArch64/bitfield-insert.ll
M llvm/test/CodeGen/AArch64/bswap-known-bits.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add.ll
M llvm/test/CodeGen/AArch64/expand-sme-pseudos.mir
M llvm/test/CodeGen/AArch64/machine-sme-abi-find-insert-pt.mir
M llvm/test/CodeGen/AArch64/machine-sme-abi-skip-debug-inst.mir
M llvm/test/CodeGen/AArch64/sme-abi-eh-liveins.mir
M llvm/test/CodeGen/AArch64/sme-lazy-sve-nzcv-live.mir
M llvm/test/CodeGen/AArch64/special-reg.ll
M llvm/test/CodeGen/AArch64/sshl_sat.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
M llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics-fp-converts.ll
A llvm/test/CodeGen/AArch64/sve2p3-intrinsics-fp-converts_x2.ll
M llvm/test/CodeGen/AArch64/ushl_sat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
A llvm/test/CodeGen/AMDGPU/div-rem-fast-path.ll
A llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation-direct-chain.ll
A llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation-indirect.ll
A llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation.ll
M llvm/test/CodeGen/AMDGPU/dvgpr_sym_fail_too_many_block_size_16.ll
M llvm/test/CodeGen/AMDGPU/dvgpr_sym_fail_too_many_block_size_16_anon.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
M llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size-error.ll
M llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.inst.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll
A llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udivrem24.ll
M llvm/test/CodeGen/AMDGPU/widen_extending_scalar_loads.ll
A llvm/test/CodeGen/DirectX/SampleGrad.ll
A llvm/test/CodeGen/NVPTX/atomicrmw-allow-ftz-atomics.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
M llvm/test/CodeGen/NVPTX/atomicrmw.py
M llvm/test/CodeGen/NVPTX/atomics.ll
M llvm/test/CodeGen/NVPTX/globals_init.ll
M llvm/test/CodeGen/NVPTX/intr-range.ll
M llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll
M llvm/test/CodeGen/NVPTX/shift-opt.ll
A llvm/test/CodeGen/PowerPC/aix-codemodel.ll
M llvm/test/CodeGen/PowerPC/ppc-i128-cmp.ll
M llvm/test/CodeGen/PowerPC/ucmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
M llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/frame.ll
M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
M llvm/test/CodeGen/RISCV/ipra.ll
M llvm/test/CodeGen/RISCV/large-stack.ll
M llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
M llvm/test/CodeGen/RISCV/pr148084.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
M llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
M llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
M llvm/test/CodeGen/RISCV/rvv/stack-probing-dynamic.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
A llvm/test/CodeGen/RISCV/rvv/xsfmm-insert-vsetvl-TMTK.mir
A llvm/test/CodeGen/RISCV/shrinkwrap-save-restore-fixed-reg.ll
A llvm/test/CodeGen/RISCV/stack-offset-large.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
A llvm/test/CodeGen/SPIRV/cloned-funcs-metadata-oob.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/module_asm_unsupported.ll
A llvm/test/CodeGen/SPIRV/transcoding/OpenCL/convert_signedness.ll
M llvm/test/CodeGen/SPIRV/transcoding/enqueue_kernel.ll
A llvm/test/CodeGen/SPIRV/transcoding/func_param_attr.ll
A llvm/test/CodeGen/SystemZ/vec-move-25.ll
A llvm/test/CodeGen/X86/GlobalISel/calllowering-inalloca.ll
A llvm/test/CodeGen/X86/aext-and-trunc-avx512.ll
A llvm/test/CodeGen/X86/aext-and-trunc.ll
M llvm/test/CodeGen/X86/and-with-overflow.ll
A llvm/test/CodeGen/X86/apx/memfold-origVNI-crash.ll
M llvm/test/CodeGen/X86/atomic-load-store.ll
M llvm/test/CodeGen/X86/avg-mask.ll
M llvm/test/CodeGen/X86/avx512-trunc.ll
M llvm/test/CodeGen/X86/bittest-big-integer.ll
A llvm/test/CodeGen/X86/bt-merge-fuse.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/clmul.ll
M llvm/test/CodeGen/X86/combine-srem.ll
M llvm/test/CodeGen/X86/fat-lto-section.ll
M llvm/test/CodeGen/X86/llvm.frexp.ll
M llvm/test/CodeGen/X86/masked_load.ll
M llvm/test/CodeGen/X86/masked_store.ll
A llvm/test/CodeGen/X86/pseudo-probe-tail-call.ll
M llvm/test/CodeGen/X86/sad.ll
M llvm/test/CodeGen/X86/shuffle-strided-with-offset-512.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-innerouter.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbits.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-lowhigh.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
A llvm/test/CodeGen/Xtensa/landingpad.ll
M llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
M llvm/test/Instrumentation/AddressSanitizer/musttail.ll
R llvm/test/Instrumentation/InstrProfiling/amdgpu-instrumentation.ll
R llvm/test/Instrumentation/InstrProfiling/amdgpu-profc-arrays.ll
R llvm/test/Instrumentation/InstrProfiling/gpu-weak.ll
M llvm/test/Instrumentation/ThreadSanitizer/tsan_musttail.ll
M llvm/test/LTO/Resolution/X86/not-prevailing-alias.ll
M llvm/test/LTO/Resolution/X86/not-prevailing-weak-aliasee.ll
M llvm/test/Linker/funcimport2.ll
M llvm/test/MC/AArch64/arm64-system-encoding.s
M llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s
M llvm/test/MC/AArch64/armv9-mrrs.s
M llvm/test/MC/AArch64/armv9-msrr-diagnostics.s
M llvm/test/MC/AArch64/armv9-msrr.s
M llvm/test/MC/AArch64/basic-a64-instructions.s
M llvm/test/MC/AMDGPU/mcexpr_amd.s
M llvm/test/MC/AMDGPU/mcexpr_amd_err.s
M llvm/test/MC/Disassembler/AArch64/armv8.2a-uao.txt
M llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt
M llvm/test/MC/Disassembler/AArch64/armv8.5a-dataproc.txt
M llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
M llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt
M llvm/test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt
M llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt
M llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt
M llvm/test/MC/Disassembler/AArch64/armv8.8a-nmi.txt
M llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
M llvm/test/MC/RISCV/rvi-pseudos.s
R llvm/test/MC/RISCV/xrivosvizip-invalid.s
R llvm/test/MC/RISCV/xrivosvizip-valid.s
M llvm/test/Other/new-pm-O0-defaults.ll
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
A llvm/test/Other/trigger-crash-flags.ll
M llvm/test/TableGen/aarch64-apple-tuning-features.td
M llvm/test/ThinLTO/AArch64/aarch64_inline.ll
M llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions1.ll
M llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions2.ll
M llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions3.ll
M llvm/test/ThinLTO/X86/ctor-dtor-alias.ll
M llvm/test/ThinLTO/X86/ctor-dtor-alias2.ll
M llvm/test/ThinLTO/X86/deadstrip.ll
M llvm/test/ThinLTO/X86/devirt_function_alias.ll
M llvm/test/ThinLTO/X86/devirt_function_alias2.ll
M llvm/test/ThinLTO/X86/devirt_pure_virtual_base.ll
M llvm/test/ThinLTO/X86/devirt_vcall_vis_public.ll
M llvm/test/ThinLTO/X86/distributed_import.ll
M llvm/test/ThinLTO/X86/dtlto/timetrace.ll
M llvm/test/ThinLTO/X86/funcattrs-prop-exported-internal.ll
M llvm/test/ThinLTO/X86/funcattrs-prop-unknown.ll
M llvm/test/ThinLTO/X86/funcattrs-prop-weak.ll
M llvm/test/ThinLTO/X86/globals-import.ll
M llvm/test/ThinLTO/X86/hidden-escaped-symbols-alt.ll
M llvm/test/ThinLTO/X86/hidden-escaped-symbols.ll
M llvm/test/ThinLTO/X86/import-ro-constant.ll
M llvm/test/ThinLTO/X86/index-const-prop-alias.ll
M llvm/test/ThinLTO/X86/index-const-prop.ll
M llvm/test/ThinLTO/X86/linkonce_resolution_comdat.ll
M llvm/test/ThinLTO/X86/memprof-dups.ll
M llvm/test/ThinLTO/X86/memprof_callee_type_mismatch.ll
M llvm/test/ThinLTO/X86/memprof_imported_internal.ll
M llvm/test/ThinLTO/X86/memprof_imported_internal2.ll
M llvm/test/ThinLTO/X86/prevailing_weak_globals_import.ll
M llvm/test/ThinLTO/X86/visibility-elf.ll
M llvm/test/ThinLTO/X86/visibility-macho.ll
M llvm/test/ThinLTO/X86/weak_resolution.ll
M llvm/test/ThinLTO/X86/windows-vftable.ll
M llvm/test/ThinLTO/X86/writeonly.ll
R llvm/test/Transforms/AssignGUID/assign_guid.ll
M llvm/test/Transforms/CallSiteSplitting/musttail.ll
M llvm/test/Transforms/CodeExtractor/input-value-debug.ll
M llvm/test/Transforms/ConstantMerge/merge-dbg.ll
M llvm/test/Transforms/EmbedBitcode/embed-wpd.ll
M llvm/test/Transforms/EmbedBitcode/embed.ll
M llvm/test/Transforms/FunctionAttrs/writeonly.ll
M llvm/test/Transforms/FunctionImport/funcimport-debug-retained-nodes.ll
M llvm/test/Transforms/FunctionImport/funcimport.ll
R llvm/test/Transforms/GlobalMerge/guid.ll
R llvm/test/Transforms/InferAddressSpaces/AMDGPU/old-pass-regressions-inseltpoison.ll
M llvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll
M llvm/test/Transforms/InstCombine/masked_intrinsics.ll
M llvm/test/Transforms/InstCombine/pr83947.ll
M llvm/test/Transforms/InstSimplify/call.ll
R llvm/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses-inseltpoison.ll
M llvm/test/Transforms/LoopInterchange/call-instructions.ll
A llvm/test/Transforms/LoopInterchange/function-attr.ll
A llvm/test/Transforms/LoopInterchange/lcssa-incoming-value-is-not-instr.ll
R llvm/test/Transforms/LoopInterchange/memory-attr.ll
M llvm/test/Transforms/LoopVectorize/AArch64/cmp_cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fully-unrolled-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleaved_cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-chained.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-metadata.ll
M llvm/test/Transforms/LoopVectorize/ARM/interleaved_cost.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
A llvm/test/Transforms/LoopVectorize/RISCV/strided-access-wide-stride.ll
A llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-narrow-iv.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/mem-interleaving-costs-02.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/mem-interleaving-costs.ll
M llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/WebAssembly/memory-interleave.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/handle-iptr-with-data-layout-to-not-assert.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2-indices-0u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-01u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-0uu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-01uu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-0uuu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-store-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/reduction-small-size.ll
M llvm/test/Transforms/LoopVectorize/cast-costs.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size.ll
M llvm/test/Transforms/LoopVectorize/early_exit_store_legality.ll
M llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
A llvm/test/Transforms/LoopVectorize/interleave_uncountable_exits.ll
M llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
A llvm/test/Transforms/LoopVectorize/scalarized_conditional_ops_uncountable_exits.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
A llvm/test/Transforms/LoopVectorize/tail_fold_uncountable_exits.ll
M llvm/test/Transforms/LoopVectorize/vplan-incomplete-cases.ll
M llvm/test/Transforms/LowerTypeTests/cfi-icall-alias.ll
M llvm/test/Transforms/MemCpyOpt/memcpy.ll
R llvm/test/Transforms/PGOProfile/amdgpu-disable-value-profiling.ll
M llvm/test/Transforms/PGOProfile/thinlto_indirect_call_promotion.ll
M llvm/test/Transforms/PhaseOrdering/speculative-devirt-then-inliner.ll
A llvm/test/Transforms/SLPVectorizer/ARM/extract-cost-scale-nullptr-user.ll
A llvm/test/Transforms/SLPVectorizer/X86/copyable-operand-non-scheduled-parent-node.ll
M llvm/test/Transforms/SLPVectorizer/X86/external-bin-op-user.ll
A llvm/test/Transforms/SLPVectorizer/X86/phi-vectorization-budget.ll
A llvm/test/Transforms/SLPVectorizer/X86/sincos.ll
M llvm/test/Transforms/SafeStack/X86/musttail.ll
M llvm/test/Transforms/SampleProfile/ctxsplit.ll
M llvm/test/Transforms/SandboxVectorizer/load_store_vec.ll
M llvm/test/Transforms/SimplifyCFG/speculate-derefable-load.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal-typeid.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal1.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-internal2.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc-internal.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/split.ll
M llvm/test/Transforms/ThinLTOBitcodeWriter/unsplittable.ll
M llvm/test/Transforms/WholeProgramDevirt/branch-funnel-profile.ll
M llvm/test/Transforms/WholeProgramDevirt/export-single-impl.ll
M llvm/test/Transforms/WholeProgramDevirt/export-vcp.ll
M llvm/test/Verifier/immarg-param-attribute-invalid.ll
M llvm/test/Verifier/musttail-invalid.ll
M llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/x86-loopvectorize-costmodel.ll
M llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/x86-loopvectorize-costmodel.ll.expected
M llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/loopvectorize-costmodel.test
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs.ll.generated.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs.ll.nogenerated.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs_prefix_reuse.ll.generated.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/generated_funcs_prefix_reuse.ll.nogenerated.globals.expected
A llvm/test/tools/dsymutil/Inputs/drop-module-fwd-decl/debug-map.map
A llvm/test/tools/dsymutil/Inputs/drop-module-fwd-decl/input.ll
A llvm/test/tools/dsymutil/Inputs/keep-module-fwd-decl-template/debug-map.map
A llvm/test/tools/dsymutil/Inputs/keep-module-fwd-decl-template/input.ll
A llvm/test/tools/dsymutil/X86/drop-module-fwd-decl.test
A llvm/test/tools/dsymutil/X86/keep-module-fwd-decl-template.test
M llvm/test/tools/dsymutil/X86/submodules.m
M llvm/test/tools/gold/X86/devirt_vcall_vis_export_dynamic.ll
M llvm/test/tools/gold/X86/devirt_vcall_vis_public.ll
M llvm/test/tools/gold/X86/devirt_vcall_vis_shared_def.ll
M llvm/test/tools/gold/X86/thinlto_weak_library.ll
M llvm/test/tools/gold/X86/thinlto_weak_resolution.ll
M llvm/test/tools/gold/X86/v1.16/devirt_vcall_vis_export_dynamic.ll
M llvm/test/tools/llubi/controlflow.ll
A llvm/test/tools/llubi/global.ll
A llvm/test/tools/llubi/global_constant_store.ll
A llvm/test/tools/llubi/global_constexpr_initializer.ll
A llvm/test/tools/llubi/global_external.ll
M llvm/test/tools/llvm-objcopy/DXContainer/copy-headers.yaml
M llvm/test/tools/llvm-objcopy/DXContainer/dump-section.yaml
A llvm/test/tools/llvm-objcopy/verbose.test
A llvm/test/tools/llvm-pdbutil/dxcontainer.test
M llvm/tools/dsymutil/BinaryHolder.h
M llvm/tools/llubi/lib/Context.cpp
M llvm/tools/llubi/lib/Context.h
M llvm/tools/llubi/lib/ExecutorBase.cpp
M llvm/tools/llubi/lib/Interpreter.cpp
M llvm/tools/llubi/lib/Value.cpp
M llvm/tools/llubi/lib/Value.h
M llvm/tools/llubi/llubi.cpp
M llvm/tools/llvm-c-test/echo.cpp
M llvm/tools/llvm-exegesis/lib/LlvmState.cpp
M llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
M llvm/tools/llvm-exegesis/lib/MCInstrDescView.h
M llvm/tools/llvm-link/llvm-link.cpp
M llvm/tools/llvm-lto2/CMakeLists.txt
M llvm/tools/llvm-lto2/llvm-lto2.cpp
M llvm/tools/llvm-objcopy/CommonOpts.td
M llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
M llvm/tools/llvm-objcopy/llvm-objcopy.cpp
M llvm/tools/llvm-pdbutil/PdbYaml.cpp
M llvm/tools/llvm-pdbutil/PdbYaml.h
M llvm/tools/llvm-pdbutil/YAMLOutputStyle.cpp
M llvm/tools/llvm-pdbutil/YAMLOutputStyle.h
M llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp
M llvm/tools/llvm-pdbutil/llvm-pdbutil.h
M llvm/tools/llvm-reduce/deltas/Delta.h
M llvm/tools/llvm-split/llvm-split.cpp
M llvm/tools/opt/NewPMDriver.cpp
M llvm/tools/opt/optdriver.cpp
M llvm/unittests/ADT/DenseMapTest.cpp
M llvm/unittests/ADT/DenseSetTest.cpp
M llvm/unittests/ADT/MapVectorTest.cpp
M llvm/unittests/Support/ReverseIterationTest.cpp
A llvm/unittests/Target/AMDGPU/AMDGPUMCExprTest.cpp
M llvm/unittests/Target/AMDGPU/CMakeLists.txt
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanUncountableExitTest.cpp
M llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp
M llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
M llvm/utils/gdb-scripts/prettyprinters.py
M llvm/utils/gn/build/sync_source_lists_from_cmake.py
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/bugprone/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/AST/ByteCode/BUILD.gn
M llvm/utils/gn/secondary/lldb/include/lldb/Host/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Host/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/DynamicLoader/Windows-DYLD/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Windows/Common/BUILD.gn
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/DTLTO/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-lto2/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn
M llvm/utils/profcheck-xfail.txt
M mlir/docs/Dialects/LLVM.md
M mlir/docs/LangRef.md
A mlir/docs/Tokens.md
M mlir/docs/Traits/_index.md
M mlir/include/mlir/Bindings/Python/IRCore.h
M mlir/include/mlir/Bytecode/BytecodeWriter.h
M mlir/include/mlir/Dialect/Async/IR/Async.h
M mlir/include/mlir/Dialect/Async/IR/AsyncOps.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/Quant/IR/QuantTypes.h
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/include/mlir/IR/BuiltinDialectBytecode.td
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/include/mlir/IR/OpBase.td
M mlir/include/mlir/IR/OpDefinition.h
M mlir/lib/AsmParser/TokenKinds.def
M mlir/lib/AsmParser/TypeParser.cpp
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bytecode/Writer/BytecodeWriter.cpp
M mlir/lib/Bytecode/Writer/IRNumbering.cpp
M mlir/lib/Bytecode/Writer/IRNumbering.h
M mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
M mlir/lib/Dialect/Async/IR/Async.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncRuntimeRefCounting.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationDialect.cpp
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCComputeLowering.cpp
M mlir/lib/Dialect/Quant/IR/QuantOps.cpp
M mlir/lib/Dialect/Quant/IR/QuantTypes.cpp
M mlir/lib/Dialect/Quant/IR/TypeDetail.h
M mlir/lib/Dialect/Quant/IR/TypeParser.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/Verifier.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/TypeFromLLVM.cpp
M mlir/lib/Target/LLVMIR/TypeToLLVM.cpp
M mlir/test/Conversion/AsyncToLLVM/convert-coro-to-llvm.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-copy.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-dealloc.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-alloc-load-store.mlir
M mlir/test/Conversion/MemRefToEmitC/memref-to-emitc-copy.mlir
M mlir/test/Dialect/ArmSME/invalid.mlir
M mlir/test/Dialect/Builtin/Bytecode/builtin_fixed.mlir
M mlir/test/Dialect/Builtin/Bytecode/builtin_fixed_0.mlirbc
M mlir/test/Dialect/Builtin/Bytecode/types.mlir
M mlir/test/Dialect/EmitC/attrs.mlir
M mlir/test/Dialect/EmitC/invalid_ops.mlir
A mlir/test/Dialect/EmitC/member_call_opaque.mlir
M mlir/test/Dialect/EmitC/ops.mlir
M mlir/test/Dialect/LLVMIR/types.mlir
M mlir/test/Dialect/Linalg/invalid.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
A mlir/test/Dialect/OpenACC/acc-compute-lowering-compute-device-type.mlir
A mlir/test/Dialect/OpenACC/acc-compute-lowering-loop-device-type.mlir
A mlir/test/Dialect/Quant/invalid-quantile-types.mlir
M mlir/test/Dialect/Quant/parse-uniform-invalid.mlir
M mlir/test/Dialect/Quant/parse-uniform.mlir
A mlir/test/Dialect/Quant/quantile-types.mlir
A mlir/test/Dialect/SPIRV/IR/tosa-ops-dynamic.mlir
M mlir/test/Dialect/SparseTensor/invalid.mlir
M mlir/test/Dialect/Tensor/invalid.mlir
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Dialect/traits.mlir
M mlir/test/IR/operand.mlir
M mlir/test/IR/result.mlir
A mlir/test/IR/token-type.mlir
M mlir/test/Target/Cpp/call.mlir
M mlir/test/Target/Cpp/expressions.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
A mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-device-2.mlir
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/mlir-tblgen/predicate.td
M mlir/test/mlir-tblgen/types.mlir
M mlir/test/python/ir/location.py
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/unittests/Bytecode/BytecodeTest.cpp
M offload/ci/hip-tpl.py
M offload/plugins-nextgen/level_zero/include/L0CmdListManager.h
M offload/plugins-nextgen/level_zero/include/L0Queue.h
M offload/plugins-nextgen/level_zero/src/L0Device.cpp
M offload/plugins-nextgen/level_zero/src/L0Queue.cpp
M openmp/docs/README.txt
M openmp/module/CMakeLists.txt
M openmp/tools/archer/ompt-tsan.cpp
M orc-rt/include/orc-rt/NativeDylibManager.h
M orc-rt/lib/executor/NativeDylibManager.cpp
M orc-rt/lib/executor/sps-ci/NativeDylibManagerSPSCI.cpp
M orc-rt/unittests/NativeDylibManagerSPSCITest.cpp
M orc-rt/unittests/NativeDylibManagerTest.cpp
M third-party/benchmark/src/sysinfo.cc
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/kasuga-fj/loop-interchange-fix-non-phi-lcssa-use
Compare: https://github.com/llvm/llvm-project/compare/8d93c0e9a1ed...5c4e85a35bda
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list