[all-commits] [llvm/llvm-project] 1a03c2: [AMDGPU] Remove definition of hi16 for scalar regi...

[Igor Wodiany via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1a03c29cab6bc8c67023181cfdafbd5e0dbac815
      https://github.com/llvm/llvm-project/commit/1a03c29cab6bc8c67023181cfdafbd5e0dbac815
  Author: Igor Wodiany <igor.wodiany at amd.com>
  Date:   2026-06-03 (Wed, 03 Jun 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/test/CodeGen/AMDGPU/asm-printer-check-vcc.mir
    M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
    M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
    M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
    M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
    M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
    M llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
    M llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
    M llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir
    M llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
    M llvm/test/CodeGen/AMDGPU/sched-image-sample-post-RA.mir
    M llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
    M llvm/test/MC/AMDGPU/gfx11_asm_t16_err.s
    M llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp

  Log Message:
  -----------
  [AMDGPU] Remove definition of hi16 for scalar registers (#197467)

The sub-register is not supported by the back-end pipelines and will
eventually cause an assert. With this change machine verifier can
enforce that hi16 is not being used. Asm parser is also updated to error
on invalid sub-registers, instead of asserting.

This is a follow up change on #188781.

Assisted-by: Claude Code



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