[all-commits] [llvm/llvm-project] f1c6c1: [NVPTX] Fix sext(shl nsw x, topbit) miscompile. (#...

[Justin Lebar via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f1c6c1a3de116fb273b25d5f9022c8d44ea72fb4
      https://github.com/llvm/llvm-project/commit/f1c6c1a3de116fb273b25d5f9022c8d44ea72fb4
  Author: Justin Lebar <justin.lebar at gmail.com>
  Date:   2026-06-01 (Mon, 01 Jun 2026)

  Changed paths:
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/test/CodeGen/NVPTX/mulwide.ll

  Log Message:
  -----------
  [NVPTX] Fix sext(shl nsw x, topbit) miscompile. (#200924)

Consider the following IR.

    i64 f(i32 %x) {
      %s = shl nsw i32 %x, 31
      %e = sext i32 %s to i64
      ret %e
    }

combineMulWide (renamed in this patch to combineSZExtToMulWide) rewrites
this into:

    mul.wide.s32 %dst, %x, -2147483648

The LLVM IR is only meaningful for %x == 0 or -1; all other inputs
result in poison. Therefore to check whether this rewrite is correct, we
just need to ask if it generates the correct output when %x is 0 and
when %x is -1.

  - When x == 0, IR and PTX both produce 0.  OK.
  - When x == -1:
    - IR produces sext(INT32_MIN), whereas
    - PTX produces sext(-1) * sext(INT32_MIN) = -sext(INT32_MIN)

Therefore the transformation is not correct.

This only happens when we're shifting by N-1 bits (where N is the narrow
integer width).  In other cases, the multiplier is positive and it works
fine.



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