[all-commits] [llvm/llvm-project] 78f429: [AArch64][SVE] Match (add_like x (lsr y, c)) -> us...

[Harry Ramsey via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 78f429c3b2aeb8105c888133008dea0023b8eebb
      https://github.com/llvm/llvm-project/commit/78f429c3b2aeb8105c888133008dea0023b8eebb
  Author: Harry Ramsey <harry.ramsey at arm.com>
  Date:   2026-06-01 (Mon, 01 Jun 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/sve2-sra.ll

  Log Message:
  -----------
  [AArch64][SVE] Match (add_like x (lsr y, c)) -> usra x, y, c

Modify SVE USRA pattern to accept add_like, so both add and or disjoint
forms can select usra.

Add known-bits support for predicated SVE logical shifts, allowing
or_disjoint matching to prove disjointness for plain ORs where possible.



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