[all-commits] [llvm/llvm-project] fb2fe7: [AArch64] Generate umaddl and smaddl from disjoint...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fb2fe71ffe5ffbced0ce2ce1f4c81bfcb5d487d9
      https://github.com/llvm/llvm-project/commit/fb2fe71ffe5ffbced0ce2ce1f4c81bfcb5d487d9
  Author: David Green <david.green at arm.com>
  Date:   2026-06-01 (Mon, 01 Jun 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll

  Log Message:
  -----------
  [AArch64] Generate umaddl and smaddl from disjoint or (#200198)

Similar to other patches recently, this adds add_like handling to the
tablegen patterns for smaddl and umaddl, allowing them to match from
disjoint or.



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