[all-commits] [llvm/llvm-project] 0b7011: [SelectionDAG] Fix SplitVecRes_VP_REVERSE for sub-...

[Justin Lebar via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0b70118713e57c947914888310584589ffca664d
      https://github.com/llvm/llvm-project/commit/0b70118713e57c947914888310584589ffca664d
  Author: Justin Lebar <justin.lebar at gmail.com>
  Date:   2026-05-31 (Sun, 31 May 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll

  Log Message:
  -----------
  [SelectionDAG] Fix SplitVecRes_VP_REVERSE for sub-byte (i1) element types (#200625)

The strided-store/reload reverse computes the byte stride as
getScalarSizeInBits() / 8, which is 0 for i1: every lane lands at the
same address and the result is garbage.

Widen sub-byte elements to a byte integer (i1 -> i8), reverse, then
truncate back.



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