[all-commits] [llvm/llvm-project] fae9a1: [clang-format] Recognize Verilog class item qualif...

[sstwcw via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fae9a1c3e887d58f03994d078f117e1f29b1810c
      https://github.com/llvm/llvm-project/commit/fae9a1c3e887d58f03994d078f117e1f29b1810c
  Author: sstwcw <su3e8a96kzlver at posteo.net>
  Date:   2026-05-31 (Sun, 31 May 2026)

  Changed paths:
    M clang/lib/Format/FormatToken.h
    M clang/lib/Format/UnwrappedLineParser.cpp
    M clang/lib/Format/UnwrappedLineParser.h
    M clang/unittests/Format/FormatTestVerilog.cpp

  Log Message:
  -----------
  [clang-format] Recognize Verilog class item qualifiers (#199085)

old

```SystemVerilog
class Packet
  extern protected virtual function int send
      (int value);
  endclass : Packet
```

new

```SystemVerilog
class Packet
  extern protected virtual function int send
      (int value);
endclass : Packet
```

Previously the `extern` line failed to parse completely because the
`protected virtual` part was not recognized. It made the following lines
get indented wrong.



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