[all-commits] [llvm/llvm-project] 62a238: [AMDGPU] Use v_rsq_f32 for f16 rsqrt on targets wi...

[Vedran Miletić via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 62a23823a97991f09745b9e76f81b490989bc467
      https://github.com/llvm/llvm-project/commit/62a23823a97991f09745b9e76f81b490989bc467
  Author: Vedran Miletić <vedran at miletic.net>
  Date:   2026-05-31 (Sun, 31 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll

  Log Message:
  -----------
  [AMDGPU] Use v_rsq_f32 for f16 rsqrt on targets without 16-bit insts (#200646)

On gfx6/gfx7 the f16 1.0/sqrt(x) pattern was not folded to a reciprocal
square root because performFDivCombine bailed out whenever f16 fsqrt was
not a legal operation. f16 fsqrt is Custom (promoted) on these targets,
so the combine never fired and the full f32 fdiv expansion was emitted.

Split the legality check: when same-type fsqrt is legal (gfx8+), keep
emitting the native rsq. For f16 without a legal fsqrt, compute the
reciprocal square root in f32 with v_rsq_f32 and round back. This is
accurate enough for f16, and needs no denormal scaling because every f16
value extends to a normal f32 and an f16 rsq result is never denormal.

bf16 is intentionally left expanded: it shares f32's exponent range, so
bf16 denormals would extend to f32 denormals that v_rsq_f32 does not
handle.

Fixes #76948

Co-authored-by: Claude Opus 4.8 <noreply at anthropic.com>



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