[all-commits] [llvm/llvm-project] 03d8fa: [MLIR][Arith][WIE] Fix Conversions for Shift Left ...

[veera via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 03d8fa70398db82a962de9368622add69e26e805
      https://github.com/llvm/llvm-project/commit/03d8fa70398db82a962de9368622add69e26e805
  Author: veera <veera at efficient.computer>
  Date:   2026-05-29 (Fri, 29 May 2026)

  Changed paths:
    M mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp
    M mlir/test/Dialect/Arith/emulate-wide-int.mlir

  Log Message:
  -----------
  [MLIR][Arith][WIE] Fix Conversions for Shift Left and Right Ops (#198457)

The current conversions for `arith.shli`, `arith.shrui` and
`arith.shrsi` does not handle shift by zero correctly. It tries to shift
a `iN` value by N and results in a poison value.

This PR fixes it by adopting the math used by RISCV backend to lower 64
bit shift operations for 32 bit targets. This implementation uses less
number of ops than the existing one.

Negative proofs for current implementation:
shli: https://alive2.llvm.org/ce/z/_Q8ZuC
shrui: https://alive2.llvm.org/ce/z/vDZeEV
shrsi: https://alive2.llvm.org/ce/z/vZVatx

Proofs for attempted fix in this PR:
shli: https://alive2.llvm.org/ce/z/SDJJXW
shrui: https://alive2.llvm.org/ce/z/FZcP5y
shrsi: https://alive2.llvm.org/ce/z/5nk86z



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