[all-commits] [llvm/llvm-project] 098b05: [RISC-V][MC] Introduce initial support for RVY (CH...

[Alexander Richardson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 098b05f32989a4243243860c69e8ec775c86669c
      https://github.com/llvm/llvm-project/commit/098b05f32989a4243243860c69e8ec775c86669c
  Author: Alexander Richardson <alexrichardson at google.com>
  Date:   2026-05-29 (Fri, 29 May 2026)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    A llvm/lib/Target/RISCV/RISCVInstrInfoY.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    A llvm/test/CodeGen/RISCV/rvy/rvy-invalid-operands.mir
    A llvm/test/MC/RISCV/rvy/rvy-basic-invalid.s
    A llvm/test/MC/RISCV/rvy/rvy-basic.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISC-V][MC] Introduce initial support for RVY (CHERI)

This adds MC-level support for most of the base Y extension instructions
using the latest 0.9.8.2 draft of the specification. This initial pull
request is restricted to the execution-mode-independent subset. The RVY
base ISA (CHERI for RISC-V) also introduces an execution mode that
determines whether certain register operands use the full extended
register or only the address subset (the current XLEN registers). The
instructions that depend on execution mode (loads/stores/jumps + AUIPC)
will be added in the following commits in this stack of changes.

Specification: https://riscv.github.io/riscv-cheri/
Co-authored-by: Jessica Clarke <jrtc27 at jrtc27.com>

Pull Request: https://github.com/llvm/llvm-project/pull/199771



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