[all-commits] [llvm/llvm-project] 8476a5: [AArch64][llvm] Restrict STSHH decoding to valid p...

[Jonathan Thackray via All-commits]

  Branch: refs/heads/users/jthackray/fix_stshh_policy
  Home:   https://github.com/llvm/llvm-project
  Commit: 8476a592795c43dca8efd04268eaa68cf10a2863
      https://github.com/llvm/llvm-project/commit/8476a592795c43dca8efd04268eaa68cf10a2863
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2026-05-29 (Fri, 29 May 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td

  Log Message:
  -----------
  [AArch64][llvm] Restrict STSHH decoding to valid policy encodings

`STSHH` only uses the `op2 == 00x` encodings, where bit 5 selects the
keep/strm policy. The TableGen definition was modeling the whole `op2`
field as a 3-bit policy operand, which made the disassembler also match
`op2 == 110` and `op2 == 111`.

Constrain STSHH to `op2 == 00x` by making the policy operand one bit
wide and fixing bits 7:6 to zero. This will avoid decode clashes in
future if these bits are set.



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