[all-commits] [llvm/llvm-project] 971ad5: [AArch64][GlobalISel] Add handling for scalar sqne...

[Joshua Rodriguez via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 971ad593d6a2df38ab3854dc3bc440eab8416057
      https://github.com/llvm/llvm-project/commit/971ad593d6a2df38ab3854dc3bc440eab8416057
  Author: Joshua Rodriguez <josh.rodriguez at arm.com>
  Date:   2026-05-29 (Fri, 29 May 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/test/CodeGen/AArch64/arm64-int-neon.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Add handling for scalar sqneg intrinsic (#200211)

Scalar versions of the intrinsic must be performed on FPR banks. To
ensure this happens, coerce the source and destination registers to be
on FPR.



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