[all-commits] [llvm/llvm-project] 50b341: [AMDGPU] Add MemoryPipeline scheduling to Coexec s...

[Jeffrey Byrnes via All-commits]

  Branch: refs/heads/users/jebyrnes/FenceWaitRebase2
  Home:   https://github.com/llvm/llvm-project
  Commit: 50b341fc95903076d8283116982817d11eacdcac
      https://github.com/llvm/llvm-project/commit/50b341fc95903076d8283116982817d11eacdcac
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir

  Log Message:
  -----------
  [AMDGPU] Add MemoryPipeline scheduling to Coexec sched

Change-Id: I52c476834155823d1ba998cdbbcb3ad6a7e6f2f5


  Commit: 6c87941a9d38de8cf36c276d0ed9ab31c3d176ae
      https://github.com/llvm/llvm-project/commit/6c87941a9d38de8cf36c276d0ed9ab31c3d176ae
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h

  Log Message:
  -----------
  Add a comment

Change-Id: I447f7f1fb185b18924cfd98249b5a0a05fef2484


  Commit: 88817729b47781743ea13769592cb00ab5df72a2
      https://github.com/llvm/llvm-project/commit/88817729b47781743ea13769592cb00ab5df72a2
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h

  Log Message:
  -----------
  Make fence heuristic work bottom-up

Change-Id: I629cbc8905b87a962e8b123287e5f60a3154df6b


  Commit: 646ff7544bc6aec14f033169c8498d0468198ab4
      https://github.com/llvm/llvm-project/commit/646ff7544bc6aec14f033169c8498d0468198ab4
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp

  Log Message:
  -----------
  Add back tryLatency

Change-Id: I12d4f255c48ed77ba927eb3b192e5903f1f5e24f


  Commit: ddef328eea399aa8993e1824e5765984e957035d
      https://github.com/llvm/llvm-project/commit/ddef328eea399aa8993e1824e5765984e957035d
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp

  Log Message:
  -----------
  Add comment

Change-Id: I2180bba631fe4a01ed3c3fbcfa8c19cbefa84133


  Commit: a3ec9c389ce3df89f9bcd062a0f0e10bad6d79fc
      https://github.com/llvm/llvm-project/commit/a3ec9c389ce3df89f9bcd062a0f0e10bad6d79fc
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir

  Log Message:
  -----------
  Adrress comments from https://github.com/llvm/llvm-project/pull/188658

Change-Id: Ia94c567a753168c1ffa16dc5d91195e7dd0ba044


  Commit: d858addf10443df323b5b2920419d1eb08129708
      https://github.com/llvm/llvm-project/commit/d858addf10443df323b5b2920419d1eb08129708
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-05-28 (Thu, 28 May 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/coexec-block-carried-latency.mir
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir

  Log Message:
  -----------
  Update tests

Change-Id: Ided5a4e6968d4670d1fd09bcb327a75a25273d4e


Compare: https://github.com/llvm/llvm-project/compare/428e06882fb8...d858addf1044

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